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1. 发明申请

WO2018080751A1 MATRIX PROCESSOR WITH LOCALIZED MEMORY 审中-公开
标题翻译：具有本地化内存的矩阵处理器
公开(公告)号：WO2018080751A1
公开(公告)日：2018-05-03
申请号：PCT/US2017/055271
申请日：2017-10-05
申请人： WISCONSIN ALUMNI RESEARCH FOUNDATION
发明人： LI, Jing , ZHANG, Jialiang
IPC分类号： G06F9/30 , G06F9/48
CPC分类号： G06F15/80 , G06F3/0613 , G06F3/0647 , G06F3/0683 , G06F13/28 , G06F15/7821 , Y02D10/12 , Y02D10/13 , Y02D10/14
摘要： A computer architecture provides for multiple processing elements arranged in logical rows and columns to share local memory associated with each column and row. This sharing of memory on a row and column basis provides for efficient matrix operations such as matrix multiplications such as can be used in a variety of processing algorithms to reduce dataflow between external memory and the local memories and/or to reduce the size of necessary local memories for efficient processing.
摘要翻译：计算机体系结构提供以逻辑行和列排列的多个处理单元，以共享与每一列和每行相关联的本地存储器。这种基于行和列的存储器共享提供了有效的矩阵操作，诸如矩阵乘法，诸如可用于各种处理算法中以减少外部存储器和本地存储器之间的数据流和/或减小必要的本地回忆高效处理。

2. 发明申请

WO2017192415A1 CLONING COMPUTING DEVICE CONTAINERS 审中-公开
标题翻译：克隆计算装置容器
公开(公告)号：WO2017192415A1
公开(公告)日：2017-11-09
申请号：PCT/US2017/030333
申请日：2017-05-01
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： REUTHER, Lars , HEPKIN, David A. , BROAS, Kevin M. , STARKS, John A. , KISHAN, Arun U. , RICHARDSON, John J. , IYIGUN, Mehmet , BAK, Yevgeniy M.
IPC分类号： G06F9/48
CPC分类号： G06F9/45558 , G06F3/0604 , G06F3/0632 , G06F3/065 , G06F3/0665 , G06F3/0683 , G06F9/4843 , G06F2009/45562 , G06F2009/45583
摘要： An operating system running on a computing device, also referred to herein as a host device, uses containers for hardware resource partitioning. A container can include one or more of various different components, such as a base operating system, a user-mode environment, an application, virtual devices, combinations thereof, and so forth. One or more container templates are maintained for a computing device, and in response to a request to create a new container, a template container is copied into memory of the computing device to create the new container. The template container includes the various components of the container, and these components are copied into memory of the computing device rather than being launched or started one after the other. Thus, time need not be expended starting the various components included in the container - the components are just copied into memory as a new container.
摘要翻译：在计算设备上运行的操作系统（在此也被称为主机设备）使用容器进行硬件资源划分。容器可以包括一个或多个各种不同的组件，诸如基本操作系统，用户模式环境，应用程序，虚拟设备及其组合等等。为计算设备维护一个或多个容器模板，并且响应于创建新容器的请求，将模板容器复制到计算设备的存储器中以创建新容器。模板容器包括容器的各种组件，并且这些组件被复制到计算设备的存储器中，而不是一个接一个地启动或启动。因此，不需要花费时间来启动包含在容器中的各种组件 - 组件仅作为新的容器复制到内存中。

3. 发明申请

WO2017143299A1 ADAPTIVE BUFFERING 审中-公开
标题翻译：适应性缓冲
公开(公告)号：WO2017143299A1
公开(公告)日：2017-08-24
申请号：PCT/US2017/018520
申请日：2017-02-17
申请人： INVENSENSE, INC
发明人： SOLBACH, Ludger , MURGIA, Carlo
IPC分类号： G06F1/32
CPC分类号： G06F13/1673 , G06F3/061 , G06F3/0656 , G06F3/0683 , G11C19/28 , G11C21/00
摘要： In a method of adaptive buffering in a mobile device having a host processor and a sensor processor coupled with the host processor, the sensor processor is used to buffer data received from a sensor that is operated by the sensor processor. The data is buffered by the sensor processor into a circular data buffer. Responsive to the sensor processor detecting triggering data within the received data: a first adaptive data buffering action is initiated with respect to the data received from the sensor operated by the sensor processor; a second adaptive data buffering action is initiated with respect to second data received from a second sensor of the mobile device; and a command is sent from the sensor processor to a second processor.
摘要翻译：在具有主处理器和与主处理器耦合的传感器处理器的移动装置中的自适应缓冲的方法中，传感器处理器用于缓冲从由传感器操作的传感器接收的数据处理器。数据由传感器处理器缓冲到循环数据缓冲区中。响应于传感器处理器检测到所接收的数据内的触发数据：相对于从由传感器处理器操作的传感器接收的数据启动第一自适应数据缓冲动作; 关于从移动设备的第二传感器接收的第二数据发起第二自适应数据缓冲动作; 并且从传感器处理器向第二处理器发送命令。

4. 发明申请

WO2017132790A1 数据恢复方法及存储设备审中-公开
公开(公告)号：WO2017132790A1
公开(公告)日：2017-08-10
申请号：PCT/CN2016/073038
申请日：2016-02-01
申请人：华为技术有限公司
发明人：伏高顶 , 江勇 , 母子安
IPC分类号： G06F11/14
CPC分类号： G06F11/1469 , G06F3/06 , G06F3/0604 , G06F3/064 , G06F3/0659 , G06F3/0683 , G06F11/1446 , G06F11/1464 , G06F17/30088 , G06F2201/84
摘要：一种数据恢复方法及存储设备，用于提高数据恢复效率。所述方法包括：接收服务器发送的待恢复文件包括的数据块的第一物理地址(108)；根据待恢复文件所包括的数据块的第一物理地址查找恢复快照，根据恢复快照中记录的被修改数据块的第一物理地址与被修改数据块在资源卷中的第二物理地址的对应关系，获取待恢复文件中的被修改数据块在资源卷中的第二物理地址，所述恢复快照为用于恢复待恢复文件的快照卷(110)；根据待恢复文件中的被修改数据块在资源卷中的第二物理地址，在源卷中恢复待恢复文件(111)。

5. 发明申请

WO2017092087A1 INTELLIGENT CODED MEMORY ARCHITECTURE WITH ENHANCED ACCESS SCHEDULER 审中-公开
标题翻译：具有增强型访问调度器的智能编码存储器架构
公开(公告)号：WO2017092087A1
公开(公告)日：2017-06-08
申请号：PCT/CN2015/098231
申请日：2015-12-22
申请人： HUAWEI TECHNOLOGIES CO., LTD.
发明人： LUAN, Hao , GATHERER, Alan , VISHWANATH, Sriram , HUNGER, Casen , JAIN, Hardik
IPC分类号： G06F13/16
CPC分类号： G06F3/0611 , G06F3/0659 , G06F3/0683 , G06F12/02
摘要： A method, system, and architecture for efficiently accessing data in a memory shared by multiple processor cores that reduces the probability of bank conflicts and decreases latency is provided. The method for accessing data in a memory includes determining, by a scheduler, a read pattern for reading data from memory to serve requests in a plurality of bank queues, the memory comprising a plurality of memory banks and a plurality of coding banks, the coding banks storing a coded version of at least some of the data stored in the plurality of memory banks; reading a first data from a first memory bank; reading coded data from one of the coding banks; and determining the second data according to the coded data and the first data.
摘要翻译：提供了用于高效地访问由多个处理器核共享的存储器中的数据的方法，系统和体系结构，其减少了存储体冲突的可能性并且减少了等待时间。用于访问存储器中的数据的方法包括由调度器确定用于从存储器读取数据以服务于多个库队列中的请求的读取模式，所述存储器包括多个存储器库和多个编码库，所述编码存储所述多个存储体中存储的至少一些数据的编码版本的存储体; 从第一存储体读取第一数据; 从一个编码库读取编码数据; 并根据编码数据和第一数据确定第二数据。

6. 发明申请

WO2017026661A1 ELECTRONIC DEVICE AND METHOD FOR STORING SECURITY INFORMATION THEREOF 审中-公开
标题翻译：用于存储其安全信息的电子设备和方法
公开(公告)号：WO2017026661A1
公开(公告)日：2017-02-16
申请号：PCT/KR2016/007320
申请日：2016-07-06
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： SEO, Won Suk , MOON, Sung Whan , LEE, Chang Wook , HWANG, Sung Oh , BHUPINDER, Singh , XIE, Chongyang , CHEN, Geng , KATTIMANI, Muralidhar , PATEL, Naman , SHUKLA, Sambit Kumar , SAPUTRA, Sia Jeffry , HAVIN, Victor , KIM, Sung Gyu , PARK, Min Woo , RYU, Jae Hoon , LEE, Seung Hoon , JANG, Dong Ho
IPC分类号： G06F21/79 , G06F21/60
CPC分类号： G06F3/0623 , G06F3/0659 , G06F3/0683 , G06F21/6218 , G06F21/645
摘要： An apparatus and method for storing security information are provided. The apparatus is generally an electronic device that includes a memory configured to include a secured region to store security information and a processor configured to electrically connect with the memory. The processor is further configured to execute an application program configured to store the security information in a first secured region, to receive a request to store the security information from the application program, and to store the security information in a second secured region different from the first secured region in response to the request.
摘要翻译：提供了一种用于存储安全信息的装置和方法。该设备通常是电子设备，其包括被配置为包括用于存储安全信息的安全区域的存储器和被配置为与存储器电连接的处理器。处理器还被配置为执行被配置为将安全信息存储在第一安全区域中的应用程序，以接收来自应用程序的存储安全信息的请求，并将安全信息存储在不同于第一个安全区域响应请求。

7. 发明申请

WO2016205070A1 ATTRIBUTING CONSUMED STORAGE CAPACITY AMONG ENTITIES STORING DATA IN A STORAGE ARRAY 审中-公开
标题翻译：在存储阵列存储数据的实体中归档消费存储容量
公开(公告)号：WO2016205070A1
公开(公告)日：2016-12-22
申请号：PCT/US2016/036693
申请日：2016-06-09
申请人： PURE STORAGE, INC.
发明人： CAO, Jianting , HARRIMAN, Martin , HAYES, John , SANDVIG, Cary
IPC分类号： G06F3/06
CPC分类号： G06F3/0604 , G06F3/0608 , G06F3/0619 , G06F3/0629 , G06F3/0644 , G06F3/065 , G06F3/0662 , G06F3/0665 , G06F3/067 , G06F3/0683 , G06F3/0689 , G06F2003/0692
摘要： Attributing consumed storage capacity among entities storing data in a storage array includes: identifying a data object stored in the storage array and shared by a plurality of entities, where the data object occupies an amount of storage capacity of the storage array; and attributing to each entity a fractional portion of the amount of storage capacity occupied by the data object.
摘要翻译：在存储阵列中存储数据的实体中，消耗的存储容量的归属包括：识别存储在存储阵列中并由多个实体共享的数据对象，其中数据对象占据存储阵列的存储容量的量; 并将每个实体归因于数据对象占用的存储容量的一部分。

8. 发明申请

WO2016202364A1 A METHOD OF LIVE MIGRATION 审中-公开
标题翻译：一种移动方法
公开(公告)号：WO2016202364A1
公开(公告)日：2016-12-22
申请号：PCT/EP2015/063417
申请日：2015-06-16
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
发明人： ROOZBEH, Amir , MONTEIRO SOARES, Joao , TURULL, Daniel
IPC分类号： G06F9/48
CPC分类号： G06F3/0647 , G06F3/0605 , G06F3/0617 , G06F3/0629 , G06F3/0658 , G06F3/067 , G06F3/0683 , G06F9/46 , G06F9/4856
摘要： A method of migrating of an application from a source host to a destination host, wherein the application is associated with a plurality of memory pages, the source host comprises a first instance of the application and a source memory region, and each memory page has an associated source memory block in the source memory region, the method comprising: at the destination host, reserving (18) a destination memory region such that each memory page has an associated destination memory block in the destination memory region, (19) a second instance of the application at the destination host; on receipt of an input (20) to the application, processing (22, 23) the input in parallel at the first and second instances at respective source and destination hosts: at the source host, if the processing requires a read or a write call to a memory page, respectively reading (24) from or writing (25) to the associated source memory block; the destination host, if the processing requires a write call to a memory page, writing (28) to the associated destination memory block and if the processing requires a read call to a memory page, sending the read call to the source host requesting that the source host read (26) the memory page from the associated source memory block and provide the memory page to the destination host, and, on receipt of the memory page by the destination host, writing (27) the memory page to the associated destination memory block.
摘要翻译：一种将应用从源主机迁移到目的主机的方法，其中所述应用与多个存储器页面相关联，所述源主机包括所述应用的第一实例和源存储器区域，并且每个存储器页面具有所述方法包括：在所述目的地主机处，保留（18）目的地存储区域，使得每个存储器页面在所述目的地存储器区域中具有相关联的目的地存储器块，（19）第二实例的目的地主机的应用程序; 在接收到应用程序的输入（20）时，处理（22,23）在相应的源和目的地主机处的第一和第二实例的并行输入：在源主机处，如果处理需要读或写调用分别从存储器页面读取（24）或写入（25）到相关联的源存储器块; 目的地主机，如果处理需要对存储器页面的写入调用，则将（28）写入相关联的目的地存储器块，并且如果处理需要对存储器页面的读取调用，则将该读取呼叫发送到源主机，源主机从相关联的源存储器块读取（26）存储器页面，并将存储器页面提供给目标主机，并且在目的地主机接收到存储器页面时，将存储器页面写入（27）到相关联的目的地存储器块。

9. 发明申请

WO2016195714A1 METHOD AND APPARATUS OF SHARED STORAGE BETWEEN MULTIPLE CLOUD ENVIRONMENTS 审中-公开
标题翻译：多云环境下共享存储的方法与装置
公开(公告)号：WO2016195714A1
公开(公告)日：2016-12-08
申请号：PCT/US2015/034484
申请日：2015-06-05
申请人： HITACHI, LTD.
发明人： NAKAJIMA, Akio , DEGUCHI, Akira
IPC分类号： G06F15/16
CPC分类号： G06F3/065 , G06F3/06 , G06F3/0619 , G06F3/0683 , G06F9/50 , G06F11/14 , G06F17/30 , G06F17/30088
摘要： A computer system is coupled to a first storage system in a first site and a second storage system in a second site. The computer system comprises: a memory configured to store information which indicates that data in each segment of a plurality of segments of a logical unit is stored in the first storage system or the second storage system; and a processor configured to: receive an instruction to deploy an application, the instruction including access characteristic of the application; and determine if a snapshot of the logical volume is to be created either in the first storage system or the second storage system based on the access characteristic of the application and the information stored in the memory.
摘要翻译：计算机系统耦合到第一站点中的第一存储系统和第二站点中的第二存储系统。计算机系统包括：存储器，被配置为存储指示逻辑单元的多个段的每个段中的数据存储在第一存储系统或第二存储系统中的信息; 以及处理器，被配置为：接收部署应用的指令，所述指令包括所述应用的访问特性; 并且基于应用的访问特性和存储在存储器中的信息来确定在第一存储系统或第二存储系统中是否要创建逻辑卷的快照。

10. 发明申请

WO2016182596A1 MEMORY CIRCUIT USING DYNAMIC RANDOM ACCESS MEMORY ARRAYS 审中-公开
标题翻译：使用动态随机访问存储器阵列的存储器电路
公开(公告)号：WO2016182596A1
公开(公告)日：2016-11-17
申请号：PCT/US2015/063740
申请日：2015-12-03
申请人： CAMBOU, Bertrand, F.
发明人： CAMBOU, Bertrand, F.
IPC分类号： G06F17/30
CPC分类号： G06F12/1408 , G06F3/0622 , G06F3/0653 , G06F3/0683 , G06F21/00 , G06F21/79 , G06F2212/1016 , G11C11/4076 , G11C11/4078 , G11C15/043 , H04L9/0894 , H04L9/3226 , Y02D10/13
摘要： A memory circuit using dynamic random access memory (DRAM) arrays. The DRAM arrays can be configured as CAMs or RAMs on the same die, with the control circuitry for performing comparisons located outside of the DRAM arrays. In addition, DRAM arrays can be configured for secure authentication where, after the first authentication performed with a non- volatile secure element, subsequent authentications can be performed by the DRAM array. Input patterns can be loaded into a DRAM array by loading logic state ones ("1") into each of the plurality of input data bit lines in each of the columns in the DRAM array and shunting one or more of the plurality of input data bit lines in the DRAM array corresponding to logic state zeroes ("0') in the input pattern.
摘要翻译：一种使用动态随机存取存储器（DRAM）阵列的存储器电路。 DRAM阵列可以被配置为同一芯片上的CAM或RAM，控制电路用于执行位于DRAM阵列外部的比较。此外，DRAM阵列可以被配置用于安全认证，其中在用非易失性安全元件执行的第一认证之后，可以由DRAM阵列执行后续认证。可以通过将逻辑状态（“1”）加载到DRAM阵列中的每个列中的多个输入数据位线中的每一个中并将多个输入数据位中的一个或多个位分流来将输入模式加载到DRAM阵列中 DRAM阵列中的线对应于输入模式中的逻辑状态零（“0”）。

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