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1. 发明申请

WO2022076060A2 HETEROGENEOUS HEIGHT LOGIC CELL ARCHITECTURE 审中-公开
公开(公告)号：WO2022076060A2
公开(公告)日：2022-04-14
申请号：PCT/US2021/043542
申请日：2021-07-28
申请人： QUALCOMM INCORPORATED
发明人： LIM, Hyeokjin , BOYNAPALLI, Venugopal , VANG, Foua , KANG, Seung Hyuk
IPC分类号： H01L27/02 , G06F30/394 , H01L27/118 , H01L2027/11875 , H01L2027/11881 , H01L27/0207 , H01L27/11807
摘要： A MOS IC includes first and second sets of adjacent transistor logic, each of which include collinear gate interconnects extending in a first direction with the same gate pitch. The first set of transistor logic has a first cell height h1 and a first number of Mx layer tracks that extend unidirectionally in a second direction orthogonal to the first direction. The second set of transistor logic has a second cell height h2 and a second number of Mx layer tracks that extend unidirectionally in the second direction, where h2 > h1 and the second number of Mx layer tracks is greater than the first number of Mx layer tracks. At least one of a height ratio hR=h2/h1 is a non-integer value or a subset of the first set of transistor logic and a subset of the second set of transistor logic are within one logic cell.

2. 发明申请

WO2017172148A2 A METAL OXIDE SEMICONDUCTOR CELL DEVICE ARCHITECTURE WITH MIXED DIFFUSION BREAK ISOLATION TRENCHES 审中-公开
标题翻译：具有混合扩散隔离栅的金属氧化物半导体器件结构
公开(公告)号：WO2017172148A2
公开(公告)日：2017-10-05
申请号：PCT/US2017/019470
申请日：2017-02-24
申请人： QUALCOMM INCORPORATED
发明人： CHEN, Xiangdong , BOYNAPALLI, Venugopal , SAHU, Satyanarayana , LIM, Hyeokjin , GUPTA, Mukul
IPC分类号： H01L27/02 , H01L27/118
摘要： A standard cell IC includes pMOS transistors in a pMOS region of a MOS device. The pMOS region extends between a first cell edge and a second cell edge opposite the first cell edge. The standard cell IC further includes nMOS transistors in an nMOS region of the MOS device. The nMOS region extends between the first cell edge and the second cell edge. The standard cell IC further includes at least one single diffusion break located in an interior region between the first cell edge and the second cell edge that extends across the pMOS region and the nMOS region to separate the pMOS region into pMOS subregions and the nMOS region into nMOS subregions. The standard cell IC includes a first double diffusion break portion at the first cell edge. The standard cell IC further includes a second double diffusion break portion at the second cell edge.
摘要翻译：标准单元IC包括MOS器件的pMOS区域中的pMOS晶体管。 pMOS区域在第一单元边缘和与第一单元边缘相对的第二单元边缘之间延伸。标准单元IC还包括MOS器件的nMOS区域中的nMOS晶体管。 nMOS区域在第一单元边缘和第二单元边缘之间延伸。标准单元IC还包括位于第一单元边缘与第二单元边缘之间的内部区域中的至少一个单个扩散中断，所述内部区域延伸穿过pMOS区域和nMOS区域以将pMOS区域分成pMOS子区域并且将nMOS区域分成 nMOS次区域。标准单元IC包括在第一单元边缘处的第一双扩散中断部分。标准单元IC还包括在第二单元边缘的第二个双扩散中断部分。

3. 发明申请

WO2016073178A2 SHARED REPAIR REGISTER FOR MEMORY REDUNDANCY 审中-公开
标题翻译：共享维修注册记忆冗余
公开(公告)号：WO2016073178A2
公开(公告)日：2016-05-12
申请号：PCT/US2015/056218
申请日：2015-10-19
申请人： QUALCOMM INCORPORATED
发明人： BOYNAPALLI, Venugopal , ZAFAR, Bilal
IPC分类号： G11C29/00
CPC分类号： G11C29/70 , G11C11/419 , G11C29/765 , G11C29/808 , G11C29/886
摘要： A cross-bar switch is provided that enables each master from a plurality of masters to read from and write to selected memories from an array of memories. A logic circuit controls the cross-bar switch so that redundancy for the memories is provided by a shared redundancy storage element.
摘要翻译：提供了一种横杆开关，其使得来自多个主机的每个主机能够从存储器阵列中读取和写入所选择的存储器。逻辑电路控制交叉开关，使得存储器的冗余由共享冗余存储元件提供。

4. 发明申请

WO2019040240A1 HIGH-SPEED SOFT-EDGE SENSE-AMPLIFIER-BASED FLIP-FLOP 审中-公开
公开(公告)号：WO2019040240A1
公开(公告)日：2019-02-28
申请号：PCT/US2018/044687
申请日：2018-07-31
申请人： QUALCOMM INCORPORATED
发明人： NARAYANAN, Venkat , YE, Qi , SRIVASTAVA, Manish , BOYNAPALLI, Venugopal
IPC分类号： H03K3/013 , H03K3/356 , H03K3/3562
CPC分类号： H03K3/35625 , H03K3/013 , H03K3/356139
摘要： A flip-flop (100) is provided that includes a sense-amplifier-based master latch (105) clocked by a first edge of a delayed version of a clock signal (120out). A slave latch (110) includes a cross-coupled pair of logic gates for latching a data output signal responsive to a second edge of the clock signal (clk).

5. 发明申请

WO2018080737A1 SEMI-DATA GATED FLOP WITH LOW CLOCK POWER/LOW INTERNAL POWER WITH MINIMAL AREA OVERHEAD 审中-公开
标题翻译：半峰值功率/低内部功率的半数字门控触发器，带有最小面积的开口
公开(公告)号：WO2018080737A1
公开(公告)日：2018-05-03
申请号：PCT/US2017/054769
申请日：2017-10-02
申请人： QUALCOMM INCORPORATED
发明人： RASOULI, Seid Hadi , CHEN, Xiandong , BOYNAPALLI, Venugopal
IPC分类号： H03K19/00 , H03K3/012 , H03K3/356
CPC分类号： H03K3/012 , H03K3/356121 , H03K3/356156 , H03K19/0016 , H03K19/20
摘要： Methods and systems for clock gating are described herein. In certain aspects, a method for clock gating includes receiving an input signal of a flip-flop and an output signal of the flip-flop, and passing a clock signal to an input of a gate in the flip-flop if the input signal and the output signal have different logic values or both the input signal and the output signal have a logic value of zero. The method also includes gating the clock signal if both the input signal and the output signal have a logic value of one.
摘要翻译：这里描述了用于时钟门控的方法和系统。在某些方面，用于时钟门控的方法包括接收触发器的输入信号和触发器的输出信号，并且如果输入信号和触发器的时钟信号和触发器的时钟信号传递到触发器中的门的输入输出信号具有不同的逻辑值，或者输入信号和输出信号都具有零的逻辑值。该方法还包括如果输入信号和输出信号都具有逻辑值1，则选通时钟信号。

6. 发明申请

WO2017172148A3 A METAL OXIDE SEMICONDUCTOR CELL DEVICE ARCHITECTURE WITH MIXED DIFFUSION BREAK ISOLATION TRENCHES 审中-公开
公开(公告)号：WO2017172148A3
公开(公告)日：2017-10-05
申请号：PCT/US2017/019470
申请日：2017-02-24
申请人： QUALCOMM INCORPORATED
发明人： CHEN, Xiangdong , BOYNAPALLI, Venugopal , SAHU, Satyanarayana , LIM, Hyeokjin , GUPTA, Mukul
IPC分类号： H01L27/02 , H01L27/118
摘要： A standard cell IC includes pMOS transistors in a pMOS region (316) of a MOS device and nMOS transistors in an nMOS region (318) of the MOS device. The pMOS and nMOS regions extend between a first cell edge (304a) and a second cell edge (304b). The standard cell IC further includes at least one single diffusion break (312) located in an interior region between the first cell edge and the second cell edge that extends across the pMOS region and the nMOS region to separate the pMOS region into pMOS subregions and the nMOS region into nMOS subregions. The standard cell IC includes a first double diffusion break portion (314') at the first cell edge (304a) and a second double diffusion break portion (314) at the second cell edge (304b).

7. 发明申请

WO2017147895A1 LOW-AREA LOW CLOCK-POWER FLIP-FLOP 审中-公开
标题翻译：低面积低功耗FLIP-FLOP
公开(公告)号：WO2017147895A1
公开(公告)日：2017-09-08
申请号：PCT/CN2016/075596
申请日：2016-03-04
申请人： QUALCOMM INCORPORATED , RASOULI, Seid Hadi , KANG, Hananel , CAI, Yanfei , CHEN, Xiangdong , BOYNAPALLI, Venugopal
发明人： RASOULI, Seid Hadi , KANG, Hananel , CAI, Yanfei , CHEN, Xiangdong , BOYNAPALLI, Venugopal
IPC分类号： H03K3/356 , H03K3/012 , H03K3/3562
CPC分类号： H03K3/012 , H03K3/35625
摘要： In one example, an apparatus may be a flip-flop that includes a slave latch and a master latch. The master latch includes a first logic element in the master latch. The first logic element includes a first transistor. The first transistor is shared by a second logic element in one of the master latch or the slave latch. The first transistor provides a clocking signal input to the first logic element and the second logic element.
摘要翻译：在一个示例中，装置可以是包括从锁存器和主锁存器的触发器。主锁存器包括主锁存器中的第一逻辑元件。第一逻辑元件包括第一晶体管。第一晶体管由主锁存器或从锁存器中的一个中的第二逻辑元件共享。第一晶体管向第一逻辑元件和第二逻辑元件提供时钟信号输入。

8. 发明申请

WO2013138467A1 POWER GATING FOR HIGH SPEED XBAR ARCHITECTURE 审中-公开
标题翻译：用于高速XBAR架构的功率增益
公开(公告)号：WO2013138467A1
公开(公告)日：2013-09-19
申请号：PCT/US2013/030884
申请日：2013-03-13
申请人： QUALCOMM INCORPORATED
发明人： RAO, Hari M. , TERZIOGLU, Esin , BOYNAPALLI, Venugopal
IPC分类号： G06F1/32
CPC分类号： G06F1/3253 , Y02D10/151
摘要： A low power interconnect allows client to client communication using an XBAR architecture. An XBAR compiler generates chip designs with XBAR data paths structured to reduce energy consumption and delay. Repeaters inserted into XBAR data paths reduce resistance capacitance (RC) delays so that a design can support desired frequency specifications along a path. Dynamic power consumption is reduced by inserting latch repeaters in the XBAR track. The latch repeaters each include a transmission gate and a latch. Select circuitry couples selected clients to a path. Enable circuitry opens the transmission gates located on the path between the selected clients. Latch repeaters that are not enabled on a given communication cycle gate off the unused portions of the path and maintain the data that was latched on a previous cycle.
摘要翻译：低功耗互连允许客户端使用XBAR架构进行客户端通信。 XBAR编译器生成具有XBAR数据路径的芯片设计，以减少能耗和延迟。插入XBAR数据路径的中继器可以减少电阻（RC）延迟，从而使设计能够沿着路径支持所需的频率规格。通过在XBAR轨道中插入锁存中继器来降低动态功耗。锁存中继器各自包括传输门和锁存器。选择电路将选定的客户端耦合到路径。启用电路打开位于所选客户端之间路径上的传输门。在给定通信周期中未启用的锁存中继器将关闭路径的未使用部分，并维护在先前周期中锁存的数据。

9. 发明申请

WO2020214827A1 LOW-POWER MEMORY 审中-公开
公开(公告)号：WO2020214827A1
公开(公告)日：2020-10-22
申请号：PCT/US2020/028543
申请日：2020-04-16
申请人： QUALCOMM INCORPORATED
发明人： JUNG, Chulmin , KIM, Keejong , JUNG, Changho , BOYNAPALLI, Venugopal
IPC分类号： G11C11/419 , G11C7/06
摘要： A charge-transfer transistor couples between a bit line and a sense node for a sense amplifier. During a read operation, a charge -transfer driver drives a gate voltage of the charge-transfer transistor to control whether the charge -transfer transistor conducts during a charge-transfer period. Prior to the charge-transfer period, a bitcell is coupled to the bit line to drive a bitcell-effected voltage on to the bit line. The charge- transfer driver drives the gate voltage such that the charge-transfer transistor only conducts when the bitcell-effected voltage equals a pre-charge voltage for the bit line.

10. 发明申请

WO2019152093A1 A NOVEL STANDARD CELL ARCHITECTURE FOR GATE TIE-OFF 审中-公开
公开(公告)号：WO2019152093A1
公开(公告)日：2019-08-08
申请号：PCT/US2018/064371
申请日：2018-12-07
申请人： QUALCOMM INCORPORATED
发明人： CHEN, Xiangdong , BOYNAPALLI, Venugopal , LIM, Hyeokjin
IPC分类号： H01L27/02 , H01L27/118
摘要： According to certain aspects of the present disclosure, a chip includes a first gate, a second gate, a first source, a first source contact disposed on the first source, a metal interconnect above the first source contact and the first gate, a first gate contact electrically coupling the first gate to the metal interconnect, and a first via electrically coupling the first source contact to the metal interconnect. The chip also includes a power rail, and a second via electrically coupling the first source contact to the power rail. The second gate is between the first source and the first gate, and the metal interconnect passes over the second gate.

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