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1. 发明申请

WO2019078999A1 CONTROLLER HARDWARE AUTOMATION FOR HOST-AWARE PERFORMANCE BOOSTER 审中-公开
公开(公告)号：WO2019078999A1
公开(公告)日：2019-04-25
申请号：PCT/US2018/052236
申请日：2018-09-21
申请人： QUALCOMM INCORPORATED
发明人： SHIN, Hyunsuk , TEB, David , VUONG, Hung
IPC分类号： G06F13/12
摘要： In a conventional system with a UFS device connected to a UFS host implementing HPB features, a UFS driver software generates commands, e.g., read and write commands, for the UFS device to perform. The commands include both physical and logical addresses of the UFS device. Typically, the UFS driver software is software based. Therefore, there is much overhead associated with implementing the HPB. To address this issue, it is proposed to enable a hardware based host controller to perform operations related to the HPB. In this way, the performance of a system may be improved.

2. 发明申请

WO2019022952A1 POWER DOWN MODE FOR UNIVERSAL FLASH STORAGE (UFS) 审中-公开
公开(公告)号：WO2019022952A1
公开(公告)日：2019-01-31
申请号：PCT/US2018/041628
申请日：2018-07-11
申请人： QUALCOMM INCORPORATED
发明人： SHIN, Hyunsuk , REYNOLDS, Todd Christopher , VUONG, Hung
IPC分类号： G06F1/32 , G11C5/14
摘要： Systems and method are directed to Universal Flash Storage (UFS) memory system configured to support deep power-down modes wherein the UFS memory system is not required to be responsive to commands received from a host device coupled to the UFS memory system. Correspondingly, in the deep power-down modes, a link or interface between the UFS memory system and the host device may also be powered down. The UFS memory system may enter the deep power-down modes based on a command received from the host device or a hardware reset assertion, and exit the deep power-down modes based on a hardware reset de-assertion or power cycling. While in deep power-down modes, the power consumption of the UFS memory device is substantially lower than the power consumption of the UFS memory device in conventional power modes.

3. 发明申请

WO2017112357A1 COMPRESSED CACHING OF A LOGICAL-TO-PHYSICAL ADDRESS TABLE FOR NAND-TYPE FLASH MEMORY 审中-公开
标题翻译： NAND型闪存的逻辑 - 物理地址表的压缩高速缓存
公开(公告)号：WO2017112357A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/063878
申请日：2016-11-28
申请人： QUALCOMM INCORPORATED
发明人： CHUN, Dexter Tamio , SHIN, Hyunsuk
IPC分类号： G06F12/02 , G06F13/28
CPC分类号： G06F12/1009 , G06F12/0246 , G06F12/0802 , G06F12/1081 , G06F2212/1024 , G06F2212/401 , G06F2212/70 , G06F2212/7201
摘要： Systems and methods are disclosed for providing logical-to-physical address translation for a managed NAND flash storage device. One embodiment is a system comprising a system on chip (SoC) electrically coupled to a volatile memory device. A direct memory access (DMA) controller is electrically coupled to the SoC. The DMA controller receives a logical address to be translated to a physical address associated with a managed NAND flash storage device. A cache controller is configured to fetch from the volatile memory device a portion of a logical-to-physical (L2P) address table comprising a compressed version of a L2P mapping for the logical address. A compression block is configured to decompress the compressed version of the L2P mapping to determine the physical address corresponding to the logical address.
摘要翻译：公开了用于为托管NAND闪存设备提供逻辑到物理地址转换的系统和方法。一个实施例是包括电耦合到易失性存储器设备的片上系统（SoC）的系统。直接存储器存取（DMA）控制器电耦合到SoC。 DMA控制器接收将被转换为与托管NAND闪存设备相关联的物理地址的逻辑地址。高速缓存控制器被配置为从易失性存储器设备提取包括用于逻辑地址的L2P映射的压缩版本的逻辑到物理（L2P）地址表的一部分。压缩块被配置为解压缩L2P映射的压缩版本以确定对应于逻辑地址的物理地址。

4. 发明申请

WO2015034580A1 UNIFIED MEMORY CONTROLLER FOR HETEROGENEOUS MEMORY ON A MULTI-CHIP PACKAGE 审中-公开
标题翻译：用于多芯片封装异构存储器的统一存储器控制器
公开(公告)号：WO2015034580A1
公开(公告)日：2015-03-12
申请号：PCT/US2014/045983
申请日：2014-07-09
申请人： QUALCOMM INCORPORATED
发明人： SHIN, Hyunsuk , KIM, Jung Pill , CHUN, Dexter Tamio , SUH, Jungwon
IPC分类号： G06F13/16
CPC分类号： G06F3/0658 , G06F3/0604 , G06F3/0683 , G06F13/1694
摘要： An enhanced multi chip package (eMCP) is provided including a unified memory controller. The UMC is configured to manage different types of memory, such as NAND flash memory and DRAM on the eMCP. The UMC provides storage memory management, DRAM management, DRAM accessibility for storage memory management, and storage memory accessibility for DRAM management. The UMC also facilitates direct data copying from DRAM to storage memory and vice versa. The direct copying may be initiated by the UMC without interaction from a host, or may be initiated by a host.
摘要翻译：提供增强的多芯片封装（eMCP），包括统一的存储器控制器。 UMC被配置为管理不同类型的存储器，例如eMCP上的NAND闪存和DRAM。联电提供存储内存管理，DRAM管理，存储内存管理的DRAM可访问性和DRAM管理的存储存储器可访问性。 UMC还有助于从DRAM到存储器的直接数据复制，反之亦然。直接复制可以由UMC发起，而无需与主机的交互，也可以由主机发起。

5. 发明申请

WO2019032455A1 DATA BIT INVERSION TRACKING IN CACHE MEMORY TO REDUCE DATA BITS WRITTEN FOR WRITE OPERATIONS 审中-公开
公开(公告)号：WO2019032455A1
公开(公告)日：2019-02-14
申请号：PCT/US2018/045379
申请日：2018-08-06
申请人： QUALCOMM INCORPORATED
发明人： SHIN, Hyunsuk , KIM, Jung Pill , KIM, Sungryul
IPC分类号： G06F12/0804 , G06F12/0891 , G11C7/10 , G11C11/4063
CPC分类号： G11C11/1673 , G06F11/1012 , G06F11/1048 , G06F12/0895 , G06F13/4204 , G06F2212/6046 , G11C7/1006 , G11C11/1655 , G11C11/1675 , G11C11/4063 , G11C13/0069 , G11C15/00 , G11C15/02 , G11C15/046 , G11C29/50 , G11C2013/0076 , G11C2029/0411 , H03M13/2906
摘要： Data bit inversion tracking in cache memory to reduce data bits written for write operations is disclosed. In one aspect, a cache memory including a cache controller and a cache array is provided. The cache array includes one or more cache entries, each of which includes a cache data field and a bit change track field. The cache controller compares a current cache data word to a new data word to be written and stores a bit track change word representing the difference (i.e., inverted bits) between the current cache data word and the new data word in the bit change track field. By using the bit track change word stored in the bit change track field to determine whether fewer bit writes are required to write data in an inverted or a non-inverted form, power consumption can be reduced for write operations through reduced bit write operations.

6. 发明申请

WO2017222818A1 MANAGING REFRESH FOR FLASH MEMORY 审中-公开
标题翻译：管理FLASH存储器的刷新
公开(公告)号：WO2017222818A1
公开(公告)日：2017-12-28
申请号：PCT/US2017/036397
申请日：2017-06-07
申请人： QUALCOMM INCORPORATED
发明人： SHIN, Hyunsuk , HARDACKER, Robert , VUONG, Hung
IPC分类号： G11C16/34
摘要： Systems and method for a host-driven data refresh of a Flash memory include registers provided in the Flash memory for storing various settings related to refresh operations, such as, when to start/stop refreshing, target partitions in the memory, target start/end address ranges for refreshing, refresh algorithms, refresh rate requirements, etc. A host can control the various settings for start/stop refreshing, target partitions in the memory, target start/end address ranges for refreshing, refresh algorithms, through the corresponding registers; and the Flash memory can control various values related to refresh rate requirements through corresponding registers. In this manner, a standard platform or interface is provided within the Flash memory for refresh operations thereof.
摘要翻译：用于闪存的主机驱动数据刷新的系统和方法包括闪存中提供的寄存器，用于存储与刷新操作有关的各种设置，诸如何时开始/停止刷新，目标分区在存储器中，用于刷新的目标开始/结束地址范围，刷新算法，刷新率要求等。主机可以控制用于开始/停止刷新，存储器中的目标分区，用于刷新的目标开始/结束地址范围，刷新算法，通过相应的寄存器; 并且闪存可以通过相应的寄存器控制与刷新率要求有关的各种值。以这种方式，在闪存内提供标准平台或接口用于其刷新操作。

7. 发明申请

WO2017048377A1 MRAM INITIALIZATION DEVICES AND METHODS 审中-公开
标题翻译： MRAM初始化设备和方法
公开(公告)号：WO2017048377A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/044703
申请日：2016-07-29
申请人： QUALCOMM INCORPORATED
发明人： SHIN, Hyunsuk , KIM, Jung Pill , KIM, Sungryul
IPC分类号： G11C29/00 , G11C7/20 , G11C11/16 , G06F12/02
CPC分类号： G11C29/76 , G06F12/0238 , G06F2212/7207 , G06F2212/7209 , G11C7/20 , G11C11/1653 , G11C29/44 , G11C29/789 , G11C29/808 , G11C29/82 , G11C29/84
摘要： A device includes a redundant region of a magnetoresistive random access memory (MRAM) array that includes first memory cells. The device includes a data region of the MRAM array that includes second memory cells. The device includes a fail address region of the MRAM array, a first row of the fail address region including validity data, wherein the validity data includes multiple validity indicators, a last row indicator, or both.
摘要翻译：一种器件包括包含第一存储器单元的磁阻随机存取存储器（MRAM）阵列的冗余区域。该装置包括包括第二存储器单元的MRAM阵列的数据区域。该设备包括MRAM阵列的故障地址区域，包括有效性数据的故障地址区域的第一行，其中有效性数据包括多个有效性指示符，最后一行指示符，或两者。

8. 发明申请

WO2018089176A1 HARDWARE AUTOMATED LINK CONTROL OF DAISY-CHAINED STORAGE DEVICE 审中-公开
标题翻译：硬件自动链接控制DAISY-CHAINED存储设备
公开(公告)号：WO2018089176A1
公开(公告)日：2018-05-17
申请号：PCT/US2017/056850
申请日：2017-10-17
申请人： QUALCOMM INCORPORATED
发明人： SHIN, Hyunsuk , TEB, David , VUONG, Hung , GOPALAKRISHNAN, Venkatakrishnan
IPC分类号： G06F13/10 , G06F13/42
CPC分类号： G11C7/1003 , G06F3/0619 , G06F12/0246 , G06F13/102 , G06F13/1668 , G06F13/4247
摘要： In conventional systems with a plurality of UFS devices daisy-chained to a UFS host, a UFS device driver must be able to differentiate among the links, and send either link control messages or data/management (D/M) messages to a UFS host controller. This can make force the UFS device driver to be complicated and error prone. To address this issue, a host controller can provide a uniform view of a plurality of daisy-chained devices to a device driver of a host. For example, the host controller can be such that from the perspective of the device driver, each device can appear to be a point-to-point connected device. This can allow the device driver to use a same set of link control messages to control the links. In this way, the device driver can be simplified and thus less error prone.
摘要翻译：在具有多个菊花链连接到UFS主机的UFS设备的传统系统中，UFS设备驱动程序必须能够区分链路，并发送链路控制消息或数据/管理（D / M）消息到UFS主机控制器。这可能会迫使UFS设备驱动程序变得复杂且容易出错。为了解决这个问题，主机控制器可以向主机的设备驱动器提供多个菊花链设备的统一视图。例如，主控制器可以是从设备驱动程序的角度看，每个设备可以看起来是点对点连接的设备。这可以允许设备驱动程序使用同一组链接控制消息来控制链接。通过这种方式，设备驱动程序可以简化，从而减少错误。

9. 发明申请

WO2017039965A1 HARDWARE-ACCELERATED STORAGE COMPRESSION 审中-公开
标题翻译：硬件加速存储压缩
公开(公告)号：WO2017039965A1
公开(公告)日：2017-03-09
申请号：PCT/US2016/046019
申请日：2016-08-08
申请人： QUALCOMM INCORPORATED
发明人： SHIN, Hyunsuk , KIM, Jung Pill
IPC分类号： G06F3/06
CPC分类号： G06F3/0608 , G06F3/061 , G06F3/064 , G06F3/0644 , G06F3/0665 , G06F3/0685
摘要： Hardware-accelerated storage compression is disclosed. In one aspect, prior to writing an uncompressed data block to a storage device, a hardware compression accelerator provided in a storage controller compresses the uncompressed data block into a compressed data block and allocates the compressed data block to a physical data block in the storage device. The hardware compression accelerator then generates a modified logical block address (LBA) to link the uncompressed data block to the compressed data block. In another aspect, the hardware compression accelerator locates a compressed data block based on a corresponding modified LBA and decompresses the compressed data block into an uncompressed data block. By performing hardware-accelerated storage compression in the storage controller, it is possible to reduce processing overhead associated with conventional software-based compression systems and improve compression control over conventional storage-device-driven compression systems.
摘要翻译：公开了硬件加速存储压缩。一方面，在将未压缩数据块写入存储装置之前，设置在存储控制器中的硬件压缩加速器将未压缩数据块压缩为压缩数据块，并将压缩数据块分配给存储装置中的物理数据块。硬件压缩加速器然后生成修改的逻辑块地址（LBA），以将未压缩的数据块链接到压缩数据块。在另一方面，硬件压缩加速器基于相应的修改的LBA定位压缩数据块，并将压缩数据块解压缩为未压缩的数据块。通过在存储控制器中执行硬件加速存储压缩，可以减少与传统的基于软件的压缩系统相关联的处理开销，并且改进对传统的存储设备驱动的压缩系统的压缩控制。

10. 发明申请

WO2015187605A1 REMOVABLE MEMORY CARD TYPE DETECTION SYSTEMS AND METHODS 审中-公开
标题翻译：可拆卸存储卡类型检测系统和方法
公开(公告)号：WO2015187605A1
公开(公告)日：2015-12-10
申请号：PCT/US2015/033649
申请日：2015-06-02
申请人： QUALCOMM INCORPORATED , SHIN, Hyunsuk , SANCHEZ, Henry, Laurel , VUONG, Hung, Quoc , GIL, Amit
发明人： SHIN, Hyunsuk , SANCHEZ, Henry, Laurel , VUONG, Hung, Quoc , GIL, Amit
IPC分类号： G06F13/40 , G06K13/067 , G06K19/077
CPC分类号： G06F13/4022 , G06F13/4068 , G06F13/4234 , G11C16/14 , G11C16/20 , G11C16/34
摘要： Removable memory card type detection systems and methods are disclosed. In one aspect, a removable memory card is inserted into a receptacle of a host. The host determines a type of removable memory card based upon either electrical or physical properties of the removable memory card. In this manner, if the host detects that the removable memory card possesses certain electrical or physical properties associated with a microSD card, the host determines that the removable memory card is a microSD type card. If the host detects that the removable memory card possesses certain electrical or physical properties associated with a UFS card, the host determines that the removable memory card is a UFS type card. By determining the card type based on detection of certain electrical or physical properties, aspects disclosed herein are able to distinguish between UFS and microSD cards without requiring an additional pin or card initialization time.
摘要翻译：公开了可移动存储卡型检测系统和方法。在一个方面，将可移动存储卡插入到主机的插座中。主机基于可移动存储卡的电气或物理属性来确定可移动存储卡的类型。以这种方式，如果主机检测到可移动存储卡具有与microSD卡相关联的某些电气或物理属性，则主机确定可移动存储卡是microSD型卡。如果主机检测到可移动存储卡具有与UFS卡相关联的某些电气或物理属性，则主机确定可移动存储卡是UFS型卡。通过基于某些电气或物理特性的检测来确定卡类型，本文公开的方面能够区分UFS和microSD卡，而不需要额外的引脚或卡初始化时间。

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