专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2017048653A1 MEMORY SYNCHRONIZATION IN BLOCK-BASED PROCESSORS 审中-公开
标题翻译：基于块式处理器的内存同步
公开(公告)号：WO2017048653A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051414
申请日：2016-09-13
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F12/0806 , G06F9/38
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for performing memory operations instructions in a block-based processor architecture. In certain examples of the disclosed technology, a block-based processor core coupled to memory includes a control unit configured to issue one or more memory operations encoded in an instruction block allocated to the core and to commit the core when execution of the instruction block is complete, a memory store queue configured to cache one or more operands for the one or more memory operations, where a result of performing the memory operations is not architecturally visible unless the instruction block is committed by the control unit, and a memory interface configured to store the cached operands in the memory responsive to the instruction block committing. In some examples, the block-based processor core supports memory synchronization using load linked and store conditional instructions.
摘要翻译：公开了用于在基于块的处理器架构中执行存储器操作指令的装置和方法。在所公开的技术的某些示例中，耦合到存储器的基于块的处理器核心包括：控制单元，被配置为发出编码在分配给核心的指令块中的一个或多个存储器操作，并且当指令块的执行是完成的存储器存储队列被配置为缓存一个或多个存储器操作的一个或多个操作数，其中执行存储器操作的结果在架构上不可见，除非指令块由控制单元提交，并且存储器接口被配置为响应于提交的指令块，将缓存的操作数存储在存储器中。在一些示例中，基于块的处理器核心使用负载链接和存储条件指令来支持存储器同步。

2. 发明申请

WO2017048646A1 GENERATION AND USE OF MEMORY ACCESS INSTRUCTION ORDER ENCODINGS 审中-公开
标题翻译：内存访问指令编码的生成和使用
公开(公告)号：WO2017048646A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051407
申请日：2016-09-13
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F12/0806 , G06F9/38
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for controlling execution of memory access instructions in a block-based processor architecture using a hardware structure that indicates a relative ordering of memory access instruction in an instruction block. In one example of the disclosed technology, a method of executing an instruction block having a plurality of memory load and/or memory store instructions includes selecting a next memory load or memory store instruction to execute based on dependencies encoded within the block, and on a store vector that stores data indicating which memory load and memory store instructions in the instruction block have executed. The store vector can be masked using a store mask. The store mask can be generated when decoding the instruction block, or copied from an instruction block header. Based on the encoded dependencies and the masked store vector, the next instruction can issue when its dependencies are available.
摘要翻译：公开了用于使用指示指令块中的存储器访问指令的相对排序的硬件结构来控制基于块的处理器架构中的存储器访问指令的执行的装置和方法。在所公开的技术的一个示例中，执行具有多个存储器加载和/或存储器存储指令的指令块的方法包括：基于在块内编码的依赖性来选择要执行的下一个存储器加载或存储器存储指令，存储指示在指令块中执行哪些存储器存储指令的数据的数据。存储向量可以使用存储掩码进行掩码。存储掩码可以在解码指令块时生成，也可以从指令块头复制。基于编码的依赖性和掩码的存储向量，下一条指令可以在其依赖性可用时发出。

3. 发明申请

WO2017048643A1 MULTI-NULLIFICATION 审中-公开
标题翻译： MULTI-无效化
公开(公告)号：WO2017048643A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051404
申请日：2016-09-13
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F9/38 , G06F9/30 , G06F9/345
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.
摘要翻译：公开了用于使存储器存储指令和在无效指令的目标字段中标识的一个或多个寄存器无效的装置和方法。在所公开的技术的一些示例中，设备可以包括被配置为获取和执行多个指令块的存储器和一个或多个基于块的处理器核心。核心之一可以包括至少部分地基于接收到无效指令而配置的控制单元，以获得多个存储器访问指令的存储器访问指令的指令标识和多个存储器访问指令中的至少一个的寄存器标识的寄存器，基于无效指令的第一和第二目标字段。与指令识别相关联的至少一个寄存器和存储器访问指令被无效。基于无效存储器访问指令，执行随后的存储器访问指令。

4. 发明申请

WO2017048642A1 WRITE NULLIFICATION 审中-公开
公开(公告)号：WO2017048642A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051403
申请日：2016-09-13
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for nullifying one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain a register identification of at least one of a plurality of registers, based on a target field of the nullification instruction. A write to the at least one register associated with the register identification is nullified. The nullification instruction is in a first instruction block of the plurality of instruction blocks. Based on the nullified write to the at least one register, a subsequent instruction is executed from a second, different instruction block.
摘要翻译：公开了用于使在无效指令的目标字段中识别的一个或多个寄存器无效的装置和方法。在所公开技术的一些示例中，设备可以包括被配置为获取和执行多个指令块的存储器和一个或多个基于块的处理器核心。核心之一可以包括基于至少部分地基于接收到无效指令而配置的控制单元，以基于无效指令的目标字段来获得多个寄存器中的至少一个的寄存器标识。对与寄存器标识相关联的至少一个寄存器的写入无效。无效指令位于多个指令块的第一指令块中。基于对至少一个寄存器的无效写入，从第二不同的指令块执行后续指令。

5. 发明申请

WO2017048607A1 INITIATING INSTRUCTION BLOCK EXECUTION USING A REGISTER ACCESS INSTRUCTION 审中-公开
标题翻译：使用寄存器访问指令启动指令块执行
公开(公告)号：WO2017048607A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051209
申请日：2016-09-12
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F12/0806 , G06F9/38
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for initiating instruction block execution using a register access instruction (e.g., a register Read instruction). In some examples of the disclosed technology, a block-based computing system can include a plurality of processor cores configured to execute at least one instruction block. The at least one instruction block encodes a data-flow instruction set architecture (ISA). The ISA includes a first plurality of instructions and a second plurality of instructions. One or more of the first plurality of instructions specify at least a first target instruction without specifying a data source operand. One or more of the second plurality of instructions specify at least a second target instruction and a data source operand that specifies a register.
摘要翻译：公开了用于使用寄存器访问指令（例如，寄存器读指令）启动指令块执行的装置和方法。在所公开技术的一些示例中，基于块的计算系统可以包括被配置为执行至少一个指令块的多个处理器核。所述至少一个指令块对数据流指令集架构（ISA）进行编码。 ISA包括第一多个指令和第二多个指令。第一组多个指令中的一个或多个指令至少指定第一目标指令而不指定数据源操作数。第二多个指令中的一个或多个指令指定至少第二目标指令和指定寄存器的数据源操作数。

6. 发明申请

WO2015120491A1 COMPUTER PROCESSOR EMPLOYING PHASES OF OPERATIONS CONTAINED IN WIDE INSTRUCTIONS 审中-公开
标题翻译：计算机处理器使用宽泛指令中包含的操作阶段
公开(公告)号：WO2015120491A1
公开(公告)日：2015-08-13
申请号：PCT/US2015/023826
申请日：2015-04-01
申请人： MILL COMPUTING, INC.
发明人： GODARD, Roger Rawson , KAHLICH, Arthur David , YOST, David Arthur , MIROLO, Sebastien Paul Maurice
IPC分类号： G06F7/53 , G06F9/38
CPC分类号： G06F9/3822 , G06F9/30167 , G06F9/3836 , G06F9/3853 , G06F9/3855 , G06F9/3861 , G06F9/3885
摘要： A computer processor employs an instruction processing pipeline that processes a sequence of wide instructions each having an encoding that represents a plurality of different operations. The plurality of different operations of the given wide instruction are logically organized into a number of phases having a predefined ordering such that at least one operation of the given wide instruction produces data that is consumed by at least one other operation of the given wide instruction. In certain circumstances where stalling is absent, the plurality of different operations of the phases of the given wide instruction can be issued for execution by the instruction processing pipeline over a plurality of consecutive machine cycles.
摘要翻译：计算机处理器采用指令处理流水线，其处理每个具有表示多个不同操作的编码的宽指令序列。给定宽指令的多个不同操作被逻辑地组织成具有预定义排序的多个阶段，使得给定宽指令的至少一个操作产生由给定宽指令的至少一个其他操作消耗的数据。在不存在停止的某些情况下，可以通过指令处理流水线在多个连续的机器周期上发出给定的宽指令的相位的多个不同的操作来执行。

7. 发明申请

WO2015061687A1 PROCESSOR AND METHODS FOR IMMEDIATE HANDLING AND FLAG HANDLING 审中-公开
标题翻译：处理器和方法立即处理和标记处理
公开(公告)号：WO2015061687A1
公开(公告)日：2015-04-30
申请号：PCT/US2014/062180
申请日：2014-10-24
申请人： ADVANCED MICRO DEVICES, INC.
发明人： VENKATACHAR, Ashok , PUNUKOLLU, Karthik , AREKAPUDI, Srikanth , CHITNIS, Samir A. , TALPES, Emil
IPC分类号： G06F9/06
CPC分类号： G06F9/384 , G06F9/30094 , G06F9/30098 , G06F9/30167 , G06F9/3838 , G06F9/3863 , G06F9/3865
摘要： Described herein are methods and processors for flag renaming in groups to eliminate dependencies of instructions. Decoder and execution units in the processor may be configured to rename flags into groups that allow each group to be treated separately as appropriate. This flag renaming eliminates flag dependencies with respect to instructions. This allows an instruction to write exactly the flags that the instruction wants without having to create merge dependencies. Methods and processors are provided for handling immediate values embedded in instructions. A 16 bit immediate bus and a 4 bit encoding/control bus are added at the interface between decode and execution units. For an 8 or 12 bit immediate, the upper 4 bits of the immediate bus contain the encoding bits. For a 16 bit immediate, the encoding/control bus contains the encoding bits. The encoding/control bus indicates when to look at the top four bits of the immediate bus.
摘要翻译：这里描述了用于组中的标志重命名以消除指令的依赖性的方法和处理器。处理器中的解码器和执行单元可以被配置为将标记重新命名为允许每个组在适当时分开对待的组。该标志重命名消除了关于指令的标志依赖性。这允许指令准确地写入指令所需的标志，而无需创建合并依赖关系。提供了方法和处理器来处理嵌入在指令中的立即值。解码和执行单元之间的接口添加了一个16位立即总线和一个4位编码/控制总线。对于8位或12位立即数，立即总线的高4位包含编码位。对于16位立即数，编码/控制总线包含编码位。编码/控制总线指示何时查看立即总线的前四位。

8. 发明申请

WO2014090093A1 MODIFY AND EXECUTE NEXT SEQUENTIAL INSTRUCTION FACILITY AND INSTRUCTIONS THEREFORE 审中-公开
标题翻译：修改和执行下一步的顺序指示工具及其说明
公开(公告)号：WO2014090093A1
公开(公告)日：2014-06-19
申请号：PCT/CN2013/088188
申请日：2013-11-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM (CHINA) CO., LIMITED
发明人： GSCHWIND, Michael K. , SCHWARZ, Eric M.
IPC分类号： G06F21/00
CPC分类号： G06F9/30145 , G06F9/30029 , G06F9/30054 , G06F9/30058 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/30181 , G06F9/324 , G06F9/342
摘要： A modify next sequential instruction (MNSI) instruction, when executed, modifies a field of the fetched copy of the next sequential instruction (NSI) to enable a program to dynamically provide parameters to the NSI being executed. Thus the MNSI instruction is a non-disruptive prefix instruction to the NSI. The NSI may be modified to effectively extend the length of the NSI field, thus providing more registers or more range (in the case of a length field) than otherwise available to the NSI instruction according to the instruction set architecture (ISA).
摘要翻译：修改下一个顺序指令（MNSI）指令，当执行时，修改下一个顺序指令（NSI）的获取副本的一个字段，以使程序能够动态地向被执行的NSI提供参数。因此，MNSI指令是NSI的非中断前缀指令。可以修改NSI以有效地扩展NSI字段的长度，从而根据指令集体系结构（ISA）提供更多的寄存器或更多的范围（在长度字段的情况下）比NSI指令可用的更多的范围。

9. 发明申请

WO2014085472A1 FUSING IMMEDIATE VALUE, WRITE-BASED INSTRUCTIONS IN INSTRUCTION PROCESSING CIRCUITS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA 审中-公开
标题翻译：在指令处理电路中建立立即价值的写入指令以及相关处理器系统，方法和计算机可读介质
公开(公告)号：WO2014085472A1
公开(公告)日：2014-06-05
申请号：PCT/US2013/072035
申请日：2013-11-26
申请人： QUALCOMM INCORPORATED
发明人： BROWN, Melinda J. , MORROW, Michael William , DIEFFENDERFER, James Norris , STEMPEL, Brian Michael , MCILVAINE, Michael Scott , SMITH, Rodney Wayne , SCHOTTMILLER, Jeffery M. , IRWIN, Andrew S
IPC分类号： G06F9/30
CPC分类号： G06F9/3017 , G06F9/30167
摘要： Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first instruction indicating an operation writing an immediate value to a register is detected by an instruction processing circuit. The circuit also detects at least one subsequent instruction indicating an operation that overwrites at least one first portion of the register while maintaining a value of a second portion of the register. The at least one subsequent instruction is converted (or replaced) with a fused instruction(s), which indicates an operation writing the at least one first portion and the second portion of the register. In this manner, conversion of multiple instructions for generating a constant into the fused instruction(s) removes the potential for a read-after-write hazard and associated consequences caused by dependencies between certain instructions, while reducing a number of clock cycles required to process the instructions.
摘要翻译：公开了立即值的融合，指令处理电路中的基于写入的指令以及相关的处理器系统，方法和计算机可读介质。在一个实施例中，指令处理电路检测指示向寄存器写入立即值的操作的第一指令。电路还检测至少一个后续指令，指示在保持寄存器的第二部分的值的同时重写寄存器的至少一个第一部分的操作。所述至少一个后续指令被转换（或替代）与一个融合指令，其指示写入寄存器的至少一个第一部分和第二部分的操作。以这种方式，将用于产生常数的多个指令转换为融合指令消除了读写后危险和由特定指令之间的依赖性引起的相关后果的可能性，同时减少了处理所需的时钟周期数说明。

10. 发明申请

WO2013095580A1 PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO GENERATE SEQUENCES OF INTEGERS IN WHICH INTEGERS IN CONSECUTIVE POSITIONS DIFFER BY A CONSTANT INTEGER STRIDE AND WHERE A SMALLEST INTEGER IS OFFSET FROM ZERO BY AN INTEGER OFFSET 审中-公开
标题翻译：处理器，方法，系统和指令，用于生成整数的序列，其中整数位置中的整数在恒定整数的范围内不同，并且最小的整数由整数偏移从零偏移
公开(公告)号：WO2013095580A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067047
申请日：2011-12-22
申请人： INTEL CORPORATION , ABRAHAM, Seth , VALL, El Moustapha Ould-Ahmed , VALENTINE, Robert , SPERBER, Zeev , GRADSTEIN, Amit
发明人： ABRAHAM, Seth , VALL, El Moustapha Ould-Ahmed , VALENTINE, Robert , SPERBER, Zeev , GRADSTEIN, Amit
IPC分类号： G06F9/06 , G06F9/30 , G06F9/305 , G06F13/14
CPC分类号： G06F9/3001 , G06F9/30032 , G06F9/30036 , G06F9/30163 , G06F9/30167 , G06F9/3455
摘要： A method of an aspect includes receiving an instruction. The instruction indicates an integer stride, indicates an integer offset, and indicates a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four integers in numerical order with a smallest one of the at least four integers differing from zero by the integer offset and with all integers of the sequence in consecutive positions differing by the integer stride. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译：方面的方法包括接收指令。该指令指示整数步长，表示整数偏移，并指示目的地存储位置。结果存储在目的地存储位置以响应该指令。结果包括以数字顺序的至少四个整数的序列，其中至少四个整数中的最小的整数与零与整数偏移不同，并且具有与整数步长不同的连续位置中的序列的所有整数。公开了其它方法，装置，系统和指令。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式