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1. 发明申请

WO2017048662A1 PREDICATED READ INSTRUCTIONS 审中-公开
标题翻译：预期阅读说明
公开(公告)号：WO2017048662A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051424
申请日：2016-09-13
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F9/38
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for example computer processors that are based on a hybrid dataflow execution model. Embodiments of the disclosed technology use read instructions to retrieve a value from a specified register in the register file of the processor architecture and send the value for use by one or more targets (e.g., other instructions in the instruction block). The read instruction may be predicated such that the instruction is only executed when a predicate condition is satisfied. In some examples of the disclosed technology, a compiler for such processors performs an analysis of the source and/or object code being compiled in order to determine whether operation(s) along conditional paths can be executed before or concurrently with determination of a condition on which the conditional operation(s) depend, thus improving processor efficiency.
摘要翻译：公开了装置和方法，例如基于混合数据流执行模型的计算机处理器。所公开技术的实施例使用读取指令来从处理器架构的寄存器文件中的指定寄存器检索值，并发送一个或多个目标（例如，指令块中的其他指令）使用的值。读取指令可以被假定为仅当满足谓词条件时才执行指令。在所公开的技术的一些示例中，用于这种处理器的编译器对正被编译的源和/或目标代码进行分析，以便确定沿着条件路径的操作是否可以在确定条件之前或同时执行条件操作取决于哪些，从而提高处理器的效率。

2. 发明申请

WO2017048660A1 BLOCK-BASED PROCESSOR CORE COMPOSITION REGISTER 审中-公开
标题翻译：基于块的处理器芯组成寄存器
公开(公告)号：WO2017048660A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051422
申请日：2016-09-13
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F12/0806 , G06F9/38
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Systems, apparatuses, and methods related to a block-based processor core composition register are disclosed. In one example of the disclosed technology, a processor can include a plurality of block-based processor cores for executing a program including a plurality of instruction blocks. A respective block-based processor core can include one or more sharable resources and a programmable composition control register. The programmable composition control register can be used to configure which resources of the one or more sharable resources are shared with other processor cores of the plurality of processor cores.
摘要翻译：公开了与基于块的处理器核心组合寄存器相关的系统，装置和方法。在所公开的技术的一个示例中，处理器可以包括多个基于块的处理器核，用于执行包括多个指令块的程序。相应的基于块的处理器核心可以包括一个或多个可共享资源和可编程组合控制寄存器。可编程组合控制寄存器可用于配置一个或多个可共享资源的哪些资源与多个处理器核的其他处理器核共享。

3. 发明申请

WO2017048656A1 DISTINCT SYSTEM REGISTERS FOR LOGICAL PROCESSORS 审中-公开
标题翻译：逻辑处理器的异常系统寄存器
公开(公告)号：WO2017048656A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051417
申请日：2016-09-13
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F12/0806 , G06F9/38
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Distinct system registers for logical processors are disclosed. In one example of the disclosed technology, a processor includes a plurality of block-based physical processor cores for executing a program comprising a plurality of instruction blocks. The processor also includes a thread scheduler configured to schedule a thread of the program for execution, the thread using the one or more instruction blocks. The processor further includes at least one system register. The at least one system register stores data indicating a number and placement of the plurality of physical processor cores to form a logical processor. The logical processor executes the scheduled thread. The logical processor is configured to execute the thread in a continuous instruction window.
摘要翻译：公开了用于逻辑处理器的不同系统寄存器。在所公开的技术的一个示例中，处理器包括用于执行包括多个指令块的程序的多个基于块的物理处理器核。处理器还包括线程调度器，其被配置为调度用于执行的程序的线程，线程使用一个或多个指令块。处理器还包括至少一个系统寄存器。所述至少一个系统寄存器存储指示多个物理处理器核的数量和布置的数据，以形成逻辑处理器。逻辑处理器执行调度的线程。逻辑处理器被配置为在连续指令窗口中执行线程。

4. 发明申请

WO2017048652A1 DYNAMIC GENERATION OF NULL INSTRUCTIONS 审中-公开
标题翻译：空指令的动态生成
公开(公告)号：WO2017048652A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051413
申请日：2016-09-13
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F9/38 , G06F9/30 , G06F9/345
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for dynamic nullification of memory access instructions, such as memory store instructions. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores. One of the cores can include an execution unit configured to execute memory access instructions comprising a plurality of memory load and/or memory store instructions contained in an instruction block. The core can also include a hardware structure storing data for at least one predicate instruction in the instruction block, the data identifying whether one or more of the memory store instructions will issue if a condition of the predicate instruction is satisfied. The core may further include a control unit configured to control issuing of the memory access instructions to the execution unit based at least in a part on the hardware structure data.
摘要翻译：公开了用于存储器访问指令的动态无效的装置和方法，诸如存储器存储指令。在所公开技术的一些示例中，装置可以包括存储器和一个或多个基于块的处理器核。核心之一可以包括被配置为执行存储器访问指令的执行单元，该存储器访问指令包括包含在指令块中的多个存储器加载和/或存储器存储指令。核心还可以包括存储指令块中的至少一个谓词指令的数据的硬件结构，如果满足谓词指令的条件，则识别存储器存储指令中的一个或多个是否将发出的数据。核心可以进一步包括控制单元，其被配置为至少部分地基于硬件结构数据来控制向执行单元发出存储器访问指令。

5. 发明申请

WO2017048651A1 BROADCAST CHANNEL ARCHITECTURES FOR BLOCK-BASED PROCESSORS 审中-公开
标题翻译：用于基于块的处理器的广播通道架构
公开(公告)号：WO2017048651A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051412
申请日：2016-09-13
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F12/0806 , G06F9/38
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for example computer processors that are based on a hybrid dataflow execution model. In particular embodiments, a processor core in a block-based processor comprises: one or more functional units configured to perform functions using one or more operands; an instruction window comprising buffers configured to store individual instructions for execution by the processor core, the instruction window including one or more operand buffers for an individual instruction configured to store operand values; a control unit configured to execute the instructions in the instruction window and control operation of the one or more functional units; and a broadcast value store comprising a plurality of buffers dedicated to storing broadcast values, each buffer of the broadcast value store being associated with a respective broadcast channel from among a plurality of available broadcast channels.
摘要翻译：公开了装置和方法，例如基于混合数据流执行模型的计算机处理器。在特定实施例中，基于块的处理器中的处理器核心包括：被配置为使用一个或多个操作数执行功能的一个或多个功能单元; 指令窗口，包括被配置为存储由处理器核心执行的单独指令的缓冲器，所述指令窗口包括用于存储操作数值的单独指令的一个或多个操作数缓冲器; 控制单元，被配置为执行所述指令窗口中的指令并控制所述一个或多个功能单元的操作; 以及广播值存储器，包括专用于存储广播值的多个缓冲器，广播值存储器的每个缓冲器与多个可用广播信道中的相应广播信道相关联。

6. 发明申请

WO2017048641A1 STORE NULLIFICATION IN THE TARGET FIELD 审中-公开
标题翻译：目标领域的存储失效
公开(公告)号：WO2017048641A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051402
申请日：2016-09-13
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for nullifying memory store instructions identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions, based on a target field of the nullification instruction. The memory access instruction associated with the instruction identification is nullified. The memory access instruction is in a first instruction block of the plurality of instruction blocks. Based on the nullified memory access instruction, a subsequent memory access instruction from the first instruction block is executed.
摘要翻译：公开了用于使在无效指令的目标字段中标识的存储器存储指令无效的装置和方法。在所公开技术的一些示例中，装置可以包括被配置为获取和执行多个指令块的存储器和一个或多个基于块的处理器核心。核心之一可以包括基于至少部分地基于接收到无效指令而配置的控制单元，以基于无效指令的目标字段获得多个存储器访问指令的存储器访问指令的指令标识。与指令识别相关联的存储器访问指令无效。存储器访问指令位于多个指令块的第一指令块中。基于无效存储器访问指令，执行来自第一指令块的后续存储器访问指令。

7. 发明申请

WO2017048606A1 OUT OF ORDER COMMIT 审中-公开
标题翻译：超出订单
公开(公告)号：WO2017048606A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051208
申请日：2016-09-12
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F9/46 , G06F9/52
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： The disclosed technology can be used for executing and committing instruction blocks of a block-based processor architecture out-of-order. In one example of the disclosed technology, an apparatus can include a plurality of block-based processor cores which can include a first group of cores and a second group of cores. The first group of cores can be configured to commit instruction blocks of the set of instruction blocks in a sequential program order. The second group of cores can be configured to commit instruction blocks of the set of instruction blocks out-of-order relative to the sequential program order.
摘要翻译：所公开的技术可以用于执行和提交无序的基于块的处理器架构的指令块。在所公开的技术的一个示例中，设备可以包括多个基于块的处理器核，其可以包括第一组核和第二组核。第一组核心可以被配置为以顺序的程序顺序提交该组指令块的指令块。可以将第二组核心配置为相对于顺序程序顺序提交指令块集无序的指令块。

8. 发明申请

WO2015050557A1 TECHNIQUES FOR HETEROGENEOUS CORE ASSIGNMENT 审中-公开
标题翻译：异质核心分配技术
公开(公告)号：WO2015050557A1
公开(公告)日：2015-04-09
申请号：PCT/US2013/063399
申请日：2013-10-04
申请人： INTEL CORPORATION , BARIK, Rajkishore , LEWIS, Brian T. , SHPEISMAN, Tatiana
发明人： BARIK, Rajkishore , LEWIS, Brian T. , SHPEISMAN, Tatiana
IPC分类号： G06F9/38 , G06F9/46
CPC分类号： G06F9/30145 , G06F1/263 , G06F8/451 , G06F9/3822 , G06F9/5094 , G06F2209/508 , Y02D10/22
摘要： Various embodiments are generally directed to techniques for assigning instances of blocks of instructions of a routine to one of multiple types of core of a heterogeneous set of cores of a processor component. An apparatus to select types of cores includes a processor component; a core selection component for execution by the processor component to select a core of multiple cores to execute an initial subset of multiple instances of an instruction block in parallel based on characteristics of instructions of the instruction block, and to select a core of the multiple cores to execute remaining instances of the multiple instances of the instruction block in parallel based on characteristics of execution of the initial subset stored in an execution database; and a monitoring component for execution by the processor component to record the characteristics of execution of the initial subset in the execution database. Other embodiments are described and claimed.
摘要翻译：各种实施例通常涉及用于将例程的指令块的实例分配给处理器组件的异构集群核心的多种类型的核心之一的技术。选择核心类型的装置包括处理器组件; 核心选择部件，用于由处理器部件执行以选择多个核的核心，以基于指令块的指令的特性并行地执行指令块的多个实例的初始子集，并且选择多个核心的核心基于存储在执行数据库中的初始子集的执行特性来并行执行指令块的多个实例的剩余实例; 以及用于由处理器组件执行以在执行数据库中记录初始子集的执行特性的监视组件。描述和要求保护其他实施例。

9. 发明申请

WO2008039908A3 PROCESSING ARCHITECTURES WITH TYPED INSTRUCTION SETS 审中-公开
标题翻译：使用特定指令集处理架构
公开(公告)号：WO2008039908A3
公开(公告)日：2008-10-30
申请号：PCT/US2007079678
申请日：2007-09-27
申请人： 3DLABS INC LTD , BLOOMFIELD JONATHAN , ROBSON JOHN DAVID , MURPHY NICHOLAS J N
发明人： BLOOMFIELD JONATHAN , ROBSON JOHN DAVID , MURPHY NICHOLAS J N
IPC分类号： G06F15/00
CPC分类号： G06F9/30145 , G06F9/3013 , G06F9/30178 , G06F9/30185 , G06F9/30192 , G06F9/3822
摘要： An architecture fear microprocessors and the like in which instructions include a type identifier, which selects one of several inteipretation registers. The mterpretation registers hold Mopnatiøn for interpreting the opcode of each instruction, so that a stream of compressed instructions (with type identifiers) can be translated into a stream of expanded instructions. Preferably the type identifiers also distinguish sequencer instructions from processing-element instructions, and can even distinguish among different types of sequencer instructions (as well as among different types of processing-element instructions).
摘要翻译：一种体系结构恐惧微处理器等，其中指令包括类型标识符，该类型标识符选择若干个内插寄存器中的一个。解释寄存器保存Mopnatiøn用于解释每条指令的操作码，以便可以将带有类型标识符的压缩指令流转换为扩展指令流。优选地，类型标识符还将定序器指令与处理元件指令区分开，并且甚至可以区分不同类型的定序器指令（以及不同类型的处理元件指令之间）。

10. 发明申请

WO2008039908A2 PROCESSING ARCHITECTURES WITH TYPED INSTRUCTION SETS 审中-公开
标题翻译：具有类型指令集的加工结构
公开(公告)号：WO2008039908A2
公开(公告)日：2008-04-03
申请号：PCT/US2007/079678
申请日：2007-09-27
申请人： 3DLABS INC., LTD. , BLOOMFIELD, Jonathan , ROBSON, John, David , MURPHY, Nicholas, J.N.
发明人： BLOOMFIELD, Jonathan , ROBSON, John, David , MURPHY, Nicholas, J.N.
IPC分类号： G06F9/44
CPC分类号： G06F9/30145 , G06F9/3013 , G06F9/30178 , G06F9/30185 , G06F9/30192 , G06F9/3822
摘要： An architecture fear microprocessors and the like in which instructions include a type identifier, which selects one of several inteipretation registers. The mterpretation registers hold Moπnatiøn for interpreting the opcode of each instruction, so that a stream of compressed instructions (with type identifiers) can be translated into a stream of expanded instructions. Preferably the type identifiers also distinguish sequencer instructions from processing-element instructions, and can even distinguish among different types of sequencer instructions (as well as among different types of processing-element instructions).
摘要翻译：架构担心微处理器等，其中指令包括选择几个互补寄存器之一的类型标识符。解释寄存器保存Mopnatiøn来解释每个指令的操作码，使得压缩指令流（带有类型标识符）可以转换为扩展指令流。优选地，类型标识符还将定序器指令与处理单元指令区分开，并且甚至可以区分不同类型的定序器指令（以及不同类型的处理单元指令）。

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