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1. 发明申请

WO2018169919A1 PRECISE EXCEPTIONS FOR EDGE PROCESSORS 审中-公开
公开(公告)号：WO2018169919A1
公开(公告)日：2018-09-20
申请号：PCT/US2018/022117
申请日：2018-03-13
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , GUPTA, Gagan
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3861 , G06F9/30116 , G06F9/3832 , G06F9/3836 , G06F9/3859 , G06F9/3863 , G06F9/3865 , G06F9/4806 , G06F9/4812 , G06F15/76 , G06F15/7839 , G06F2209/481
摘要： Systems and methods are disclosed for supporting debugging of programs in block-based processor architectures. In one example of the disclosed technology, a processor includes an exception event handler, a memory interface, at least one block-based processor core coupled to the memory interface and configured to responsive to receiving an exception event signal while executing an instruction block, store state data for the core generated by executing the instruction block, transfer control of the core to a second instruction block, and resume execution of the first instruction by restoring state for the processor core from the stored state data.

2. 发明申请

WO2018080684A1 NESTED EXCEPTION HANDLING 审中-公开
标题翻译：嵌套异常处理
公开(公告)号：WO2018080684A1
公开(公告)日：2018-05-03
申请号：PCT/US2017/053088
申请日：2017-09-22
申请人： INTEL CORPORATION
发明人： XING, Bin
IPC分类号： G06F21/53 , G06F21/54 , G06F21/56
CPC分类号： G06F12/1009 , G06F9/30054 , G06F9/30076 , G06F9/3802 , G06F9/3861 , G06F12/08 , G06F12/109 , G06F12/12 , G06F12/128 , G06F12/145 , G06F21/79 , G06F2212/1052 , G06F2212/657 , G06F2212/684 , G06F2212/70
摘要： An example system that includes a processor and a memory device. The processor may include multiple execution units to execute instructions and a memory device coupled to the processor. The memory device stores the instructions in an unprotected region and a protected region. The processor may determine that a first exception occurred while executing a first set of instructions for an application stored in a secured page of the protected region. The processor may invoke a first subroutine to forward exception context for the first exception to a second subroutine, where the first subroutine is stored in the protected region and the second subroutine is stored in the unprotected region. The processor may invoke, by the second subroutine, a third subroutine to execute a second set of instructions associated with the exception context for the first exception.
摘要翻译：
包含处理器和存储器设备的示例系统。处理器可以包括执行指令的多个执行单元和耦合到处理器的存储器设备。存储设备将指令存储在未受保护的区域和受保护的区域中。处理器可以确定在执行存储在受保护区域的受保护页面中的应用的第一组指令时发生第一异常。处理器可以调用第一子例程来将用于第一例外的异常上下文转发到第二子例程，其中第一子例程存储在受保护区域中并且第二子例程存储在未受保护区域中。处理器可以通过第二子例程调用第三子例程来执行与第一例外的异常上下文相关联的第二组指令。

3. 发明申请

WO2017168197A1 APPARATUS AND METHOD FOR IMPROVING PERFORMANCE OF INTER-STRAND COMMUNICATIONS 审中-公开
标题翻译：提高跨层通信性能的装置和方法
公开(公告)号：WO2017168197A1
公开(公告)日：2017-10-05
申请号：PCT/IB2016/000612
申请日：2016-04-01
申请人： INTEL CORPORATION
发明人： PODKORYTOV, Evgeniy , CHUDNOVETS, Andrey , TITOV, Alexandr , MASLENNIKOV, Dimitry
IPC分类号： G06F9/30 , G06F9/38 , G06F9/45
CPC分类号： G06F9/3851 , G06F9/30087 , G06F9/30185 , G06F9/3828 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3861
摘要： An apparatus and method are described for inter-strand processing. For example, one embodiment of a processor comprises: a plurality of cores to concurrently execute a plurality of strands of program code; a first circuit to separate an instruction sequence into at least a first strand and a second strand; a second circuit comprising a plurality of entries to track associations between one or more instructions in the first strand and one or more instructions in the second strand, the second circuit to store a register identifier in a first entry responsive to execution of a first instruction in the first strand; a third circuit to compare an argument of a second instruction in a second strand with the register identifier in the first entry in response to detecting a branch misprediction in the second strand, wherein if the argument and the register identifier do not match, then the third circuit to cause the second strand to wait until the argument and the register identifier match before consuming a register value.
摘要翻译：描述了用于链间处理的装置和方法。例如，处理器的一个实施例包括：多个内核以同时执行多个程序代码链; 将指令序列分成至少第一链和第二链的第一电路; 第二电路，其包括用于跟踪第一链中的一个或多个指令与第二链中的一个或多个指令之间的关联的多个条目，第二电路响应于第一指令的执行而在第一条目中存储寄存器标识符第一股; 第三电路，用于响应于检测到所述第二链中的分支错误预测，将第二链中的第二指令的自变量与所述第一条目中的所述寄存器标识符进行比较，其中如果所述自变量和所述寄存器标识符不匹配，则所述第三使第二条链等待，直到参数和寄存器标识符匹配，然后才消耗一个寄存器值。

4. 发明申请

WO2017116652A1 REPLAY OF PARTIALLY EXECUTED INSTRUCTION BLOCKS IN A PROCESSOR-BASED SYSTEM EMPLOYING A BLOCK-ATOMIC EXECUTION MODEL 审中-公开
标题翻译：在采用块式原子执行模型的基于处理器的系统中重新部署执行指令块
公开(公告)号：WO2017116652A1
公开(公告)日：2017-07-06
申请号：PCT/US2016/065740
申请日：2016-12-09
申请人： QUALCOMM INCORPORATED
发明人： WRIGHT, Gregory, Michael
IPC分类号： G06F9/38
CPC分类号： G06F9/30181 , G06F9/30043 , G06F9/3832 , G06F9/3861
摘要： Replay of partially executed instruction blocks in a processor-based system employing a block-atomic execution model is disclosed. In one aspect, a partial replay controller is provided in a processor(s) of a central processing unit (CPU). If an instruction is detected in the instruction block associated with a potential architectural state modification, or an exception occurs during execution of instructions, the instruction block is re-executed. During re-execution of the instruction block, the partial replay controller is configured to record produced results from load/store instructions. Thus, if an exception occurs during re-execution of the instruction block, previously recorded produced results for the executed load/store instructions before the exception occurred are replayed during re-execution of the instruction block after the exception is resolved. Thus, execution of instructions leading up to side-effect operations in the instruction block can be deterministically repeated with previously produced results, without repeating the side-effects.
摘要翻译：公开了在采用块原子执行模型的基于处理器的系统中重放部分执行的指令块。在一个方面，在中央处理单元（CPU）的处理器中提供部分重放控制器。如果在与潜在的架构状态修改相关联的指令块中检测到指令，或者在执行指令期间发生异常，则指令块被重新执行。在重新执行指令块期间，部分重放控制器被配置为记录来自加载/存储指令的生成结果。因此，如果在指令块的重新执行期间发生异常，则在解决异常之后在指令块的重新执行期间重播先前记录的在发生异常之前执行的加载/存储指令的产生结果。因此，执行导致指令块中的副作用操作的指令可以用先前产生的结果确定性地重复，而不会重复副作用。

5. 发明申请

WO2017112315A1 NON-TRACKED CONTROL TRANSFERS WITHIN CONTROL TRANSFER ENFORCEMENT 审中-公开
标题翻译：非追踪控制权转让的控制权转移执行
公开(公告)号：WO2017112315A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/063665
申请日：2016-11-23
申请人： INTEL CORPORATION
发明人： SHANBHOGUE, Vedvyas , SAHITA, Ravi, L. , GUPTA, Deepak, K.
IPC分类号： G06F21/54 , G06F21/50
CPC分类号： G06F9/3861 , G06F9/3005 , G06F9/30054 , G06F9/30076 , G06F21/123 , G06F21/125
摘要： A processor includes an execution unit and a processing logic operatively coupled to the execution unit, the processing logic to: enter a first execution state; responsive to executing a control transfer instruction having a pre-defined subcode, remain in the first execution state; responsive to executing a control transfer instruction not having the pre-defined subcode, transition into a second execution state; and responsive to determining, in the second execution state, that a next instruction to be executed differs from an ENDBRANCH instruction, raise an execution exception.
摘要翻译：处理器包括执行单元和可操作地耦合到执行单元的处理逻辑，处理逻辑用于：进入第一执行状态; 响应于执行具有预定子代码的控制传送指令，保持在第一执行状态; 响应于执行不具有预定子码的控制传送指令，转换到第二执行状态; 并响应于在第二执行状态中确定要执行的下一条指令与ENDBRANCH指令不同，引发执行异常。

6. 发明申请

WO2016177992A1 CHECK INSTRUCTION FOR VERIFYING CORRECT CODE EXECUTION CONTEXT 审中-公开
标题翻译：检查正确代码执行条件的指令
公开(公告)号：WO2016177992A1
公开(公告)日：2016-11-10
申请号：PCT/GB2016/051023
申请日：2016-04-12
申请人： ARM LIMITED
发明人： PARKER, Jason
IPC分类号： G06F9/30
CPC分类号： G06F9/30079 , G06F9/30021 , G06F9/30076 , G06F9/30094 , G06F9/30101 , G06F9/30189 , G06F9/3861 , G06F11/004 , G06F21/52 , G06F21/71
摘要： A data processing apparatus and method of data processing are provided which make use of a processor state check instruction to determine if the data processing apparatus is currently operating in a processor state, defined by at least one runtime processor state configuration value, which matches a processor state check value defined by the processor state check instruction. Dependent on the required runtime processor state configuration value(s) matching the processor state check value, the processor state check instruction is treated as an ineffective instruction. When the at least one runtime processor state configuration value does not match the processor state check value an exception is generated. Improved security of the data processing apparatus is thus provided.
摘要翻译：提供了一种数据处理装置和数据处理方法，其使用处理器状态检查指令来确定数据处理装置当前是否处于由至少一个运行时处理器状态配置值定义的处理器状态，该运行时处理器状态配置值与处理器由处理器状态检查指令定义的状态检查值。根据与处理器状态检查值匹配的所需运行时处理器状态配置值，处理器状态检查指令被视为无效指令。当至少一个运行时处理器状态配置值与处理器状态检查值不匹配时，生成异常。因此提供了数据处理装置的改进的安全性。

7. 发明申请

WO2016097792A1 APPARATUS AND METHOD TO PRECLUDE LOAD REPLAYS DEPENDENT ON WRITE COMBINING MEMORY SPACE ACCESS IN OUT-OF-ORDER PROCESSOR 审中-公开
标题翻译：根据订单处理程序中写入组合记忆空间访问依据的装载和方法
公开(公告)号：WO2016097792A1
公开(公告)日：2016-06-23
申请号：PCT/IB2014/003171
申请日：2014-12-14
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： COL, Gerard, M. , EDDY, Colin , HENRY, G., Glenn
IPC分类号： G06F9/30
CPC分类号： G06F9/3838 , G06F9/30043 , G06F9/3824 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3861
摘要： An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The plurality of prescribed resources includes system memory, coupled to the out-of-order processor via a memory bus, where the specified load micro instruction is known to resolve to write combining memory space in the system memory.
摘要翻译：一种包括第一和第二保留站的装置。第一保留站调度负载微指令，并且在保持总线上指示负载微指令是否是指定的从指定资源（除了内核高速缓冲存储器）检索操作数的指定负载微指令。第二保留站耦合到保持总线，并且在分配第一加载微指令之后的多个时钟周期之后，分派一个或多个取决于载入微指令以执行的较新的微指令，并且如果在所述保持总线，所述加载微指令是指定的负载微指令，所述第二保留站被配置为停止所述一个或多个较小的微指令的分派，直到所述加载微指令已经检索到所述操作数。多个规定资源包括经由存储器总线耦合到无序处理器的系统存储器，其中已知指定的负载微指令解决写入组合系统存储器中的存储器空间。

8. 发明申请

WO2015144499A1 HARDWARE COUNTERS TO TRACK UTILIZATION IN A MULTITHREADING COMPUTER SYSTEM 审中-公开
标题翻译：硬件计数器在多计算机系统中跟踪应用
公开(公告)号：WO2015144499A1
公开(公告)日：2015-10-01
申请号：PCT/EP2015/055571
申请日：2015-03-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED
发明人： BRADBURY, Jonathan, David , SCHMIDT, Donald, William , ROSA, Daniel, Vincent , BARTIK, Jane , KING, Gary, Malcolm
IPC分类号： G06F9/50
CPC分类号： G06F9/3851 , G06F1/10 , G06F9/30145 , G06F9/3861 , G06F9/5061 , G06F9/5083
摘要： Embodiments relate tracking utilization in a multithreading (MT) computer system. According to one aspect, a computer system includes a configuration with a core configured to operate in a MT that supports multiple threads on shared resources of the core. The core is configured to perform a method that includes resetting a plurality of utilization counters. The utilization counters include a plurality of sets of counters. During each clock cycle on the core, a set of counters is selected from the plurality of sets of counters. The selecting is based on a number of currently active threads on the core. In addition, during each clock cycle a counter in the selected set of counters is incremented based on an aggregation of one or more execution events at the multiple threads of the core. Values of the utilization counters are provided to a software program.
摘要翻译：实施例涉及多线程（MT）计算机系统中的跟踪利用。根据一个方面，一种计算机系统包括具有被配置为在支持所述核心的共享资源上的多个线程的MT中操作的核心的配置。核心被配置为执行包括重置多个利用计数器的方法。利用计数器包括多组计数器。在核心的每个时钟周期期间，从多组计数器中选择一组计数器。该选择基于核心上当前活动的线程数量。此外，在每个时钟周期期间，所选择的一组计数器中的计数器基于核心的多个线程处的一个或多个执行事件的聚合而递增。利用率计数器的值被提供给软件程序。

9. 发明申请

WO2015142435A1 FREEING PHYSICAL REGISTERS IN A MICROPROCESSOR 审中-公开
标题翻译：在微处理器中释放物理寄存器
公开(公告)号：WO2015142435A1
公开(公告)日：2015-09-24
申请号：PCT/US2015/014541
申请日：2015-02-05
申请人： QUALCOMM INCORPORATED
发明人： KRISHNA, Anil , WU, Weidan , NAVADA, Sandeep Suresh , CHOUDHARY, Niket Kumar , SMITH, Rodney Wayne
IPC分类号： G06F9/38
CPC分类号： G06F9/30098 , G06F9/3832 , G06F9/3838 , G06F9/384 , G06F9/3861
摘要： Physical register scrubbing in computer microprocessors. Most instructions in a computer program produce some output value that is destined for one or more architected registers. These architected destination registers are renamed, in the processor pipeline, to physical registers in order to improve performance by exposing more instruction level parallelism to the processor. In one aspect, a method comprises identifying, in a reorder buffer, a first instruction and a second instruction, without intervening potential pipeline flushers, that write to the same architected destination register, in order to free the physical register corresponding to the older of the two instructions.
摘要翻译：计算机微处理器中的物理寄存器擦除。计算机程序中的大多数指令产生一些输出值，用于一个或多个架构化寄存器。这些架构化的目标寄存器在处理器流水线中被重命名为物理寄存器，以便通过向处理器暴露更多的指令级并行性来提高性能。在一个方面，一种方法包括在重排序缓冲器中识别第一指令和第二指令，而不间断地写入到同一架构目的寄存器的潜在流水线冲洗器，以便释放对应于较早的两个说明。

10. 发明申请

WO2014111771A1 DYNAMIC ACCESSING OF EXECUTION ELEMENTS THROUGH MODIFICATION OF ISSUE RULES 审中-公开
标题翻译：通过修改问题规则对执行单位进行动态的访问
公开(公告)号：WO2014111771A1
公开(公告)日：2014-07-24
申请号：PCT/IB2013/061067
申请日：2013-12-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM JAPAN LIMITED
发明人： KRYGOWSKI, Christopher, Anthony , SHUM, Chung-Lung, Kevin , BUSABA, Fadi, Yusuf , CARLOUGH, Steven , PRASKY, Brian, Robert
IPC分类号： G06F11/20 , G06F9/46
CPC分类号： G06F11/0793 , G06F9/30145 , G06F9/3836 , G06F9/3861 , G06F11/0721 , G06F11/0724 , G06F11/079 , G06F11/2025 , G06F11/2035 , G06F11/2043
摘要： Embodiments of the invention relate to dynamically routing instructions to execution units based on detected errors in the execution units. An aspect of the invention includes a computer system including a processor having an instruction issue unit and a plurality of execution units. The processor is configured to detect an error in a first execution unit among the plurality of execution units and adjust instruction dispatch rules of the instruction issue unit based on detecting the error in the first execution unit to restrict access to the first execution unit while leaving un-restricted access to the remaining execution units of the plurality of execution units.
摘要翻译：本发明的实施例涉及基于执行单元中检测到的错误将指令动态地路由到执行单元。本发明的一个方面包括一种包括具有指令发布单元和多个执行单元的处理器的计算机系统。处理器被配置为检测多个执行单元中的第一执行单元中的错误，并且基于检测到第一执行单元中的错误来调整指令发布单元的指令分派规则，以限制对第一执行单元的访问，同时留下un - 对所述多个执行单元中的剩余执行单元的限制访问。

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