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1. 发明申请

WO2017078882A1 ENABLING REMOVAL AND RECONSTRUCTION OF FLAG OPERATIONS IN A PROCESSOR 审中-公开
标题翻译：在处理器中实现标志操作的移除和重构
公开(公告)号：WO2017078882A1
公开(公告)日：2017-05-11
申请号：PCT/US2016/055612
申请日：2016-10-06
申请人： INTEL CORPORATION
发明人： SPERBER, Zeev , WEINER, Tomer , GRADSTEIN, Amit , RUBANOVICH, Simon , GERBER, Alex , RAVID, Itai
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/3001 , G06F9/30094 , G06F9/30145 , G06F9/30167 , G06F9/3832 , G06F9/384
摘要： In one embodiment, a processor includes a fetch logic to fetch instructions, a decode logic to decode the fetched instructions, and an execution logic to execute at least some of the instructions. The decode logic may determine whether a flag portion of a first instruction to be folded is to be performed, and if not, accumulate a first immediate value of the first instruction with a folded immediate value obtained from an entry of an immediate buffer. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括用于获取指令的获取逻辑，用于解码获取的指令的解码逻辑以及用于执行至少一些指令的执行逻辑。解码逻辑可以确定是否要执行要被折叠的第一指令的标志部分，并且如果不是，则利用从立即缓冲器的条目获得的折叠立即值来累计第一指令的第一立即值。描述并要求保护其他实施例。

2. 发明申请

WO2017007557A1 DYNAMIC THREAD SPLITTING 审中-公开
标题翻译：动态螺纹分割
公开(公告)号：WO2017007557A1
公开(公告)日：2017-01-12
申请号：PCT/US2016/035849
申请日：2016-06-03
申请人： INTEL CORPORATION , NALLURI, Hema, C. , PAL, Supratim , MAIYURAN, Subramaniam , CHANDRA, Joy
发明人： NALLURI, Hema, C. , PAL, Supratim , MAIYURAN, Subramaniam , CHANDRA, Joy
IPC分类号： G06F9/50 , G06F9/48 , G06F9/38 , G06T1/20
CPC分类号： G06F9/30094 , G06F9/30072 , G06F9/3851
摘要： Systems, apparatuses and methods may provide for associating a first instruction pointer with an IF block of a primary IF-ELSE conditional construct associated with a thread and activating a second instruction pointer in response to a dependency associated with the IF block. Additionally, the second instruction pointer may be associated with an ELSE block of the primary IF-ELSE conditional construct. In one example, the IF block and the ELSE block are executed, via the first instruction pointer and the second instruction pointer, one or more of independently from or parallel to one another.
摘要翻译：系统，装置和方法可以提供将第一指令指针与与线程相关联的主IF-ELSE条件结构的IF块相关联，并且响应于与IF块相关联的依赖关系来激活第二指令指针。另外，第二指令指针可以与主IF-ELSE条件构造的ELSE块相关联。在一个示例中，经由第一指令指针和第二指令指针执行IF块和ELSE块，彼此独立地或并行地执行一个或多个。

3. 发明申请

WO2016177992A1 CHECK INSTRUCTION FOR VERIFYING CORRECT CODE EXECUTION CONTEXT 审中-公开
标题翻译：检查正确代码执行条件的指令
公开(公告)号：WO2016177992A1
公开(公告)日：2016-11-10
申请号：PCT/GB2016/051023
申请日：2016-04-12
申请人： ARM LIMITED
发明人： PARKER, Jason
IPC分类号： G06F9/30
CPC分类号： G06F9/30079 , G06F9/30021 , G06F9/30076 , G06F9/30094 , G06F9/30101 , G06F9/30189 , G06F9/3861 , G06F11/004 , G06F21/52 , G06F21/71
摘要： A data processing apparatus and method of data processing are provided which make use of a processor state check instruction to determine if the data processing apparatus is currently operating in a processor state, defined by at least one runtime processor state configuration value, which matches a processor state check value defined by the processor state check instruction. Dependent on the required runtime processor state configuration value(s) matching the processor state check value, the processor state check instruction is treated as an ineffective instruction. When the at least one runtime processor state configuration value does not match the processor state check value an exception is generated. Improved security of the data processing apparatus is thus provided.
摘要翻译：提供了一种数据处理装置和数据处理方法，其使用处理器状态检查指令来确定数据处理装置当前是否处于由至少一个运行时处理器状态配置值定义的处理器状态，该运行时处理器状态配置值与处理器由处理器状态检查指令定义的状态检查值。根据与处理器状态检查值匹配的所需运行时处理器状态配置值，处理器状态检查指令被视为无效指令。当至少一个运行时处理器状态配置值与处理器状态检查值不匹配时，生成异常。因此提供了数据处理装置的改进的安全性。

4. 发明申请

WO2016055085A1 SYSTEM AND METHOD FOR PATTERN-RECOGNITION BASED MONITORING AND CONTROLLED PROCESSING OF DATA OBJECTS BASED ON CONFORMITY MEASUREMENTS 审中-公开
标题翻译：基于一致性测量的基于模式识别的数据对象的监控和控制处理的系统和方法
公开(公告)号：WO2016055085A1
公开(公告)日：2016-04-14
申请号：PCT/EP2014/071319
申请日：2014-10-06
申请人： SWISS REINSURANCE COMPANY LTD.
发明人： UNSWORTH, Rory , PAYÁ, Jorge
IPC分类号： G06Q10/10 , G06Q40/08
CPC分类号： G06Q40/08 , G06F9/30094 , G06F17/30946 , G06F17/30964 , G06K9/00335 , G06Q10/10
摘要： Proposed is a pattern-recognition-based control and monitoring system (10) for automated underwriting systems (20, 21), or automated data capturing systems, or automated data surveillance systems, in particular network surveillance systems, and a method thereof. The underwriting workflow of the underwriting system (20, 21) is monitored by capturing underwriting objects (71, 72, 73) in the underwriting process flow (19) and/or by forming a source of pooled underwriting objects (71,72,73), and by activating additional process states (1911, 1912, 1913), when non-conforming underwriting workflow objects (71, 72, 73) are triggered within the underwriting process flow (19). A recognition block-map (111) comprising a plurality of block elements (1112, 1113, 1114) is generated and captured by means of a first searchable datastructure (112) of a first database (11), and a plurality of historical underwriting workflow objects (1211, 1212) is captured by means of a second searchable datastructure (121) of a second database (12). Underwriting objects (71, 72, 73) are captured, wherein the captured workflow objects (71, 72, 73) are scanned for block elements (1112, 1113, 1114) of the stored recognition block-map (111). Based on the filtered block elements of the captured workflow object (71, 72, 73), a proximity factor with regard to each of the stored workflow objects (1211, 1212) of the second database (12) is determined. A conformity index value is triggered by the workflow objects of the second database (12) within a predefined range of the proximity factor, and the additional process states are triggered and assigned to the process flow (19) by means of a process management engine (13) of the measurement and monitoring system (10), when the measurement that is taken of the conformity index exceeds a risk threshold value (141).
摘要翻译：提出了一种用于自动承保系统（20,21）或自动数据采集系统或自动数据监控系统（特别是网络监控系统）的基于模式识别的控制和监控系统（10）及其方法。通过在承保处理流程（19）中捕获承保对象（71,72,73）和/或通过形成合并的承保对象的源（71,72,73）来监视承保系统（20,21）的承保工作流程），并且当在承保处理流程（19）内触发不合格的承保工作流对象（71,72,73）时，激活附加过程状态（1911,1912,1913）。通过第一数据库（11）的第一可搜索数据结构（112）和多个历史承保工作流（112）生成并捕获包括多个块元素（1112,1113,1114）的识别块映射（111）通过第二数据库（12）的第二可搜索数据结构（121）捕获对象（1211,1212）。捕获承保对象（71,72,73），其中对所存储的识别块映射（111）的块元素（1112,1113,1114）扫描所捕获的工作流对象（71,72,73）。基于所捕获的工作流对象（71,72,73）的经滤波的块元素，确定关于第二数据库（12）的每个存储的工作流对象（1211,1212）的接近因子。在第二数据库（12）的工作流对象在邻近因子的预定义范围内触发一致性指标值，并且借助于过程管理引擎触发附加过程状态并将其分配给过程流（19）当测量符合指标的测量超过风险阈值（141）时，测量和监视系统（10）的测量和监视系统（10）的测量和监控系统（10）

5. 发明申请

WO2011038411A1 EFFICIENT PREDICATED EXECUTION FOR PARALLEL PROCESSORS 审中-公开
标题翻译：高效预防并行处理器的执行
公开(公告)号：WO2011038411A1
公开(公告)日：2011-03-31
申请号：PCT/US2010/050588
申请日：2010-09-28
申请人： NVIDIA CORPORATION , JOHNSON, Richard, Craig , NICKOLLS, John, R. , GLANVILLE, Robert, Steven
发明人： JOHNSON, Richard, Craig , NICKOLLS, John, R. , GLANVILLE, Robert, Steven
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F9/3851 , G06F9/30021 , G06F9/30029 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/30094 , G06F9/3012 , G06F9/3013 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： The invention set forth herein describes a mechanism for predicated execution of instructions within a parallel processor executing multiple threads or data lanes. Each thread or data lane executing within the parallel processor is associated with a predicate register that stores a set of 1-bit predicates. Each of these predicates can be set using different types of predicate-setting instructions, where each predicate setting instruction specifies one or more source operands, at least one operation to be performed on the source operands, and one or more destination predicates for storing the result of the operation. An instruction can be guarded by a predicate that may influence whether the instruction is executed for a particular thread or data lane or how the instruction is executed for a particular thread or data lane.
摘要翻译：本文阐述的发明描述了用于在执行多个线程或数据通道的并行处理器内预测执行指令的机制。在并行处理器内执行的每个线程或数据通道与存储一组1位谓词的谓词寄存器相关联。可以使用不同类型的谓词设置指令来设置这些谓词中的每一个，其中每个谓词设置指令指定一个或多个源操作数，要对源操作数执行的至少一个操作以及用于存储结果的一个或多个目标谓词的操作。指令可以由可能影响特定线程或数据通道执行指令的指令或如何针对特定线程或数据通道执行指令的谓词来保护。

6. 发明申请

WO2009114961A1 一种支持X86虚拟机的RISC处理器装置及方法审中-公开
公开(公告)号：WO2009114961A1
公开(公告)日：2009-09-24
申请号：PCT/CN2008/002023
申请日：2008-12-17
申请人：中国科学院计算技术研究所 , 李国杰 , 胡伟武 , 李晓钰 , 苏孟豪
发明人：李国杰 , 胡伟武 , 李晓钰 , 苏孟豪
IPC分类号： G06F9/455 , G06F9/30
CPC分类号： G06F9/30174 , G06F9/30076 , G06F9/30094 , G06F9/30185

7. 发明申请

WO2009087158A3 COMPARE AND BRANCH FACILITY AND INSTRUCTION THEREFORE 审中-公开
标题翻译：比较和分支机构及其指导
公开(公告)号：WO2009087158A3
公开(公告)日：2009-09-17
申请号：PCT/EP2009050105
申请日：2009-01-07
申请人： IBM , IBM UK , GREINER DAN , SLEGEL TIMOTHY
发明人： GREINER DAN , SLEGEL TIMOTHY
IPC分类号： G06F9/32
CPC分类号： G06F9/30058 , G06F9/30094 , G06F9/30167
摘要： An atomic compare and branch instruction is executed that combines the function of a compare instruction having an option field with a conditional branch or jump instruction such that condition codes are preserved rather than setting condition codes to a value representative of the compare results. One comparand is obtained from any one of a memory location or an immediate field and the other comparand is obtained from a register field.
摘要翻译：执行原子比较和分支指令，其将具有选项字段的比较指令的功能与条件分支或跳转指令相结合，使得保留条件代码而不是将条件代码设置为代表比较结果的值。从存储器位置或立即场中的任何一个获得一个比较，并且从寄存器字段获得另一个比较。

8. 发明申请

WO2009086727A1 一种RISC处理器及其寄存器标志位处理方法审中-公开
公开(公告)号：WO2009086727A1
公开(公告)日：2009-07-16
申请号：PCT/CN2008/001906
申请日：2008-11-24
申请人：中国科学院计算技术研究所 , 胡伟武 , 李晓钰 , 李国杰
发明人：胡伟武 , 李晓钰 , 李国杰
IPC分类号： G06F15/78 , G06F9/30
CPC分类号： G06F9/30094 , G06F9/30076 , G06F9/30174 , G06F9/30189
摘要： A RISC processor and its register flag bit processing method. The processor comprises a physical register stack, an operating component connected to the physical register stack and an decoder connected to the operating component; the physical register stack comprises a simulating flag register for simulating to realize a flag bit of a flag register of a CISC processor; the operating component comprises a flag read-write module for reading and writing the value of the flag bit of the simulating flag register. The operating component also comprises an operating controller, in the operating process, the operating controller is used for controlling operating based on the value of the flag bit of the simulating flag register when the RISC processor is in the working mode of X86 virtual machine.

9. 发明申请

WO2008022217A1 SYSTEM AND METHOD OF PROCESSING DATA USING SCALAR/VECTOR INSTRUCTIONS 审中-公开
标题翻译：使用标准/矢量指令处理数据的系统和方法
公开(公告)号：WO2008022217A1
公开(公告)日：2008-02-21
申请号：PCT/US2007/076033
申请日：2007-08-15
申请人： QUALCOMM Incorporated , CODRESCU, Lucian , PLONDKE, Erich , SIMPSON, Taylor
发明人： CODRESCU, Lucian , PLONDKE, Erich , SIMPSON, Taylor
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F15/78
CPC分类号： G06F9/30101 , G06F9/30021 , G06F9/30094 , G06F9/3885
摘要： A processor device is disclosed that includes a register file with a combined condition code register for scalar and vector operations. The processor device utilizes the combined condition code register for scalar and vector operations. Further, a compare operation can store resulting bits in the combined condition code register and a conditional operation can utilize the combined condition code register bits for evaluating a condition.
摘要翻译：公开了一种处理器装置，其包括具有用于标量和矢量操作的组合条件码寄存器的寄存器文件。处理器设备利用组合条件码寄存器进行标量和向量操作。此外，比较操作可以将结果位存储在组合条件码寄存器中，并且条件操作可以利用组合条件码寄存器位来评估条件。

10. 发明申请

WO2006085277A3 AN ELECTRONIC PARALLEL PROCESSING CIRCUIT 审中-公开
标题翻译：电子并联处理电路
公开(公告)号：WO2006085277A3
公开(公告)日：2007-01-11
申请号：PCT/IB2006050422
申请日：2006-02-09
申请人： KONINKL PHILIPS ELECTRONICS NV , KLEIHORST RICHARD P , ABBO ANTENEH A , MOUY SEBASTIEN F
发明人： KLEIHORST RICHARD P , ABBO ANTENEH A , MOUY SEBASTIEN F
IPC分类号： G06F9/32
CPC分类号： G06F9/30094 , G06F9/3842 , G06F9/3885 , G06F9/3887
摘要： The electronic circuit contains a plurality of processing elements (10), which are supplied with instructions under control of a common program flow, typically for SIMD operation wherein the same instructions are applied to all processing elements and different operand data of the instructions to respective ones of the processing elements (10). Under control of the instructions each processing element (10) determines, whether an operand data dependent condition has occurred. The processing element outputs a condition signal dependent on said determination. The condition signals are summed to form a sum signal. Program flow is controlled by a conditional jump dependent on a value represented by the sum signal.
摘要翻译：电子电路包含多个处理元件（10），这些处理元件（10）在公共程序流程的控制下被提供，通常用于SIMD操作，其中将相同的指令应用于所有处理元件，并将指令的不同操作数数据应用于相应的指令的处理元件（10）。在指令的控制下，每个处理元件（10）确定是否已经发生操作数数据相关条件。处理单元输出取决于所述确定的条件信号。将条件信号求和以形成和信号。程序流程由取决于由和信号表示的值的条件跳转来控制。

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