专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2018103113A1 基于FPGA的Local Bus转USB的系统及芯片审中-公开
公开(公告)号：WO2018103113A1
公开(公告)日：2018-06-14
申请号：PCT/CN2016/109450
申请日：2016-12-12
申请人：邦彦技术股份有限公司
发明人：闫立国
IPC分类号： G06F13/40
CPC分类号： G06F13/4004 , G06F13/4068 , G06F13/4221 , G06F13/4282 , G06F2213/0024 , G06F2213/0042
摘要：一种基于FPGA的Local Bus转USB系统（100），包括：FPGA模块（10），用于与FPGA芯片（200）通过Local Bus协议进行数据传输；处理模块（20），用于与所述FPGA模块（10）通过自定义数据传输协议进行数据传输；以及，USB通信模块（30），用于连接处理模块（20）与USB通信设备（300）通过USB协议进行数据传输。上述系统设置FPGA模块（10）通过Local Bus协议与FPGA芯片（200）进行数据传输，将传输的数据再通过USB通信模块（30）与USB通信设备（300）通过USB协议进行传输，实现了Local Bus信号与USB信号的转换，方便快捷，安全性及稳定性高。

2. 发明申请

WO2017048657A1 PREFETCHING ASSOCIATED WITH PREDICATED LOAD INSTRUCTIONS 审中-公开
标题翻译：与预测负荷指令相关的预备
公开(公告)号：WO2017048657A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051418
申请日：2016-09-13
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F9/38 , G06F12/0862 , G06F9/30
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Technology related to prefetching data associated with predicated loads of programs in block-based processor architectures is disclosed. In one example of the disclosed technology, a processor includes a block-based processor core for executing an instruction block comprising a plurality of instructions. The block-based processor core includes decode logic and prefetch logic. The decode logic is configured to detect a predicated load instruction of the instruction block. The prefetch logic is configured to calculate a target address of the predicated load instruction and issue a prefetch request to a memory hierarchy of the processor for data at the calculated target address.
摘要翻译：公开了与在基于块的处理器架构中预测与程序负载相关联的数据相关的技术。在所公开的技术的一个示例中，处理器包括用于执行包括多个指令的指令块的基于块的处理器核心。基于块的处理器核心包括解码逻辑和预取逻辑。解码逻辑被配置为检测指令块的预测加载指令。预取逻辑被配置为计算预测加载指令的目标地址，并且在计算出的目标地址的数据上向处理器的存储器层次结构发出预取请求。

3. 发明申请

WO2017048655A1 DENSE READ ENCODING FOR DATAFLOW ISA 审中-公开
标题翻译： DENSE读取编码数据流ISA
公开(公告)号：WO2017048655A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051416
申请日：2016-09-13
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F12/0806 , G06F9/38
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for controlling execution of memory access instructions in a block-based processor architecture using an instruction decoder that decodes instructions having variable numbers of target operands. In one example of the disclosed technology, a block-based processor core includes an instruction decoder configured to decode target operands for an instruction in an instruction block, the instruction being encoded to allow for a variable number of target operands and a control unit configured to send data for at least one of the decoded target operands for an operation performed by the at least one of the cores. In some examples, the instruction indicates target instructions with a vector encoding. In other examples, a variable length format allows for the indication of one or more targets.
摘要翻译：公开了用于在基于块的处理器架构中使用解码具有可变数目的目标操作数的指令的指令解码器来控制存储器访问指令的执行的装置和方法。在所公开的技术的一个示例中，基于块的处理器核心包括指令解码器，其被配置为对指令块中的指令进行解码目标操作数，所述指令被编码以允许可变数量的目标操作数，以及控制单元，为所述至少一个核执行的操作发送用于所述解码的目标操作数中的至少一个的数据。在一些示例中，该指令指示具有向量编码的目标指令。在其他示例中，可变长度格式允许指示一个或多个目标。

4. 发明申请

WO2017048650A1 DEBUG SUPPORT FOR BLOCK-BASED PROCESSOR 审中-公开
标题翻译：用于基于块的处理器的调试支持
公开(公告)号：WO2017048650A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051411
申请日：2016-09-13
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F9/38 , G06F11/00 , G06F11/36 , G06F9/30
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Systems and methods are disclosed for supporting debugging of programs in block-based processor architectures. In one example of the disclosed technology, a processor includes a block-based processor core for executing an instruction block comprising an instruction header and a plurality of instructions. The block-based processor core includes execution control logic and core state access logic. The execution control logic can be configured to schedule respective instructions of the plurality of instructions for execution in a dynamic order during a default execution mode and to schedule the respective instructions for execution in a static order during a debug mode. The core state access logic can be configured to read intermediate states of the block-based processor core and to provide the intermediate states outside of the block-based processor core during the debug mode.
摘要翻译：公开了用于支持基于块的处理器架构中的程序的调试的系统和方法。在所公开的技术的一个示例中，处理器包括用于执行包括指令标题和多个指令的指令块的基于块的处理器核心。基于块的处理器核心包括执行控制逻辑和核心状态访问逻辑。执行控制逻辑可以被配置为在默认执行模式期间以动态顺序调度多个指令的相应指令以便以动态顺序执行，并且在调试模式期间调度各个指令以静态顺序执行。核心状态访问逻辑可以被配置为读取基于块的处理器核的中间状态，并且在调试模式期间将中间状态提供到基于块的处理器核之外。

5. 发明申请

WO2017048649A1 REGISTER READ/WRITE ORDERING 审中-公开
标题翻译：注册阅读/写命令
公开(公告)号：WO2017048649A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051410
申请日：2016-09-13
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F12/0806 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for controlling execution of register access instructions in a block-based processor architecture using a hardware structure that indicates a relative ordering of register access instruction in an instruction block. In one example of the disclosed technology, a method of operating a processor includes selecting a register access instruction of the plurality of instructions to execute based at least in part on dependencies encoded within a previous block of instructions and on stored data indicating which of the register write instructions have executed for the previous block, and executing the selected instruction. In some examples, one or more of a write mask, a read mask, a register write vector register, or a counter are used to determine register read/write dependences. Based on the encoded dependencies and the masked write vector, the next instruction block can issue when its register dependencies are available.
摘要翻译：公开的装置和方法用于使用指示指令块中的寄存器访问指令的相对排序的硬件结构来控制基于块的处理器架构中的寄存器访问指令的执行。在所公开的技术的一个实例中，一种操作处理器的方法包括：至少部分地基于在先前的指令块内编码的依存关系以及存储的数据来选择多个指令的寄存器访问指令，以指示寄存器对上一个程序段执行写入指令，并执行所选择的指令。在一些示例中，使用写掩码，读掩码，寄存器写向量寄存器或计数器中的一个或多个来确定寄存器读/写依赖性。基于编码的依赖性和掩码写入向量，下一个指令块可以在其寄存器依赖性可用时发出。

6. 发明申请

WO2017048648A1 SEGMENTED INSTRUCTION BLOCK 审中-公开
标题翻译：分段指令块
公开(公告)号：WO2017048648A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051409
申请日：2016-09-13
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F9/30 , G06F9/38 , G06F9/46
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Systems and methods are disclosed for fetching and decoding instructions in block-based processor architectures. In one example of the disclosed technology, a block-based processor core can be used for executing an instruction block. The instruction block can include an instruction header and one or more instructions. The block-based processor core can include header decode logic and fetch logic that are in communication with each other. The header decode logic can be configured to decode the instruction block header to determine starting positions of a plurality of sub-blocks within the instruction block. The fetch logic can be configured to initiate parallel fetch and decode operations for the plurality of sub-blocks.
摘要翻译：公开了用于在基于块的处理器架构中提取和解码指令的系统和方法。在所公开的技术的一个示例中，可以使用基于块的处理器核来执行指令块。指令块可以包括指令头和一个或多个指令。基于块的处理器核心可以包括彼此通信的报头解码逻辑和提取逻辑。报头解码逻辑可以被配置为解码指令块报头以确定指令块内的多个子块的开始位置。提取逻辑可以被配置为启动用于多个子块的并行获取和解码操作。

7. 发明申请

WO2017048605A1 CONFIGURING MODES OF PROCESSOR OPERATION 审中-公开
标题翻译：处理器操作的配置模式
公开(公告)号：WO2017048605A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051207
申请日：2016-09-12
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for configuring, operating, and compiling code for, block-based processor architectures. In one example of the disclosed technology, a block-based processor includes processor cores configured to decode an instruction block header for a block-based processor instruction block including one or more fields and configure at least one of the cores to execute instructions in the instruction block according to a mode of operation specified by at least one of the fields, the modes including one or more of the following: core fusion operation, vector mode operation, memory dependence prediction operation, and/or deterministic order of execution.
摘要翻译：公开了用于配置，操作和编译用于基于块的处理器架构的代码的装置和方法。在所公开的技术的一个示例中，基于块的处理器包括被配置为对包括一个或多个字段的基于块的处理器指令块的指令块头进行解码并且配置至少一个核来执行指令中的指令的处理器核根据由至少一个字段指定的操作模式，所述模式包括以下中的一个或多个：核心融合操作，向量模式操作，存储器依赖性预测操作和/或确定性执行顺序。

8. 发明申请

WO2016160731A1 METHODS AND APPARATUS FOR IO, PROCESSING AND MEMORY BANDWIDTH OPTIMIZATION FOR ANALYTICS SYSTEMS 审中-公开
标题翻译：用于分析系统的IO，处理和存储带宽优化的方法和设备
公开(公告)号：WO2016160731A1
公开(公告)日：2016-10-06
申请号：PCT/US2016/024571
申请日：2016-03-28
申请人： INTEGRATED DEVICE TECHNOLOGY, INC.
发明人： AKHTER, Mohammad
IPC分类号： G06F13/40 , G06F13/12
CPC分类号： G06F13/4027 , G06F13/4221 , G06T1/20 , Y02D10/14 , Y02D10/151
摘要： Methods and Apparatus for IO, Processing and Memory Bandwidth Optimization for Analytics Systems has been disclosed. In one implementation, a plurality of cards each having one or more GPU+CPU are interconnected via RapidlO, multiple SATA interfaces, multiple Ethernet interfaces, and multiple RapidIO interfaces.
摘要翻译：已经公开了用于分析系统的IO，处理和存储带宽优化的方法和装置。在一个实现中，通过Rapid10，多个SATA接口，多个以太网接口和多个RapidIO接口来互连多个具有一个或多个GPU + CPU的卡。

9. 发明申请

WO2016105671A1 DYNAMIC LANE MANAGEMENT OF AN AGGRESSOR COMMUNICATIONS BUS FOR INTERFERENCE MITIGATION 审中-公开
标题翻译：抗干扰通信总线用于干扰减缓的动态LANE管理
公开(公告)号：WO2016105671A1
公开(公告)日：2016-06-30
申请号：PCT/US2015/059381
申请日：2015-11-06
申请人： QUALCOMM INCORPORATED
发明人： WIETFELDT, Richard, Dominic
IPC分类号： G06F13/40 , G06F13/42 , G06F15/163 , H04B15/02 , H04L12/40
CPC分类号： G06F13/4221 , G06F13/4022 , G06F13/409 , G06F13/4282 , G06F13/4295 , G06F15/163 , H04B15/02 , H04L12/40169
摘要： Dynamic lane management for interference mitigation is disclosed. In one aspect, an integrated circuit (IC) is provided that employs a control system configured to mitigate electromagnetic interference (EMI) caused by an aggressor communications bus. The control system is configured to receive information related to EMI conditions and adjust which lanes of the aggressor communications bus are employed for signal transmission. The IC includes an interface configured to couple to the aggressor communications bus. The interface is configured to transmit signals to and receive signals from the aggressor communications bus. The control system is configured to use the information related to the EMI conditions to assign signals to be transmitted via particular lanes of the aggressor communications bus to mitigate the EMI experienced by a victim receiver. The control system provides designers with an additional tool that may reduce the performance degradation of the victim receiver attributable to EMI.
摘要翻译：公开了用于干扰减轻的动态车道管理。在一个方面，提供了一种集成电路（IC），其采用被配置为减轻由侵略者通信总线引起的电磁干扰（EMI）的控制系统。控制系统被配置为接收与EMI条件相关的信息，并且调整侵入者通信总线的哪些通道用于信号传输。 IC包括被配置为耦合到侵略者通信总线的接口。该接口被配置为向侵入者通信总线发送信号并从其接收信号。控制系统被配置为使用与EMI条件相关的信息来分配要通过侵略者通信总线的特定通道发送的信号，以减轻受害者接收机所经历的EMI。控制系统为设计人员提供了一个额外的工具，可以降低受EMI接收机的性能下降。

10. 发明申请

WO2016099627A1 DATA TRANSMISSION USING PCIe PROTOCOL VIA USB PORT 审中-公开
标题翻译：使用PCIe协议通过USB端口进行数据传输
公开(公告)号：WO2016099627A1
公开(公告)日：2016-06-23
申请号：PCT/US2015/053760
申请日：2015-10-02
申请人： INTEL CORPORATION
发明人： PETHE, Akshay G. , HARRIMAN, David J. , WAGH, Mahesh , ISMAIL, Abdul Hawk
IPC分类号： G06F13/42 , G06F13/38
CPC分类号： G06F13/102 , G06F1/266 , G06F1/3203 , G06F13/287 , G06F13/387 , G06F13/4022 , G06F13/4221 , G06F13/4282
摘要： Techniques for transmitted data through a USB port using a PCIe protocol are described herein. In one example, a method includes detecting a coupling of an apparatus and a PCIe compatible device via a Type-C connector and sending at least one vendor defined message to the PCIe compatible device. The method can also include receiving an alternate mode indicator corresponding to a data transfer via a PCIe protocol and sending an enter mode command to the PCIe compatible device to enable the data transfer between the apparatus and the PCIe compatible device via the PCIe protocol. Furthermore, the method can include transferring data between the apparatus and the PCIe compatible device via the Type-C connector with the PCIe protocol.
摘要翻译：本文描述了通过使用PCIe协议的USB端口传输的数据的技术。在一个示例中，一种方法包括经由Type-C连接器检测设备和PCIe兼容设备的耦合，并向PCIe兼容设备发送至少一个供应商定义的消息。该方法还可以包括经由PCIe协议接收对应于数据传输的备用模式指示符，并且向PCIe兼容设备发送输入模式命令，以通过PCIe协议启用设备与PCIe兼容设备之间的数据传输。此外，该方法可以包括经由具有PCIe协议的Type-C连接器在设备和PCIe兼容设备之间传送数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式