专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2022029563A1 OBTAINING CACHE RESOURCES FOR EXPECTED WRITES TO TRACKS IN WRITE SET AFTER THE CACHE RESOURCES WERE RELEASED FOR THE TRACKS IN THE WRITE SET 审中-公开
公开(公告)号：WO2022029563A1
公开(公告)日：2022-02-10
申请号：PCT/IB2021/056809
申请日：2021-07-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM (CHINA) INVESTMENT COMPANY LTD. , IBM DEUTSCHLAND GMBH
发明人： PETERSON, Beth , FUNG, Chung , KALOS, Matthew , CRAIG, Matthew
IPC分类号： G06F12/0862 , G06F12/08 , G06F12/12 , G06F12/0806 , G06F2212/602 , G06F3/0604 , G06F3/0655 , G06F3/0676 , G06F3/0679 , G06F3/0689
摘要： Provided are a computer program product, system, and method for prefetching cache resources for a write request from a host to tracks in storage cached in a cache. Cache resources held for a plurality of tracks in a write set are released before expected writes are received for the tracks in the write set. Cache resources for tracks in the write set are obtained, following the release of the cache resources, to use for expected write requests to the tracks in the write set.

2. 发明申请

WO2021094704A1 AN APPARATUS AND METHOD FOR HANDLING ORDERED TRANSACTIONS 审中-公开
公开(公告)号：WO2021094704A1
公开(公告)日：2021-05-20
申请号：PCT/GB2020/052281
申请日：2020-09-21
申请人： ARM LIMITED
发明人： RINGE, Tushar P , JALAL, Jamshed , RAMAGIRI, Gurunath , TUMMALA, Ashok Kumar , WERKHEISER, Mark David
IPC分类号： G06F12/0806 , G06F12/0817 , G06F13/38 , G06F12/0813
摘要： An apparatus and method are provided for handling ordered transactions. The apparatus has a plurality of completer elements to process transactions, a requester element to issue a sequence of ordered transactions, and an interconnect providing, for each completer element, a communication channel between that completer element and the requester element for transfer of signals between that completer element and the requester element in either direction. A given completer element that is processing a given transaction in the sequence is arranged to issue a response signal to the requester element over its associated communication channel that comprises an ordered channel indication to identify whether the associated communication channel has an ordered channel property. The ordered channel property guarantees that processing of transactions issued by the requester element over the associated communication channel in a given order will be completed by the given completer element in the same given order. The requester element is then responsive to the ordered channel indication to control timing of issuance from the requester element of at least one signal relating to one or more transactions after the given transaction in the sequence. By such an approach, the ordering flow adopted for ordered transactions can be varied by the requester element in dependence on the presence or absence of an ordered channel, whilst enabling interconnect-agnostic requester element designs to be utilised.

3. 发明申请

WO2018098225A2 DYNAMIC APPLICATION OF SOFTWARE DATA CACHING HINTS BASED ON CACHE TEST REGIONS 审中-公开
公开(公告)号：WO2018098225A2
公开(公告)日：2018-05-31
申请号：PCT/US2017/062944
申请日：2017-11-22
申请人： ADVANCED MICRO DEVICES, INC.
发明人： MOYER, Paul
IPC分类号： G06F12/0806
CPC分类号： G06F12/123 , G06F12/0862 , G06F12/0888 , G06F12/12 , G06F2212/1016 , G06F2212/502 , G06F2212/6028
摘要： A processor [101] applies a software hint policy (111, 112) to a portion (118) of a cache based on access metrics for different test regions (115, 116) of the cache, wherein each test region applies a different software hint policy for data associated with cache entries in each region of the cache. One test region applies a software hint policy under which software hints are followed. The other test region applies a software hint policy under which software hints are ignored. One of the software hint policies is selected for application to a non-test region of the cache.

4. 发明申请

WO2017048655A1 DENSE READ ENCODING FOR DATAFLOW ISA 审中-公开
标题翻译： DENSE读取编码数据流ISA
公开(公告)号：WO2017048655A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051416
申请日：2016-09-13
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F12/0806 , G06F9/38
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for controlling execution of memory access instructions in a block-based processor architecture using an instruction decoder that decodes instructions having variable numbers of target operands. In one example of the disclosed technology, a block-based processor core includes an instruction decoder configured to decode target operands for an instruction in an instruction block, the instruction being encoded to allow for a variable number of target operands and a control unit configured to send data for at least one of the decoded target operands for an operation performed by the at least one of the cores. In some examples, the instruction indicates target instructions with a vector encoding. In other examples, a variable length format allows for the indication of one or more targets.
摘要翻译：公开了用于在基于块的处理器架构中使用解码具有可变数目的目标操作数的指令的指令解码器来控制存储器访问指令的执行的装置和方法。在所公开的技术的一个示例中，基于块的处理器核心包括指令解码器，其被配置为对指令块中的指令进行解码目标操作数，所述指令被编码以允许可变数量的目标操作数，以及控制单元，为所述至少一个核执行的操作发送用于所述解码的目标操作数中的至少一个的数据。在一些示例中，该指令指示具有向量编码的目标指令。在其他示例中，可变长度格式允许指示一个或多个目标。

5. 发明申请

WO2017048649A1 REGISTER READ/WRITE ORDERING 审中-公开
标题翻译：注册阅读/写命令
公开(公告)号：WO2017048649A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051410
申请日：2016-09-13
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F12/0806 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for controlling execution of register access instructions in a block-based processor architecture using a hardware structure that indicates a relative ordering of register access instruction in an instruction block. In one example of the disclosed technology, a method of operating a processor includes selecting a register access instruction of the plurality of instructions to execute based at least in part on dependencies encoded within a previous block of instructions and on stored data indicating which of the register write instructions have executed for the previous block, and executing the selected instruction. In some examples, one or more of a write mask, a read mask, a register write vector register, or a counter are used to determine register read/write dependences. Based on the encoded dependencies and the masked write vector, the next instruction block can issue when its register dependencies are available.
摘要翻译：公开的装置和方法用于使用指示指令块中的寄存器访问指令的相对排序的硬件结构来控制基于块的处理器架构中的寄存器访问指令的执行。在所公开的技术的一个实例中，一种操作处理器的方法包括：至少部分地基于在先前的指令块内编码的依存关系以及存储的数据来选择多个指令的寄存器访问指令，以指示寄存器对上一个程序段执行写入指令，并执行所选择的指令。在一些示例中，使用写掩码，读掩码，寄存器写向量寄存器或计数器中的一个或多个来确定寄存器读/写依赖性。基于编码的依赖性和掩码写入向量，下一个指令块可以在其寄存器依赖性可用时发出。

6. 发明申请

WO2023029441A1 多口存储器的数据读写方法、装置、存储介质和电子设备审中-公开
公开(公告)号：WO2023029441A1
公开(公告)日：2023-03-09
申请号：PCT/CN2022/081866
申请日：2022-03-19
申请人：深圳市中兴微电子技术有限公司
发明人：牛忠华 , 刘衡祁 , 王志忠 , 施伟祥
IPC分类号： G06F12/0806
摘要：一种多口存储器的数据读写方法，包括：将目标存储器拆分为多个子存储器，其中，每一个子存储器包括一个读端口和一个写端口（S202）；将多个待写入数据同时写入到目标存储器的多个子存储器中（S204）。解决了多口存储器面积和功耗增大的问题，进而达到了减少多口存储器的占用面积和功耗的效果。还公开了一种多口存储器的数据读写装置、存储介质和电子设备。

7. 发明申请

WO2020176828A1 PRIORITY SCHEDULING IN QUEUES TO ACCESS CACHE DATA IN A MEMORY SUB-SYSTEM 审中-公开
公开(公告)号：WO2020176828A1
公开(公告)日：2020-09-03
申请号：PCT/US2020/020289
申请日：2020-02-28
申请人： MICRON TECHNOLOGY, INC.
发明人： BAVISHI, Dhawal
IPC分类号： G06F12/126 , G06F12/0806 , G06F3/06 , G06F13/16
摘要： A request to read data stored at a memory sub-system can be received. A determination can be made of whether the data is stored at a cache of the memory subsystem. Responsive to determining that the data is not stored at the cache of the memory subsystem, the data can be obtained from a memory component of the memory sub-system. A first priority indicator can be assigned to a fill operation associated with the data that is obtained from the memory component. A second priority indicator can be assigned to the request to read the data. A schedule of executing the fill operation and the request to read the data can be determined based on the first priority indicator and the second priority indicator.

8. 发明申请

WO2017173844A1 一种目录读取的方法、装置及系统审中-公开
公开(公告)号：WO2017173844A1
公开(公告)日：2017-10-12
申请号：PCT/CN2016/109580
申请日：2016-12-13
申请人：浪潮电子信息产业股份有限公司
发明人：周玉龙 , 童元满 , 李仁刚
IPC分类号： G06F12/0806
CPC分类号： G06F12/0806
摘要：一种目录读取的方法、装置及系统，该方法包括：接收对目录缓存进行读取的第一请求信息（101）；确定所述第一请求信息所要读取的第一目录（102）；判断是否存在至少一个正在执行的第二请求信息，其中所述第二请求信息所要读取的第二目录与所述第一目录位于同一个缓存块上（103）；如果是，将所述第一请求信息缓存到预设的缓存区内，执行所述第二请求信息获取到包括所述第一目录及所述第二目录的第二缓存块后，根据所述第二缓存块及所述缓存区内的请求信息，将包括所述第一目录及所述第二目录在内的至少两个目录发送给对应的请求信息发送端（104）。该方法能够减小读目录操作的延迟。

9. 发明申请

WO2017126924A1 이종 시스템에서의 데이터 분배 기법 审中-公开
标题翻译：异构系统中的数据分发技术
公开(公告)号：WO2017126924A1
公开(公告)日：2017-07-27
申请号：PCT/KR2017/000694
申请日：2017-01-19
申请人： 서울대학교 산학협력단
发明人： 이재진 , 조강원
IPC分类号： G06F9/54 , G06F12/0804 , G06F12/0806 , G06F13/16
CPC分类号： G06F9/54 , G06F12/0804 , G06F12/0806 , G06F13/16
摘要： 본 발명은 이종 시스템에서의 데이터 분배 기법에 관한 것이다. 본 발명의 제 1 측면에 따르면 적어도 하나의 계산 디바이스를 포함하는 이종 시스템에서의 데이터 분배 기법을 수행하는 시스템에 있어서, 상기 이종 시스템에서 수행되는 커널의 복수의 워크 아이템들의 수행에 필요한 데이터가 저장되는 버퍼를 가상 디바이스 메모리 영역에 할당하는 버퍼할당부 및 상기 복수의 워크 아이템 중 어느 하나의 계산 디바이스에서 처리되는 워크아이템이 이용하는 데이터를 저장하는 부분버퍼로 상기 버퍼에 저장된 데이터를 분배하는 데이터분배부를 포함할 수 있다.
摘要翻译：本发明涉及异构系统中的数据分配技术。根据本发明，用于执行在非均相系统中的数据发布方法中的至少一个包括一个计算装置，其中用于执行多个内核的工作项目的所需的数据在非均相体系中进行的系统的第一个方面被存储它包括分配到缓冲器来分配在虚拟设备的存储区的缓冲区，并且所述多个工作项目的任何节缓冲器的计算来存储利用工作项数据在装置部分数据分配要被处理用于分配存储在所述缓冲器中的数据的你可以做到。

10. 发明申请

WO2017048659A1 PREFETCHING INSTRUCTION BLOCKS 审中-公开
标题翻译：预制指令块
公开(公告)号：WO2017048659A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051420
申请日：2016-09-13
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C.
IPC分类号： G06F12/0806 , G06F9/38
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Technology related to prefetching instruction blocks is disclosed. In one example of the disclosed technology, a processor comprises a block-based processor core for executing a program comprising a plurality of instruction blocks. The block-based processor core can include prefetch logic and a local buffer. The prefetch logic can be configured to receive a reference to a predicted instruction block and to determine a mapping of the predicted instruction block to one or more lines. The local buffer can be configured to selectively store portions of the predicted instruction block and to provide the stored portions of the predicted instruction block when control of the program passes along a predicted execution path to the predicted instruction block.
摘要翻译：公开了与预取指令块有关的技术。在所公开技术的一个示例中，处理器包括用于执行包括多个指令块的程序的基于块的处理器核心。基于块的处理器核心可以包括预取逻辑和本地缓冲器。预取逻辑可以被配置为接收对预测指令块的引用，并且确定预测指令块与一行或多行的映射。本地缓冲器可以被配置为选择性地存储预测指令块的部分，并且当程序的控制沿着预测执行路径传递到预测指令块时，提供预测指令块的存储部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式