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1. 发明申请

WO2018125501A1 APPARATUSES AND METHODS FOR MULTILANE UNIVERSAL SERIAL BUS (USB2) COMMUNICATION OVER EMBEDDED UNIVERSAL SERIAL BUS (eUSB2) 审中-公开
公开(公告)号：WO2018125501A1
公开(公告)日：2018-07-05
申请号：PCT/US2017/063931
申请日：2017-11-30
申请人： INTEL CORPORATION
发明人： SRIVASTAVA, Amit Kumar
IPC分类号： G06F13/38 , G06F13/42
CPC分类号： G06F13/4282 , G06F13/287 , G06F13/387 , G06F2213/0026 , G06F2213/4002 , Y02D10/14 , Y02D10/151
摘要： Methods and apparatuses relating to circuitry for multilane serial bus communications are described. In an embodiment, an apparatus includes a serial bus controller, upstream serial bus lanes, a single downstream serial bus lane, and a host/device lane controller. The serial bus controller is to send and receive data transmissions to and from serial bus devices. The upstream serial bus lanes correspond to the serial bus devices and are associated with serial port addresses. The host/device lane controller is to receive data transmissions through the upstream serial bus lanes and includes a port address assignment circuit and a multiplexer. The port address assignment circuit is to assign serial port addresses to data transmissions, to be included in data transmissions to identify the upstream serial bus lanes through which the data transmission was received. The multiplexer is to forward data transmissions from upstream serial bus lanes to the downstream serial bus lane.

2. 发明申请

WO2018097867A1 MODULAR LIGHTING AND ANCILLARY COMPONENT APPARATUS AND SYSTEM 审中-公开
公开(公告)号：WO2018097867A1
公开(公告)日：2018-05-31
申请号：PCT/US2017/045899
申请日：2017-08-08
申请人： THOMAS, John-Michael
发明人： THOMAS, John-Michael
IPC分类号： F21K9/232 , G06F13/42 , H05B33/08 , H04W84/02 , F21K9/237 , G06F13/38 , H05B37/02
CPC分类号： H01R13/7175 , F21K9/23 , F21K9/232 , F21K9/237 , F21K9/238 , F21V3/02 , F21V17/002 , F21V19/0015 , F21V23/06 , F21Y2115/10 , G06F13/385 , G06F13/4282 , H01R13/665 , H04R1/028 , H04W84/02 , H05B33/0803 , H05B33/0845 , H05B33/0857 , H05B37/0254 , Y02B20/383 , Y02D10/14 , Y02D10/151
摘要： A modular lighting and ancillary component apparatus and system utilizes standard USB protocol and connections between modules so that different modules can be selected, installed, and changed by a user. The USB-C protocol is preferably used, which may permit bidirectional functionality between connected modules in an apparatus and potentially between separate apparatuses. The USB-PD protocol may also be employed so that a greater range of items can be powered. The apparatus includes a base module, and may include one or more ancillary modules and/or a light-emitting module.

3. 发明申请

WO2018055324A1 AN APPARATUS, MEMORY CONTROLLER, MEMORY MODULE AND METHOD FOR CONTROLLING DATA TRANSFER 审中-公开
标题翻译：用于控制数据传输的设备，存储器控制器，存储器模块和方法
公开(公告)号：WO2018055324A1
公开(公告)日：2018-03-29
申请号：PCT/GB2017/052224
申请日：2017-07-31
申请人： ARM LIMITED
发明人： HANSSON, Andreas , ELSASSER, Wendy Arnott , CAMPBELL, Michael Andrew
IPC分类号： G06F13/42
CPC分类号： G06F12/0623 , G06F12/084 , G06F12/0888 , G06F13/1663 , G06F13/4234 , G06F2212/6046 , Y02D10/14 , Y02D10/151
摘要： An apparatus, memory controller, memory module and method are provided for controlling data transfer in memory. The apparatus comprises a memory controller and a plurality of memory modules. The memory controller is arranged to orchestrate direct data transfer by transmitting a first direct transfer command to a first memory module and a second direct transfer command to a second memory module. The first memory module is responsive to receipt of the first direct transfer command to directly transmit the data for receipt by the second memory module in a way that bypasses the memory controller. The second memory module is responsive to the second direct transfer command to receive the data from the first memory module directly, rather than requiring the data to have been routed via the memory controller, and then stores that data in dependence on the second direct transfer command. This provides an efficient mechanism for transferring data between multiple memory modules coupled to the same memory controller.
摘要翻译：提供了用于控制存储器中的数据传输的设备，存储器控制器，存储器模块和方法。该装置包括存储器控制器和多个存储器模块。存储器控制器被配置为通过向第一存储器模块发送第一直接转移命令并向第二存储器模块发送第二直接转移命令来编排直接数据传输。第一存储器模块响应于第一直接传输命令的接收而以绕过存储器控制器的方式直接传输供第二存储器模块接收的数据。第二存储器模块响应于第二直接传输命令而直接从第一存储器模块接收数据，而不是要求数据经由存储器控制器被路由，然后根据第二直接传输命令来存储该数据。这提供了一种有效的机制，用于在连接到同一个内存控制器的多个内存模块之间传输数据。

4. 发明申请

WO2018048510A1 DEVICES, METHODS, AND GRAPHICAL USER INTERFACES FOR WIRELESS PAIRING WITH PERIPHERAL DEVICES AND DISPLAYING STATUS INFORMATION CONCERNING THE PERIPHERAL DEVICES 审中-公开
标题翻译：无线与外围设备配对以及显示外围设备状态信息的设备，方法和图形用户界面
公开(公告)号：WO2018048510A1
公开(公告)日：2018-03-15
申请号：PCT/US2017/043047
申请日：2017-07-20
申请人： APPLE INC.
发明人： BEHZADI, Arian , STACK, Caelan, G. , CHAUDHRI, Imran , COFFMAN, Patrick, L.
IPC分类号： H04M1/60 , G06F3/0484
CPC分类号： G06F3/14 , G06F3/0484 , G06F3/04883 , G06F13/128 , H04M1/6066 , Y02D10/14
摘要： In accordance with some embodiments, a method is performed at an electronic device with a display, radio frequency (RF) circuitry, and one or more input devices. The device displays a first user interface on the display. While displaying the first user interface, the device detects a pairing request to pair a first peripheral with the electronic device. In response to detecting the pairing request, the device determines whether the first peripheral meets coupling criteria, wherein the coupling criteria require that the first peripheral is coupled to a second peripheral. In accordance with a determination that the first peripheral meets the coupling criteria, the device displays a pairing affordance that initiates pairing of the electronic device with the first peripheral. In accordance with a determination that the first peripheral does not meet the coupling criteria, the device displays information concerning coupling of the first peripheral and the second peripheral.
摘要翻译：根据一些实施例，在具有显示器，射频（RF）电路和一个或多个输入设备的电子设备处执行一种方法。设备在显示器上显示第一个用户界面。在显示第一用户界面的同时，设备检测配对请求以将第一外围设备与电子设备配对。响应于检测到配对请求，设备确定第一外围设备是否满足耦合标准，其中耦合标准要求第一外围设备耦合到第二外围设备。根据第一外围设备满足耦合标准的确定，设备显示启动电子设备与第一外围设备的配对的配对可供件。根据确定第一外围设备不符合耦合标准，设备显示关于第一外围设备和第二外围设备的耦合的信息。

5. 发明申请

WO2018034003A1 電気機器、電力制御システム、電力制御方法及びプログラム审中-公开
标题翻译：电器，电源控制系统，电源控制方法和程序
公开(公告)号：WO2018034003A1
公开(公告)日：2018-02-22
申请号：PCT/JP2016/074257
申请日：2016-08-19
申请人：三菱電機株式会社
发明人：遠藤　聡 , 樋熊　利康
IPC分类号： H02J3/14 , G06F13/00
CPC分类号： G06F13/00 , H02J3/14 , Y02B70/3225 , Y02D10/14 , Y04S20/222
摘要：電気機器（３０）は、住宅に設置されて送信装置（２０）に接続される。電気機器（３０）は、住宅に電力線を介して供給される総電力の基準値と、総電力の計測値と総電力の目標値との差と、の比を示すデータであって、送信装置（２０）から同報送信されるデータを繰り返し受信する受信部（３０１）と、電気機器（３０）が消費する電力である機器電力を計測して機器電力の計測値を出力する計測部（３０４）と、電気機器（３０）の稼働状態を、比と機器電力の計測値とに対応する予め定められた状態に変更することで、機器電力を制御して差の大きさを小さくする制御部（３０５）と、を備える。
摘要翻译：电气设备（30）安装在房屋中并连接到发送设备（20）。电气设备（30）是表示经由电力线向住宅供给的总电力的基准值，总电力的测量值与总电力的目标值之差与电力设备的比率的数据（301），其重复接收从测量单元（20）广播发送的数据;测量单元（304），其测量由电气设备（30）消耗的电力，并输出设备电力的测量值）;控制单元，用于将电子设备（30）的操作状态改变为与设备电力的比率和测量值对应的预定状态，以控制设备电力以减小差值的大小和（305），包括：a。

6. 发明申请

WO2018022498A1 TIME-SEQUENCED MULTI-DEVICE ADDRESS ASSIGNMENT 审中-公开
标题翻译：时间顺序的多器件地址分配
公开(公告)号：WO2018022498A1
公开(公告)日：2018-02-01
申请号：PCT/US2017/043488
申请日：2017-07-24
申请人： QUALCOMM INCORPORATED
发明人： MISHRA, Lalan, Jee , PITIGOI-ARON, Radu , WIETFELDT, Richard, Dominic
IPC分类号： G06F13/37
CPC分类号： H04L61/2061 , G06F13/37 , H04L12/40013 , H04W52/0235 , H04W72/1263 , Y02D10/14 , Y02D70/00 , Y02D70/142 , Y02D70/144
摘要： Time-sequenced multi-device address assignment is provided. In this regard, an electronic device includes a plurality of client devices that are daisy-chained to a host interface port in a host controller by a reset line. The host controller is configured to assert the reset line to reset the daisy-chained client devices and then sequentially de-assert the reset line for the daisy-chained client devices according to a determined time sequence. Accordingly, the host controller assigns a unique client device address to each of the client devices when the reset line is de-asserted for the client device. By daisy-chaining the client devices via the reset line and sequentially assigning the unique client device addresses based on the determined time sequence, it is possible to assign the unique client device addresses from a single host interface port, thus reducing design complexity, footprint, and power consumption in the electronic device.
摘要翻译：
提供时间顺序的多设备地址分配。就这一点而言，电子设备包括多个客户端设备，所述多个客户端设备通过重置线路以菊花链形式链接到主机控制器中的主机接口端口。主机控制器被配置为断言重置线以重置菊花链式客户端设备，然后根据确定的时间顺序依次取消菊花链式客户端设备的重置线。因此，当针对客户端设备重置线被解除断言时，主机控制器向每个客户端设备分配唯一的客户端设备地址。通过经由重置线菊花链连接客户端设备并基于所确定的时间顺序顺序地分配唯一客户端设备地址，可以从单个主机接口端口分配唯一客户端设备地址，从而降低设计复杂度，占用空间，和电子设备的功耗。

7. 发明申请

WO2017078681A1 OPERATING MODE MEMORY MIGRATION 审中-公开
标题翻译：操作模式存储器迁移
公开(公告)号：WO2017078681A1
公开(公告)日：2017-05-11
申请号：PCT/US2015/058787
申请日：2015-11-03
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
发明人： HAAS COSTA, Carlos , PERONE, Christian S. , RAHN MEDAGLIA, Diego
IPC分类号： G06F12/06 , G06F13/16 , G06F12/10
CPC分类号： G06F13/16 , Y02D10/14
摘要： Examples include a system comprising a non-volatile memory and a volatile memory. Examples migrate system memory between the volatile memory and the non-volatile memory. After migration, examples translate virtual addresses to physical memory addresses corresponding to the volatile memory and/or non-volatile memory.
摘要翻译：示例包括包括非易失性存储器和易失性存储器的系统。示例在易失性存储器和非易失性存储器之间迁移系统存储器。迁移后，示例将虚拟地址转换为与易失性存储器和/或非易失性存储器对应的物理存储器地址。

8. 发明申请

WO2017048661A1 BLOCK-BASED PROCESSOR CORE TOPOLOGY REGISTER 审中-公开
标题翻译：基于块的处理器核心拓扑寄存器
公开(公告)号：WO2017048661A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051423
申请日：2016-09-13
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F15/78 , G06F9/38
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Systems, apparatuses, and methods related to a block-based processor core topology register are disclosed. In one example of the disclosed technology, a processor can include a plurality of block-based processor cores for executing a program including a plurality of instruction blocks. A respective block-based processor core can include a sharable resource and a programmable composition topology register. The programmable composition topology register can be used to assign a group of the physical processor cores that share the sharable resource.
摘要翻译：公开了与基于块的处理器核心拓扑寄存器相关的系统，装置和方法。在所公开的技术的一个示例中，处理器可以包括多个基于块的处理器核，用于执行包括多个指令块的程序。相应的基于块的处理器核心可以包括可共享资源和可编程组合拓扑寄存器。可编程组合拓扑寄存器可用于分配一组共享可共享资源的物理处理器内核。

9. 发明申请

WO2017048647A1 IMPLICIT PROGRAM ORDER 审中-公开
标题翻译：暗示程序令
公开(公告)号：WO2017048647A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/051408
申请日：2016-09-13
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for controlling execution of memory access instructions in a block-based processor architecture using a hardware structure that generates a relative ordering of memory access instruction in an instruction block. In one example of the disclosed technology, a method of executing an instruction block having a plurality of memory load and/or memory store instructions includes decoding an instruction block encoding a plurality of memory access instructions and generating data indicating a relative order for executing the memory access instructions in the instruction block and scheduling operation of a portion of the instruction block based at least in part on the relative order data. In some examples, a store vector data register can store the generated relative ordering data for use in subsequent instances of the instruction block.
摘要翻译：公开了用于在基于块的处理器架构中使用生成指令块中的存储器访问指令的相对排序的硬件结构来控制存储器访问指令的执行的装置和方法。在所公开的技术的一个示例中，执行具有多个存储器加载和/或存储器存储指令的指令块的方法包括对编码多个存储器访问指令的指令块进行解码，并产生指示执行存储器的相对次序的数据指令块中的访问指令和指令块的一部分的调度操作至少部分地基于相对顺序数据。在一些示例中，存储向量数据寄存器可以存储所生成的相关订购数据，以供在指令块的后续实例中使用。

10. 发明申请

WO2017030871A1 A ROBUST MECHANISM FOR ADAPTIVE POWER CONSERVATION IN SOLID-STATE DEVICES 审中-公开
标题翻译：一种在固态设备中自适应功率保存的稳定机制
公开(公告)号：WO2017030871A1
公开(公告)日：2017-02-23
申请号：PCT/US2016/046365
申请日：2016-08-10
申请人： APPLE INC.
发明人： ADAVI, Bhaskar R. , SARCONE, Christopher J. , RADHAKRISHNAN, Manoj K.
IPC分类号： G06F1/32 , G06F3/06
CPC分类号： G06F3/06 , G06F1/3225 , G06F1/3268 , G06F1/3275 , Y02D10/14 , Y02D10/154
摘要： Disclosed herein is a technique for dynamically scaling a low-power self-refresh (LPSR) idle interval associated with a solid state drive (SSD) of a user device in order to promote enhanced battery life efficiency within the user device. A determination can be made regarding whether the LPSR idle interval is to be scaled up or scaled down. Specifically, the determination is based on a total elapsed since the user device was first powered on and a total number of LPSR transitions or cycles that have been performed in association with the SSD. In turn, the dynamic scaling of the LPSR idle intervals causes NAND power-cycles to be consumed responsibly over an average system lifetime of the user device, which can result in better power management at the user device.
摘要翻译：本文公开了一种用于动态地缩放与用户设备的固态驱动器（SSD）相关联的低功率自刷新（LPSR）空闲间隔的技术，以便在用户设备内促进增强的电池寿命效率。可以确定LPSR空闲间隔是放大还是缩小。具体地，该确定基于从用户设备第一次通电开始的总经过量以及已经与SSD相关联地执行的LPSR转换或周期的总数。反过来，LPSR空闲间隔的动态缩放导致NAND功率周期在用户设备的平均系统寿命内被负责地消耗，这可以导致用户设备的更好的功率管理。

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