专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2012120267A1 ADDRESS GENERATION IN A DATA PROCESSING APPARATUS 审中-公开
标题翻译：数据处理设备中的地址生成
公开(公告)号：WO2012120267A1
公开(公告)日：2012-09-13
申请号：PCT/GB2012/050158
申请日：2012-01-26
申请人： ARM LIMITED , STEPHENS, Nigel John , SEAL, David James
发明人： STEPHENS, Nigel John , SEAL, David James
IPC分类号： G06F9/34 , G06F9/30 , G06F9/32 , G06F9/355
CPC分类号： G06F9/3557 , G06F9/30007 , G06F9/30112 , G06F9/30167 , G06F9/342 , G06F9/345 , G06F2212/657
摘要： A data processing apparatus is provided comprising processing circuitry and an instruction decoder responsive to program instructions to control processing circuitry to perform the data processing. The instruction decoder is responsive to an address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value such that a full address specifying a memory location of an information entity is calculable from said partial address result using at least one supplementary program instruction. The partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction. A corresponding data processing method, virtual machine and computer program product are also provided.
摘要翻译：提供了一种数据处理装置，其包括响应于程序指令的处理电路和指令解码器，以控制处理电路执行数据处理。指令解码器响应于地址计算指令来执行地址计算操作，用于从非固定参考地址和部分偏移值计算部分地址结果，使得可以从...计算指定信息实体的存储位置的完整地址所述部分地址结果使用至少一个补充程序指令。部分偏移值具有大于或等于所述指令大小的位宽，并且被编码在所述地址计算指令的至少一个部分偏移字段内。还提供了相应的数据处理方法，虚拟机和计算机程序产品。

2. 发明申请

WO2012087446A1 SYSTEM, APPARATUS, AND METHOD FOR SEGMENT REGISTER READ AND WRITE REGARDLESS OF PRIVILEGE LEVEL 审中-公开
标题翻译：系统，设备和分段注册读取和写入权限的优先权级别
公开(公告)号：WO2012087446A1
公开(公告)日：2012-06-28
申请号：PCT/US2011/060011
申请日：2011-11-09
申请人： INTEL CORPORATION , PATEL, Baiju V. , NEIGER, Gilbert , DIXON, Martin G. , COKE, James S. , CROSSLAND, James B.
发明人： PATEL, Baiju V. , NEIGER, Gilbert , DIXON, Martin G. , COKE, James S. , CROSSLAND, James B.
IPC分类号： G06F9/30 , G06F9/06
CPC分类号： G06F9/30032 , G06F9/30101 , G06F9/342
摘要： Embodiments of systems, apparatuses, and methods for performing privilege agnostic segment base register read or write instruction are described. An exemplary method may include fetching the privilege agnostic segment base register write instruction, wherein the privilege agnostic write instruction includes a 64-bit data source operand, decoding the fetched privilege agnostic segment base register write instruction, and executing the decoded privilege agnostic segment base register write instruction to write the 64-bit data of the source operand into the segment base register identified by the opcode of the privilege agnostic segment base register write instruction.
摘要翻译：描述用于执行特权不可知段段基址寄存器读或写指令的系统，装置和方法的实施例。一种示例性方法可以包括获取特权不可知段基址寄存器写指令，其中特权不可知写指令包括64位数据源操作数，对获取的特权不可知段基址寄存器写指令进行解码，以及执行解码的特权不可知段基址寄存器写指令将源操作数的64位数据写入由特权不可知段基址寄存器写指令的操作码标识的段基寄存器中。

3. 发明申请

WO2010093661A2 MICROCONTROLLER WITH SPECIAL BANKING INSTRUCTIONS 审中-公开
标题翻译：具有特殊银行指示的微控制器
公开(公告)号：WO2010093661A2
公开(公告)日：2010-08-19
申请号：PCT/US2010/023706
申请日：2010-02-10
申请人： MICROCHIP TECHNOLOGY INCORPORATED , LUNDSTRUM, Zeke, R. , DELPORT, Vivien , STEEDMAN, Sean , JULICHER, Joseph
发明人： LUNDSTRUM, Zeke, R. , DELPORT, Vivien , STEEDMAN, Sean , JULICHER, Joseph
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30101 , G06F9/30145 , G06F9/30167 , G06F9/342 , G06F9/35 , G06F12/0623
摘要： An instruction set for a microcontroller with a data memory divided into a plurality of memory banks wherein the data memory has more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped, a bank select register which is not mapped to the data memory for selecting a memory bank, and with an indirect access register mapped to at least one memory bank, wherein the instruction set includes a plurality of instructions operable to directly address all memory locations within a selected bank, at least one instruction that provides access to the bank select register, and at least one instruction performing an indirect address to the data memory using the indirect access register.
摘要翻译：一种用于具有划分成多个存储体的数据存储器的微控制器的指令集，其中数据存储器具有多个存储体的多于一个存储体，其形成没有特殊功能寄存器映射的线性数据存储器块，没有映射到用于选择存储体的数据存储器并且映射到至少一个存储体的间接访问寄存器的存储体选择寄存器，其中指令集包括可以直接寻址一个存储体内的所有存储器位置的多个指令至少一个提供对存储体选择寄存器的访问的指令，以及使用间接访问寄存器向数据存储器执行间接地址的至少一个指令。

4. 发明申请

WO2008061154A9 APPARATUS AND METHOD FOR PROCESSING COMPLEX INSTRUCTION FORMATS IN A MULTI-THREADED ARCHITECTURE SUPPORTING VARIOUS CONTEXT SWITCH MODES AND VIRTUALIZATION SCHEMES 审中-公开
标题翻译：在支持各种上下文切换模式和虚拟化方案的多线程架构中处理复杂指令格式的装置和方法
公开(公告)号：WO2008061154A9
公开(公告)日：2008-07-03
申请号：PCT/US2007084710
申请日：2007-11-14
申请人： SOFT MACHINES INC , ABDALLAH MOHAMMAD
发明人： ABDALLAH MOHAMMAD
IPC分类号： G06F19/00
CPC分类号： G06F9/34 , G06F9/30043 , G06F9/3009 , G06F9/30123 , G06F9/30134 , G06F9/30138 , G06F9/3016 , G06F9/342 , G06F9/3808 , G06F9/3824 , G06F9/3826 , G06F9/383 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3853 , G06F9/3857 , G06F9/3885 , G06F9/3891 , G06F9/462 , G06F9/4843
摘要： A unified architecture for dynamic generation, execution, synchronization and paralleli
摘要翻译：用于动态生成，执行，同步和并行的统一架构

5. 发明申请

WO2004099950A1 INSTRUCTIONS TO ASSIST THE PROCESSING OF A CIPHER MESSAGE 审中-公开
标题翻译：帮助加油机信息的指示
公开(公告)号：WO2004099950A1
公开(公告)日：2004-11-18
申请号：PCT/GB2004/001928
申请日：2004-05-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , LUNDVALL, Shawn , SMITH, Ronald , YEH, Phil, Chi-Chung
发明人： LUNDVALL, Shawn , SMITH, Ronald , YEH, Phil, Chi-Chung
IPC分类号： G06F1/00
CPC分类号： G06F9/45504 , G06F9/30007 , G06F9/30018 , G06F9/30094 , G06F9/3017 , G06F9/30181 , G06F9/342 , G06F21/72 , H04L9/08
摘要： A method, system and program product for enciphering or deciphering storage of a computing environment by specifying, via an instruction, a unit of storage to be enciphered or deciphered.
摘要翻译：一种通过指定要加密或解密的存储单元来加密或解密计算环境的存储的方法，系统和程序产品。

6. 发明申请

WO2002099634A1 DYNAMICALLY RECONFIGURABLE DATA SPACE 审中-公开
标题翻译：动态可重构数据空间
公开(公告)号：WO2002099634A1
公开(公告)日：2002-12-12
申请号：PCT/US2002/016970
申请日：2002-05-30
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： CATHERWOOD, Michael , TRIECE, Joseph, W. , PYSKA, Michael , CONNER, Joshua, M.
IPC分类号： G06F9/38
CPC分类号： G06F9/342 , G06F9/30185 , G06F9/345 , G06F12/0284 , G06F12/109
摘要： A processor is provided that has a data memory that may be addressed as a dual memory space in one mode and as a single linear memory space in another mode. The memory may permit dual concurrent operand fetches from the data memory when DSP instructions are processed. The memory may then dynamically permit the same memory to be accessed as a single linear memory address space for non-DSP instructions.
摘要翻译：提供了一种处理器，其具有数据存储器，该数据存储器可以以一种模式被寻址为双存储器空间，并且在另一种模式下可以被寻址为单个线性存储器空当处理DSP指令时，存储器可能允许从数据存储器获取双重并发操作数。然后，存储器可以动态地允许相同的存储器作为用于非DSP指令的单个线性存储器地址空间被访问。

7. 发明申请

WO2015144489A1 MULTITHREADING CAPABILITY INFORMATION RETRIEVAL 审中-公开
标题翻译：多元化能力信息检索
公开(公告)号：WO2015144489A1
公开(公告)日：2015-10-01
申请号：PCT/EP2015/055516
申请日：2015-03-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED
发明人： GREINER, Dan , FARRELL, Mark , OSISEK, Damian, Leo , SCHMIDT, Donald, William , BUSABA, Fadi, Yusuf , KUBALA, Jeffrey, Paul , BRADBURY, Jonathan, David , HELLER, Lisa, Cranton , SLEGEL, Timothy
IPC分类号： G06F9/50 , G06F9/38
CPC分类号： G06F9/30181 , G06F9/30076 , G06F9/30189 , G06F9/342 , G06F9/3851 , G06F9/4881 , G06F9/50
摘要： Embodiments relate to multithreading capability information retrieval. An aspect is a computer system includes a configuration with one or more cores configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of each core. The computer system also includes a multithreading facility configured to control utilization of the configuration to perform a method that includes executing, by the core, a retrieve multithreading capability information instruction. The execution includes obtaining thread identification information that identifies multithreading capability of the configuration, and storing the obtained thread identification information.
摘要翻译：实施例涉及多线程能力信息检索。一个方面是一种计算机系统，其包括具有在单线程（ST）模式和多线程（MT））模式之间可配置的一个或多个核心的配置。 ST模式寻址主线程，MT模式寻址主线程和每个内核共享资源上的一个或多个辅助线程。计算机系统还包括配置成控制配置的利用以执行包括通过核心执行检索多线程能力信息指令的方法的多线程设施。执行包括获得标识配置的多线程能力的线程标识信息，并存储所获得的线程标识信息。

8. 发明申请

WO2013050923A1 LINKING CODE FOR AN ENHANCED APPLICATION BINARY INTERFACE (ABI) WITH DECODE TIME INSTRUCTION OPTIMIZATION 审中-公开
标题翻译：链接代码用于增强应用二进制接口（ABI）与解码时间指令优化
公开(公告)号：WO2013050923A1
公开(公告)日：2013-04-11
申请号：PCT/IB2012/055255
申请日：2012-10-01
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM (CHINA) INVESTMENT COMPANY LIMITED
发明人： BLAINEY, Robert, James , GSCHWIND, Michael, Karl , MCINNES, James, Lawrence , MUNROE, Steven, Jay , MEISSNER, Michael
IPC分类号： G06F9/45
CPC分类号： G06F8/54 , G06F9/3017 , G06F9/342
摘要： A code sequence made up multiple instructions and specifying an offset from a base address is identified in an object file. The offset from the base address corresponds to an offset location in a memory configured for storing an address of a variable or data. The identified code sequence is configured to perform a memory reference function or a memory address computation function. It is determined that the offset location is within a specified distance of the base address and that a replacement of the identified code sequence with a replacement code sequence will not alter program semantics. The identified code sequence in the object file is replaced with the replacement code sequence that includes a no-operation (NOP) instruction or having fewer instructions than the identified code sequence. Linked executable code is generated based on the object file and the linked executable code is emitted.
摘要翻译：在目标文件中标识由多个指令构成的代码序列并指定与基地址的偏移量。与基地址的偏移量对应于配置为存储变量或数据地址的存储器中的偏移位置。所识别的代码序列被配置为执行存储器引用功能或存储器地址计算功能。确定偏移位置在基地址的指定距离内，并且用替换代码序列替换所识别的代码序列将不会改变程序语义。目标文件中所识别的代码序列被替换为包含无操作（NOP）指令或具有比识别的代码序列少的指令的替换代码序列。链接的可执行代码是基于目标文件生成的，并且发送链接的可执行代码。

9. 发明申请

WO2010093661A3 MICROCONTROLLER WITH SPECIAL BANKING INSTRUCTIONS 审中-公开
标题翻译：带有特殊银行指令的微控制器
公开(公告)号：WO2010093661A3
公开(公告)日：2010-11-25
申请号：PCT/US2010023706
申请日：2010-02-10
申请人： MICROCHIP TECH INC , LUNDSTRUM ZEKE R , DELPORT VIVIEN , STEEDMAN SEAN , JULICHER JOSEPH
发明人： LUNDSTRUM ZEKE R , DELPORT VIVIEN , STEEDMAN SEAN , JULICHER JOSEPH
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30101 , G06F9/30145 , G06F9/30167 , G06F9/342 , G06F9/35 , G06F12/0623
摘要： An instruction set for a microcontroller with a data memory divided into a plurality of memory banks wherein the data memory has more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped, a bank select register which is not mapped to the data memory for selecting a memory bank, and with an indirect access register mapped to at least one memory bank, wherein the instruction set includes a plurality of instructions operable to directly address all memory locations within a selected bank, at least one instruction that provides access to the bank select register, and at least one instruction performing an indirect address to the data memory using the indirect access register.
摘要翻译：一种用于具有被分成多个存储体的数据存储器的微控制器的指令集，其中数据存储器具有形成线性数据存储器块的多个存储体中的多于一个存储体，其中没有特殊功能寄存器被映射到所述线性数据存储体块，没有被映射到数据存储器以用于选择存储体的存储体选择寄存器以及被映射到至少一个存储体的间接访问寄存器，其中所述指令集包括多个指令，所述指令可操作以直接寻址至少一个提供对所述银行选择寄存器的访问的指令，以及至少一个使用所述间接访问寄存器对所述数据存储器执行间接地址的指令。

10. 发明申请

WO2010093657A2 MICROCONTROLLER WITH LINEAR MEMORY IN A BANKED MEMORY 审中-公开
标题翻译：具有线性记忆的微控制器在银行存储器中
公开(公告)号：WO2010093657A2
公开(公告)日：2010-08-19
申请号：PCT/US2010/023701
申请日：2010-02-10
申请人： MICROCHIP TECHNOLOGY INCORPORATED , LUNDSTRUM, Zeke, R. , DELPORT, Vivien , STEEDMAN, Sean , JULICHER, Joseph
发明人： LUNDSTRUM, Zeke, R. , DELPORT, Vivien , STEEDMAN, Sean , JULICHER, Joseph
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30101 , G06F9/30145 , G06F9/30167 , G06F9/342 , G06F9/35 , G06F12/0623
摘要： A microcontroller has a data memory divided into a plurality of memory banks, an address multiplexer for providing an address to the data memory, an instruction register providing a first partial address to a first input of the address multiplexer, a bank select register which is not mapped to the data memory for providing a second partial address to a the first input of the address multiplexer, and a plurality of special function registers mapped to the data memory, wherein the plurality of special function registers comprises an indirect access register coupled with a second input of the address multiplexer, and wherein the data memory comprises more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped.
摘要翻译：微控制器具有分成多个存储体的数据存储器，用于向数据存储器提供地址的地址多路复用器，向地址多路复用器的第一输入端提供第一部分地址的指令寄存器，不是地址复用器的存储体选择寄存器映射到数据存储器，用于向地址多路复用器的第一输入提供第二部分地址，以及映射到数据存储器的多个特殊功能寄存器，其中多个特殊功能寄存器包括与第二个地址多路复用器的输入，并且其中数据存储器包括多个存储器组中的多于一个存储器组，其形成没有映射特殊功能寄存器的线性数据存储器块。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式