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1. 发明申请

WO2008073741A1 METHODS AND APPARATUS FOR LOW-COMPLEXITY INSTRUCTION PREFETCH SYSTEM 审中-公开
标题翻译：低复杂度指导预制系统的方法和装置
公开(公告)号：WO2008073741A1
公开(公告)日：2008-06-19
申请号：PCT/US2007/086254
申请日：2007-12-03
申请人： QUALCOMM Incorporated , MORROW, Michael William , DIEFFENDERFER, James Norris
发明人： MORROW, Michael William , DIEFFENDERFER, James Norris
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3802 , G06F12/0862
摘要： When misses occur in an instruction cache, prefetching techniques are used that minimize miss rates, memory access bandwidth, and power use. One of the prefetching techniques operates when a miss occurs. A notification that a fetch address missed in an instruction cache is received. The fetch address that caused the miss is analyzed to determine an attribute of the fetch address and based on the attribute a line of instructions is prefetched. The attribute may indicate that the fetch address is a target address of a non-sequential operation. Another attribute may indicate that the fetch address is a target address of a non-sequential operation and the target address is more than X% into a cache line. A further attribute may indicate that the fetch address is an even address in the instruction cache. Such attributes may be combined to determine whether to prefetch.
摘要翻译：当在指令高速缓存中发生错误时，使用预取技术来最小化错误率，存储器访问带宽和功率使用。当缺失发生时，预取技术之一运行。接收到在指令高速缓存中丢失的获取地址的通知。分析导致遗漏的提取地址，以确定提取地址的属性，并根据属性预取一行指令。该属性可以指示提取地址是非顺序操作的目标地址。另一个属性可以指示提取地址是非顺序操作的目标地址，并且目标地址大于高速缓存行中的X％。进一步的属性可以指示提取地址是指令高速缓存中的偶数地址。可以组合这些属性以确定是否预取。

2. 发明申请

WO2014152064A1 METHOD AND APPARATUS FOR FORWARDING LITERAL GENERATED DATA TO DEPENDENT INSTRUCTIONS MORE EFFICIENTLY USING A CONSTANT CACHE 审中-公开
标题翻译：使用恒定缓存更有效地将文献生成数据转发给相关指令的方法和装置
公开(公告)号：WO2014152064A1
公开(公告)日：2014-09-25
申请号：PCT/US2014/026907
申请日：2014-03-14
申请人： QUALCOMM INCORPORATED
发明人： DIEFFENDERFER, James Norris , MORROW, Michael William , SMITH, Rodney Wayne , SCHOTTMILLER, Jeffery M. , HIGDON, Daniel S. , MCILVAINE, Michael Scott , STEMPEL, Brian Michael , KOTHARI, Kulin Narendra
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3832 , G06F9/30032 , G06F9/3828
摘要： A processor to a store constant value (immediate or literal) in a cache upon decoding a move immediate instruction in which the immediate is to be moved (copied or written) to an architected register. The constant value is stored in an entry in the cache. Each entry in the cache includes a field to indicate whether its stored constant value is valid, and a field to associate the entry with an architected register. Once a constant value is stored in the cache, it is immediately available for forwarding to a processor pipeline where a decoded instruction may need the constant value as an operand.
摘要翻译：解码将立即数移动（复制或写入）到结构化寄存器的移动即时指令时，缓存中存储恒定值（立即数或立即数）的处理器。常量值存储在缓存中的条目中。缓存中的每个条目包括一个字段，用于指示其存储的常量值是否有效，以及一个字段，用于将条目与架构化寄存器相关联。一旦常数值被存储在高速缓存中，则立即可以转发到处理器流水线，其中解码的指令可能需要常数值作为操作数。

3. 发明申请

WO2014025815A1 FUSING FLAG-PRODUCING AND FLAG-CONSUMING INSTRUCTIONS IN INSTRUCTION PROCESSING CIRCUITS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA 审中-公开
标题翻译：指令处理电路中的熔接生产和标签消费指令以及相关处理器系统，方法和计算机可读介质
公开(公告)号：WO2014025815A1
公开(公告)日：2014-02-13
申请号：PCT/US2013/053844
申请日：2013-08-06
申请人： QUALCOMM INCORPORATED
发明人： IRWIN, Andrew S. , DIEFFENDERFER, James Norris , BROWN, Melinda J , SCHOTTMILLER, Jeffery M. , STEMPEL, Brian Michael , MCILVAINE, Michael Scott , SMITH, Rodney Wayne , MORROW, Michael William
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F9/30072
摘要： Fusing flag-producing and flag-consuming instructions in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a flag-producing instruction indicating a first operation generating a first flag result is detected in an instruction stream by an instruction processing circuit. The instruction processing circuit also detects a flag-consuming instruction in the instruction stream indicating a second operation consuming the first flag result as an input. The instruction processing circuit generates a fused instruction indicating the first operation generating the first flag result and indicating the second operation consuming the first flag result as the input. In this manner, as a non-limiting example, the fused instruction eliminates a potential for a read-after-write hazard between the flag-producing instruction and the flag-consuming instruction.
摘要翻译：公开了在指令处理电路和相关处理器系统，方法和计算机可读介质中对产生标记和标记消息的指令进行融合。在一个实施例中，指令处理电路在指令流中检测指示产生第一标志结果的第一操作的标志产生指令。指令处理电路还检测指示流中指示消耗第一标志结果的第二操作的指令消息指令作为输入。指令处理电路产生指示第一操作的融合指令，该第一操作产生第一标志结果并指示第二操作消耗第一标志结果作为输入。以这种方式，作为非限制性示例，融合指令消除了标志产生指令和标志消耗指令之间的写后读取危险的可能性。

4. 发明申请

WO2013173552A1 A MULTI LEVEL INDIRECT PREDICTOR USING CONFIDENCE COUNTER AND PROGRAM COUNTER ADDRESS FILTER SCHEME 审中-公开
标题翻译：使用信心计数器和程序计数器地址过滤器方案的多级间接预测
公开(公告)号：WO2013173552A1
公开(公告)日：2013-11-21
申请号：PCT/US2013/041293
申请日：2013-05-16
申请人： QUALCOMM INCORPORATED
发明人： KOTHARI, Kulin N. , MORROW, Michael William , DIEFFENDERFER, James Norris , MCILVAINE, Michael Scott , STEMPEL, Brian Michael , STREETT, Daren Eugene
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3844 , G06F9/3848
摘要： The disclosure relates to predicting simple and polymorphic branch instructions. An embodiment of the disclosure detects that a program instruction is a branch instruction, determines whether a program counter for the branch instruction is stored in a program counter filter, and, if the program counter is stored in the program counter filter, prevents the program counter from being stored in a first level predictor.
摘要翻译：本公开涉及预测简单和多态分支指令。本公开的实施例检测到程序指令是分支指令，确定用于分支指令的程序计数器是否存储在程序计数器滤波器中，并且如果程序计数器存储在程序计数器滤波器中，则防止程序计数器从存储在第一级预测器中。

5. 发明申请

WO2008092032A1 METHOD AND APPARATUS FOR SETTING CACHE POLICIES IN A PROCESSOR 审中-公开
标题翻译：用于在处理器中设置高速缓存的方法和装置
公开(公告)号：WO2008092032A1
公开(公告)日：2008-07-31
申请号：PCT/US2008/051953
申请日：2008-01-24
申请人： QUALCOMM Incorporated , MORROW, Michael William
发明人： MORROW, Michael William
IPC分类号： G06F12/12 , G06F12/08
CPC分类号： G06F12/121 , G06F12/0804 , G06F12/0888 , G06F12/0897 , G06F12/1027
摘要： According to the methods and apparatus taught herein, processor caching policies are determined using cache policy information associated with a target memory device accessed during a memory operation. According to one embodiment of a processor, the processor comprises at least one cache and a memory management unit. The at least one cache is configured to store information local to the processor. The memory management unit is configured to set one or more cache policies for the at least one cache. The memory management unit sets the one or more cache policies based on cache policy information associated with one or more target memory devices configured to store information used by the processor.
摘要翻译：根据本文教导的方法和装置，使用与在存储器操作期间访问的目标存储器设备相关联的高速缓存策略信息来确定处理器高速缓存策略。根据处理器的一个实施例，处理器包括至少一个高速缓存和存储器管理单元。至少一个缓存被配置为存储处理器本地的信息。存储器管理单元被配置为为至少一个高速缓存设置一个或多个高速缓存策略。存储器管理单元基于与被配置为存储由处理器使用的信息的一个或多个目标存储器设备相关联的高速缓存策略信息设置一个或多个高速缓存策略。

6. 发明申请

WO2017146860A1 COMBINING LOADS OR STORES IN COMPUTER PROCESSING 审中-公开
标题翻译：计算机处理中的负载或存储组合
公开(公告)号：WO2017146860A1
公开(公告)日：2017-08-31
申请号：PCT/US2017/015117
申请日：2017-01-26
申请人： QUALCOMM INCORPORATED
发明人： JAGET, Kevin , MORROW, Michael William , DIEFFENDERFER, James Norris
IPC分类号： G06F9/30 , G06F9/38 , G06F9/345
CPC分类号： G06F9/3017 , G06F9/30021 , G06F9/3004 , G06F9/30043 , G06F9/30145 , G06F9/345 , G06F9/3455 , G06F9/3824 , G06F9/3832
摘要： Aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in processors. An exemplary method includes detecting a pattern of pipelined instructions to access memory using a first portion of available bus width and, in response to detecting the pattern, combining the pipelined instructions into a single instruction to access the memory using a second portion of the available bus width that is wider than the first portion. Devices including processors using disclosed aspects may execute currently available software in a more efficient manner without the software being modified.
摘要翻译：这里公开的各方面涉及组合指令以在处理器中处理指令时从存储器中加载数据或将数据存储在存储器中。一种示例性方法包括：检测流水线指令的模式，以使用可用总线宽度的第一部分访问存储器，并且响应于检测到模式，将流水线指令组合成单条指令以使用可用总线的第二部分访问存储器宽度比第一部分宽。包括使用所公开的方面的处理器的设备可以以更有效的方式执行当前可用的软件，而不修改软件。

7. 发明申请

WO2017030678A1 DETERMINING PREFETCH INSTRUCTIONS BASED ON INSTRUCTION ENCODING 审中-公开
标题翻译：基于指令编码确定前缀指令
公开(公告)号：WO2017030678A1
公开(公告)日：2017-02-23
申请号：PCT/US2016/041896
申请日：2016-07-12
申请人： QUALCOMM INCORPORATED
发明人： YEN, Luke , MORROW, Michael William , SPEIER, Thomas Philip , DIEFFENDERFER, James Norris
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3802 , G06F9/30043 , G06F9/30047 , G06F9/383
摘要： Systems and methods for identifying candidate load instructions for prefetch operations based on at least instruction encoding of the load instructions, include an identifier based on a function of at least one or more fields of a load instruction and optionally, a subset of bits of the PC value of the load instruction, wherein the one or more fields exclude a full address or program counter (PC) value of the load instruction. Prefetch mechanisms, including a prefetch table indexed by the identifier, can determine whether the load instruction is a candidate load instruction for prefetching load data, based on the identifier. The function may be a hash, a concatenation, or a combination thereof, of one or more bits of the one or more fields. The fields include one or more of a base register, a destination register, an immediate offset, an offset register, or other bits of instruction encoding of the load instruction.
摘要翻译：用于基于至少指令编码加载指令来识别用于预取操作的候选加载指令的系统和方法包括基于加载指令的至少一个或多个字段的功能的标识符，以及可选地，PC的位的子集值，其中一个或多个字段排除加载指令的完整地址或程序计数器（PC）值。预取机制，包括由标识符索引的预取表，可以基于标识符来确定加载指令是否是用于预取负载数据的候选加载指令。该功能可以是一个或多个字段的一个或多个比特的散列，连接或其组合。这些字段包括基本寄存器，目的地寄存器，立即偏移量，偏移寄存器或加载指令的指令编码的其他位中的一个或多个。

8. 发明申请

WO2016195848A1 MITIGATING WRONG-PATH EFFECTS IN BRANCH PREDICTION 审中-公开
标题翻译：缓解分支预测中的错误路径效应
公开(公告)号：WO2016195848A1
公开(公告)日：2016-12-08
申请号：PCT/US2016/029484
申请日：2016-04-27
申请人： QUALCOMM INCORPORATED
发明人： REDDY, Vimal Kodandarama , CHOUDHARY, Niket Kumar , MCILVAINE, Michael Scott , STREETT, Daren Eugene , CLANCY, Robert Douglas , DIEFFENDERFER, James Norris , MORROW, Michael William
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/30058 , G06F9/3844
摘要： Systems and methods for mitigating influence of wrong-path branch instructions in branch prediction include a branch prediction write queue. A first entry of the branch prediction write queue is associated with a first branch instruction based on an order in which the first branch instruction is fetched. Upon speculatively executing the first branch instruction, a correct direction of the first branch instruction is written in the first entry. Prior to committing the first branch instruction, the branch prediction write queue is configured to update one or more branch prediction mechanisms based on the first entry if the first branch instruction was speculatively executed in a correct-path. Updates to the one or more branch prediction mechanisms based on the first entry are prevented if the first branch instruction was speculatively executed in a wrong-path.
摘要翻译：用于减轻分支预测中错误路径分支指令的影响的系统和方法包括分支预测写入队列。分支预测写入队列的第一条目基于获取第一分支指令的顺序与第一分支指令相关联。在推测性地执行第一分支指令时，在第一条目中写入第一分支指令的正确方向。在提交第一分支指令之前，如果在正确路径中推测性地执行第一分支指令，则分支预测写入队列被配置为基于第一条目来更新一个或多个分支预测机制。如果在错误路径中推测性地执行第一分支指令，则可以防止基于第一条目对一个或多个分支预测机制的更新。

9. 发明申请

WO2014085683A1 ESTABLISHING A BRANCH TARGET INSTRUCTION CACHE (BTIC) ENTRY FOR SUBROUTINE RETURNS TO REDUCE EXECUTION PIPELINE BUBBLES, AND RELATED SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA 审中-公开
标题翻译：建立分支目标指导缓存（BTIC）进入SUBRONTINE返回以减少执行管道泡沫以及相关系统，方法和计算机可读介质
公开(公告)号：WO2014085683A1
公开(公告)日：2014-06-05
申请号：PCT/US2013/072372
申请日：2013-11-27
申请人： QUALCOMM INCORPORATED
发明人： DIEFFENDERFER, James Norris , MORROW, Michael William , MCILVAINE, Michael Scott , STREETT, Daren Eugene , REDDY, Vimal K. , STEMPEL, Brian Michael
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3808 , G06F9/30054
摘要： Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce pipeline bubbles, and related systems, methods, and computer-readable media are disclosed. In one embodiment, a method of establishing a BTIC entry includes detecting a subroutine call in an execution pipeline. In response, at least one instruction fetched sequential to the subroutine call is written as a branch target instruction in a BTIC entry for a subroutine return. A next instruction fetch address is calculated, and is written into a next instruction fetch address field in the BTIC entry. In this manner, the BTIC may provide correct branch target instruction and next instruction fetch address data for the subroutine return, even if the subroutine return is encountered for the first time or the subroutine is called from different calling locations.
摘要翻译：建立用于子程序的分支目标指令缓存（BTIC）条目返回以减少管道气泡，以及相关系统，方法和计算机可读介质。在一个实施例中，建立BTIC条目的方法包括检测执行流水线中的子程序调用。作为响应，在子程序返回的BTIC条目中写入与子程序调用顺序取得的至少一个指令作为分支目标指令。计算下一个指令提取地址，并将其写入BTIC条目中的下一个指令获取地址字段。以这种方式，即使第一次遇到子程序返回或从不同的呼叫位置调用子程序，BTIC可以为子程序返回提供正确的分支目标指令和下一个指令获取地址数据。

10. 发明申请

WO2013049759A1 PROCESSOR HARDWARE PIPELINE CONFIGURED FOR SINGLE INSTRUCTION ADDRESS EXTRACTION AND MEMORY ACCESS OPERATION 审中-公开
标题翻译：处理器硬件管道配置为单指令地址提取和存储器访问操作
公开(公告)号：WO2013049759A1
公开(公告)日：2013-04-04
申请号：PCT/US2012/058174
申请日：2012-09-30
申请人： QUALCOMM INCORPORATED , DE, Subrato K. , MORROW, Michael William , KHAN, Moinul H. , BAPST, Mark
发明人： DE, Subrato K. , MORROW, Michael William , KHAN, Moinul H. , BAPST, Mark
IPC分类号： G06F9/30
CPC分类号： G06F9/30043
摘要： Memory access instructions, such as load and store instructions, are processed in a processor-based system. Processor hardware pipeline configurations enable efficient performance of memory access instructions, such as a pipeline configuration that enables, for a memory access operation request by a register-operand based virtual machine, computation of the memory location corresponding to a virtual-machine register by extracting a bit-field from the virtual-machine instruction and accessing (load or store) the computed memory location that represents a virtual register of the virtual-machine, in a single pass through the pipeline. Thus this processor hardware pipeline configuration enables a virtual machine register read/write operation to be performed by a single hardware processor instruction through a single pass in the processor hardware pipeline, for a register-operand based virtual machine.
摘要翻译：诸如加载和存储指令之类的存储器访问指令在基于处理器的系统中被处理。处理器硬件流水线配置能够有效地执行存储器访问指令，例如流水线配置，其能够通过基于寄存器操作数的虚拟机对存储器访问操作请求进行与虚拟机寄存器对应的存储器位置的计算，来自虚拟机指令的位字段，并且在通过管道的单次通过中访问（加载或存储）表示虚拟机的虚拟寄存器的计算的存储器位置。因此，这种处理器硬件流水线配置使得能够通过单个硬件处理器指令通过处理器硬件流水线中的单次执行对基于寄存器操作数的虚拟机执行虚拟机寄存器读/写操作。

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