专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2021067331A1 METHOD AND APPARATUS FOR VECTOR SORTING 审中-公开
公开(公告)号：WO2021067331A1
公开(公告)日：2021-04-08
申请号：PCT/US2020/053364
申请日：2020-09-30
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： ANDERSON, Timothy, David , RAMAN, Mujibur
IPC分类号： G06F9/30 , G06F17/16 , G06F7/24 , G06F7/483 , G06F7/487 , G06F7/4876 , G06F7/49915 , G06F7/53 , G06F7/57 , G06F9/3001 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F9/30149 , G06F9/3818 , G06F9/3836 , G06F9/3851 , G06F9/48 , H03H17/06 , H03H17/0664 , H03H2017/0298
摘要： A method for sorting of a vector in a processor is provided that includes performing (5200), by the processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values are sorted in an order indicated by the vector sort instruction, and storing (5202) the sorted vector in a storage location.

2. 发明申请

WO2021041139A1 SIGNED MULTIWORD MULTIPLIER 审中-公开
公开(公告)号：WO2021041139A1
公开(公告)日：2021-03-04
申请号：PCT/US2020/047147
申请日：2020-08-20
申请人： GOOGLE LLC
发明人： POPE, Reiner
IPC分类号： G06F7/53
摘要： Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a hardware circuit configured as a signed multiword multiplier. The circuit includes a processing circuit that receives inputs that each have a respective bit-width. The processing circuit can represent at least one input as a signed multiword input based on the first input having a bit-width that exceeds a fixed bit-width of the hardware circuit. The circuit includes signed multipliers that are each configured to multiply signed inputs. Each signed multiplier includes multiplication circuitry configured to: receive the signed multiword input; receive a signed second input; and generate a signed output in response to multiplying the signed multiword input with the signed second input.

3. 发明申请

WO2020060885A1 DIGITAL CIRCUIT WITH COMPRESSED CARRY 审中-公开
公开(公告)号：WO2020060885A1
公开(公告)日：2020-03-26
申请号：PCT/US2019/051203
申请日：2019-09-14
申请人： GROQ, INC.
发明人： CLARK, Christopher, Aaron , ROSS, Jonathan
IPC分类号： G06F7/53
摘要： Embodiments of the present disclosure pertain to digital circuits with compressed carries. In one embodiment, an adder circuit generates a sum and carry. The carry is compressed to reduce the number of bits required to represent the carry. In one embodiment, a multiplier circuit generates output product values. The output product values may be summed to produce a sum and carry. The carry may be compressed. In other embodiments, a multiplier circuit receives an input sum and compressed carry. The compressed input carry is decompressed and added to output product values and the input sum, and a resulting carry is compressed. The output of such a multiplier is another sum and compressed carry.

4. 发明申请

WO2019125835A1 SYSTEM AND METHOD OF FLOATING POINT MULTIPLY OPERATION PROCESSING 审中-公开
公开(公告)号：WO2019125835A1
公开(公告)日：2019-06-27
申请号：PCT/US2018/065034
申请日：2018-12-11
申请人： QUALCOMM INCORPORATED
发明人： DANYSH, Albert , PLONDKE, Erich , MAHURIN, Eric
IPC分类号： G06F7/523 , G06F7/53
CPC分类号： G06F7/4876 , G06F7/485 , G06F7/523 , G06F7/5324
摘要： A processor includes an integer multiplier configured to execute an integer multiply instruction to multiply significand bits of at least one floating point operand of a floating point multiply operation. The processor also includes a floating point multiplier configured to execute a special purpose floating point multiply accumulate instruction with respect to an intermediate result of the floating point multiply operation and the at least one floating point operand to generate a final floating point multiplication result.

5. 发明申请

WO2015120491A1 COMPUTER PROCESSOR EMPLOYING PHASES OF OPERATIONS CONTAINED IN WIDE INSTRUCTIONS 审中-公开
标题翻译：计算机处理器使用宽泛指令中包含的操作阶段
公开(公告)号：WO2015120491A1
公开(公告)日：2015-08-13
申请号：PCT/US2015/023826
申请日：2015-04-01
申请人： MILL COMPUTING, INC.
发明人： GODARD, Roger Rawson , KAHLICH, Arthur David , YOST, David Arthur , MIROLO, Sebastien Paul Maurice
IPC分类号： G06F7/53 , G06F9/38
CPC分类号： G06F9/3822 , G06F9/30167 , G06F9/3836 , G06F9/3853 , G06F9/3855 , G06F9/3861 , G06F9/3885
摘要： A computer processor employs an instruction processing pipeline that processes a sequence of wide instructions each having an encoding that represents a plurality of different operations. The plurality of different operations of the given wide instruction are logically organized into a number of phases having a predefined ordering such that at least one operation of the given wide instruction produces data that is consumed by at least one other operation of the given wide instruction. In certain circumstances where stalling is absent, the plurality of different operations of the phases of the given wide instruction can be issued for execution by the instruction processing pipeline over a plurality of consecutive machine cycles.
摘要翻译：计算机处理器采用指令处理流水线，其处理每个具有表示多个不同操作的编码的宽指令序列。给定宽指令的多个不同操作被逻辑地组织成具有预定义排序的多个阶段，使得给定宽指令的至少一个操作产生由给定宽指令的至少一个其他操作消耗的数据。在不存在停止的某些情况下，可以通过指令处理流水线在多个连续的机器周期上发出给定的宽指令的相位的多个不同的操作来执行。

6. 发明申请

WO2011124649A1 LOGARITHMIC GAIN ADJUSTER 审中-公开
标题翻译：对数增益调节器
公开(公告)号：WO2011124649A1
公开(公告)日：2011-10-13
申请号：PCT/EP2011/055440
申请日：2011-04-07
申请人： ICERA INC , FELIX, Stephen
发明人： FELIX, Stephen
IPC分类号： G06F7/53
CPC分类号： G06F7/523 , G06F7/53
摘要： A circuit for multiplying a digital signal by a variable gain, controlled in dependence on a digital gain control value. The circuit comprises: a multiplier input for receiving the digital signal; a multiplier output for outputting the digital signal multiplied by the gain; a plurality of multiplier stages each arranged to multiply by a respective predetermined multiplication factor; and switching circuitry arranged so as to apply selected ones of the multiplier stages in a multiplication path between the input and output, in dependence on the digital gain control value. The multiplication factors are arranged such that binary steps in the digital gain control value result in logarithmic steps in said gain.
摘要翻译：用于将数字信号乘以可变增益的电路，其根据数字增益控制值进行控制。该电路包括：用于接收数字信号的乘法器输入; 用于输出乘以增益的数字信号的乘法器输出; 多个乘法器级，每个乘法器级布置成乘以相应的预定乘法因子; 以及开关电路，其被布置为根据数字增益控制值在输入和输出之间的乘法路径中施加选择的乘法器级。乘法因子被布置成使得数字增益控制值中的二进制步长导致所述增益中的对数步长。

7. 发明申请

WO2009063050A1 METHOD AND APPARATUS FOR MULTIPLYING BINARY OPERANDS 审中-公开
标题翻译：用于二进制运算的方法和装置
公开(公告)号：WO2009063050A1
公开(公告)日：2009-05-22
申请号：PCT/EP2008/065554
申请日：2008-11-14
申请人： TEXAS INSTRUMENTS DEUTSCHLAND GMBH , WIENCKE, Christian
发明人： WIENCKE, Christian
IPC分类号： G06F7/53
CPC分类号： G06F7/5306 , G06F2207/3816 , G06F2207/382
摘要： Method and apparatus for multiplying a signed first operand of na bits and a signed second operand of nb bits, wherein na and nb are different positive integer numbers, the method comprising generating single bit products of pairs of a single bit from the signed first operand and a single bit from the signed second operand with a logical AND function to produce na times nb single bit products, selectively inverting for the signed first operand and the signed second operands the single bit products of the first operand bit na-1 multiplied with the second operand bits 0 to nb-2, selectively inverting the single bit products of the signed second operand bits 0 to na-2 multiplied with the signed second operand bit nb-1, after the step of inverting adding the single bit products in accordance with their respective order for producing an intermediate product, and adding a "1" bit value at bit positions nb-1, na-1 and na+nb-1 for receiving a final product.
摘要翻译：用于将n比特的带符号的第一操作数和nb比特的带符号的第二操作数相乘的方法和装置，其中，na和nb是不同的正整数，所述方法包括从签名的第一操作数生成单个比特对的单个比特产物，以及从具有逻辑AND函数的带符号的第二操作数中的单个位产生na次nb单位乘积，对于带符号的第一操作数和带符号的第二操作数有选择地反相，第一操作数位na-1的单位乘积与第二操作数乘以第二操作数操作数位0到nb-2，在反转步骤之后，选择性地将符号的第二操作数位0到na-2的单位乘积与符号的第二操作数位nb-1相乘，根据它们产生中间产品的相应顺序，以及在用于接收最终产品的位位置nb-1，na-1和na + nb-1处添加“1”比特值。

8. 发明申请

WO2004051456A2 MULTIPLIER WITH LOOK UP TABLES 审中-公开
标题翻译：具有查看表的乘法器
公开(公告)号：WO2004051456A2
公开(公告)日：2004-06-17
申请号：PCT/IB0305095
申请日：2003-11-11
申请人： KONINKL PHILIPS ELECTRONICS NV , HUBERT GERARDUS T M
发明人： HUBERT GERARDUS T M
IPC分类号： G06F7/52 , G06F7/53 , G06F7/00
CPC分类号： G06F7/5334 , G06F7/49931 , G06F7/5318
摘要： A method of performing modular multiplication of integers X and Y to produce a result R, where R = X.Y mod N, in a multiplication engine. X is fragmented into a first plurality of words xn each having a first predetermined number of bits, k and Y is fragmented into a second plurality of words yn each having a second predetermined number of bits, m. Multiples of a word xn of X are derived in a pre-calculation circuit and subsequently used to derive products of the word xn of X with each of the plurality of words yn of Y. An intermediate result Rj is calculated as a cumulating sum derived from said pre-calculated multiples and the steps repeated for each successive word of X so as to generate successive intermediate results, Rj, for each of the first plurality of words xn. The final result, R is obtained from the last of the intermediate results Rn-1.
摘要翻译：执行整数X和Y的模数乘法以在乘法引擎中产生结果R（其中R = X.Y mod N）的方法。 X被分割成具有第一预定位数的第一多个单词xn，k和Y被分段成每个具有第二预定位数m的第二多个单词yn。 X的单词xn的倍数在预计算电路中导出，随后用于以Y的多个单词yn中的每一个Yn得出X的单词xn的乘积。中间结果Rj被计算为从对于X的每个连续字重复所述预先计算的倍数和步骤，以便为第一多个单词xn中的每一个生成连续的中间结果R j。最后的结果是从最后一个中间结果Rn-1得到R。

9. 发明申请

WO00033174A1 DIGITAL VALUE PROCESSOR 审中-公开
标题翻译：数字处理器
公开(公告)号：WO00033174A1
公开(公告)日：2000-06-08
申请号：PCT/EP1999/008407
申请日：1999-11-03
IPC分类号： G06F7/53 , G06F7/38 , G06F7/523 , G06F7/552 , H04J13/00
CPC分类号： G06F7/552 , G06F2207/5523
摘要： The present application relates to a device and method for processing a digital value to thereby determine an estimate of the square of said digital value. This is done by linearly approximating the square function with the help of anchor points that are powers of 2, such that the estimate of the square of a digital value xa is determined on the basis of a first processing value 2 , where 2 , and a second processing value (3xa - 2 ). The present invention is advantageous in that it allows simple processing steps and a simple processing hardware. It is preferably applied to the mean signal power estimation of a digital signal being sent to a transmitter.
摘要翻译：本申请涉及一种用于处理数字值从而确定所述数字值的平方的估计的装置和方法。这通过使用功率为2的锚点的线性逼近平方函数来完成，使得基于第一处理值2确定数字值xa的平方的估计，其中2 和第二处理值（3xa-2i + 1）。本发明的优点在于它允许简单的处理步骤和简单的处理硬件。优选地应用于发送到发射机的数字信号的平均信号功率估计。

10. 发明申请

WO9308523A3 1-BIT ADDER AND MULTIPLIER CONTAINING A 1-BIT ADDER 审中-公开
标题翻译：包含1位加法器的1位加法器和乘法器
公开(公告)号：WO9308523A3
公开(公告)日：1993-05-27
申请号：PCT/EP9202350
申请日：1992-10-12
申请人： THOMSON CONSUMER ELECTRONICS
发明人： CHAN YAN FONG JOSEPH
IPC分类号： G06F7/507 , G06F7/50 , G06F7/52 , G06F7/527 , G06F7/53 , G06F7/533 , H03K19/0944
CPC分类号： G06F7/5338 , G06F7/501 , G06F7/507 , G06F2207/3884 , G06F2207/4812 , G06F2207/4816 , H03K19/09448
摘要： E.g. for video applications fast multipliers with high resolution are required. But a higher resolution results in more partial products to be calculated internally. The Booth-Mc Sorley algorithm can be used in order to reduce the required number of such partial products. This algorithm can be combined with a diagonal propagation of the carry from one partial product to the other, allowing all the sums on a line to be calculated simultaneously. But the reachable multiplication time is not short enough. The inventive multiplier in nearly full CMOS design has been constructed with a 1.2 ν BICMOS technology, having a multiplication time of 9 ns with a supply voltage of 5 volts. Minimum multiplication time has been achieved by a combination of the following techniques: use of the Booth-Mc Sorley algorithm in order to reduce the number of partial products; diagonal propagation of the carry from one partial product to the other allowing all the sums on one line to be done simultaneously; use of the carry select approach in the final 14 bits adder and in the first two adders in the intermediate rows; use of inventive fast one-bit full adders with complementary pass transistor logic.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式