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1. 发明申请

WO2009140299A3 SELF-STABILIZING SENSOR CIRCUIT FOR RESISTIVE MEMORIES 审中-公开
标题翻译：用于电阻记忆体的自稳定传感器电路
公开(公告)号：WO2009140299A3
公开(公告)日：2010-01-28
申请号：PCT/US2009043661
申请日：2009-05-12
申请人： SYMETRIX CORP , CELINSKA JOLANTA , PAZ DE ARAUJO CARLOS A , MCWILLIAMS CHRISTOPHER RANDOLP
发明人： CELINSKA JOLANTA , PAZ DE ARAUJO CARLOS A , MCWILLIAMS CHRISTOPHER RANDOLPH
IPC分类号： G11C13/00
CPC分类号： G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0078 , G11C2213/32
摘要： An integrated circuit resistance memory comprising: a memory cell comprising a variable resistance element capable of having a low resistance state and a high resistance state; a sensing circuit for sensing the resistance of the variable resistance element, the sensing circuit comprising a Wheatstone bridge circuit; and wherein the variable resistance element in the memory cell is electrically connectable to provide at least a portion of the resistance in one leg of the Wheatstone bridge circuit.
摘要翻译：一种集成电路电阻存储器，包括：存储单元，包括能够具有低电阻状态和高电阻状态的可变电阻元件; 感测电路，用于感测可变电阻元件的电阻，感测电路包括惠斯通电桥电路; 并且其中所述存储单元中的所述可变电阻元件可电连接以提供所述惠斯通电桥电路的一条支路中的至少一部分电阻。

2. 发明申请

WO2009135079A3 FERROELECTRIC INFRARED SENSOR AND INTEGRATOR 审中-公开
标题翻译：铁电红外传感器和积分器
公开(公告)号：WO2009135079A3
公开(公告)日：2009-12-23
申请号：PCT/US2009042432
申请日：2009-04-30
申请人： SYMETRIX CORP , CELINSKA JOLANTA , PAZ DE ARAUJO CARLOS A , UNGLAUB RICARDO
发明人： CELINSKA JOLANTA , PAZ DE ARAUJO CARLOS A , UNGLAUB RICARDO
IPC分类号： G01J5/34 , G01J5/52
CPC分类号： G01J5/34 , G01J5/02 , G01J5/024 , G01J5/52 , G01J2005/068 , H01L28/55
摘要： An infrared sensor includes a first ferroelectric capacitor, oriented such that the first ferroelectric capacitor is not exposed to radiation to be measured; a second ferroelectric capacitor, the second ferroelectric capacitor comprising a silicon substrate, an insulating layer, and a ferroelectric element; a subtractor that receives electric signals from both the first and second ferroelectric capacitor and finds a difference; and an integrator that receives electric signals from the subtractor and integrates the electric signals from the subtractor.
摘要翻译：一种红外传感器包括第一铁电电容器，其定向为使得第一铁电电容器不暴露于待测辐射; 一个第二铁电电容器，该第二铁电电容器包括一个硅衬底，一个绝缘层和一个铁电元件; 减法器，接收来自第一和第二铁电电容器的电信号并找出差值; 以及从减法器接收电信号并且积分来自减法器的电信号的积分器。

3. 发明申请

WO2008058264A3 CORRELATED ELECTRON MEMORY 审中-公开
标题翻译：相关电子存储器
公开(公告)号：WO2008058264A3
公开(公告)日：2008-09-04
申请号：PCT/US2007084183
申请日：2007-11-08
申请人： SYMETRIX CORP , PAZ DE ARAUJO CARLOS A , BRUBAKER MATTHEW D , CELINSKA JOLANTA
发明人： PAZ DE ARAUJO CARLOS A , BRUBAKER MATTHEW D , CELINSKA JOLANTA
IPC分类号： H01L27/10
CPC分类号： H01L27/101 , G11C13/003 , G11C2213/53 , G11C2213/75 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L45/04 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A non-volatile resistive switching memory that includes a material which changes between the insulative and conductive states due to correlations between electrons, particularly via a Mott transition. The material is crystallized into the conductive state and does not require electroforming.
摘要翻译：一种非易失性电阻切换存储器，其包括由于电子之间的相关性而在绝缘状态和导电状态之间变化的材料，特别是通过Mott转变。材料结晶成导电状态，不需要电铸。

4. 发明申请

WO2004076991A3 PYROELECTRIC SENSOR 审中-公开
标题翻译：光电传感器
公开(公告)号：WO2004076991A3
公开(公告)日：2005-05-12
申请号：PCT/US2004005100
申请日：2004-02-20
申请人： DELPHI TECH INC , SYMETRIX CORP , MANTESE JOSEPH V , SCHUBRING NORMAN W , MICHELI ADOLPH L , PAZ DE ARAUJO CARLOS A , MCMILLAN LARRY D , CELINSKA JOLANTA
发明人： MANTESE JOSEPH V , SCHUBRING NORMAN W , MICHELI ADOLPH L , PAZ DE ARAUJO CARLOS A , MCMILLAN LARRY D , CELINSKA JOLANTA
IPC分类号： G01J5/34 , G01J5/10
CPC分类号： G01J5/34
摘要： A ferroelectric/pyroelectric sensor employs a technique for determining a charge output of a ferroelectric scene element (134) of the sensor by measuring the hysteresis loop output of the scene element (134) several times during a particular time frame for the same temperature. An external AC signal is applied to the ferroelectric scene element (134) to cause the hysteresis loop output from the element (134) to switch polarization. Charge integration circuitry (138), such as a combination output capacitor and operational amplifier, is employed to measure the charge from the scene element (134). Preferably, the ferroelectric of the scene element (134) is made of SBT or derivative thereof, disposed directly between the top and bottom electrodes. Because of the frequency characteristics of the sensor, created by the external AC signal, the element (134) need not be thermally isolated from the silicon substrate by a traditional air bridge, and instead is preferably thermally isolated by spin-on-glass, SOG. To prevent saturation of an output signal voltage of the sensor by excessive charge accumulation in an output capacitor, the sensor has a reference element (132) in parallel with the scene element (134). When the voltage of the AC signal is negative the output capacitor is discharged by flowing current through the reference element (132) thus interrogating the polarization of the reference element (132) which is compared to and subtracted from the polarization of the scene element (134) for each cycle. The polarization difference measured for each cycle over a set time period are summed by an integrating amplifier to produce a signal output.
摘要翻译：铁电/热电传感器采用用于通过在相同温度的特定时间范围内测量场景元件（134）的多次磁滞回线输出来确定传感器的铁电场景元件（134）的电荷输出的技术。将外部AC信号施加到铁电场景元件（134）以使得从元件（134）输出的磁滞回线切换偏振。采用诸如组合输出电容器和运算放大器的电荷积分电路（138）来测量来自场景元件（134）的电荷。优选地，场景元件（134）的铁电体由直接设置在顶部和底部电极之间的SBT或其衍生物制成。由于由外部AC信号产生的传感器的频率特性，元件（134）不需要通过传统的空气桥与硅衬底热隔离，而是优选通过旋涂玻璃SOG热隔离。为了通过输出电容器中的过度电荷积累来防止传感器的输出信号电压的饱和，传感器具有与场景元件（134）并联的参考元件（132）。当AC信号的电压为负时，输出电容器通过流过参考元件（132）的电流而被放电，从而询问与场景元件（134）的极化相比较和减去的参考元件（132）的极化）。通过积分放大器对设定时间段内的每个周期测量的偏振差进行求和以产生信号输出。

5. 发明申请

WO0225667A2 FERROELECTRIC MEMORY AND METHOD OF OPERATING SAME 审中-公开
标题翻译：铁电存储器及其操作方法
公开(公告)号：WO0225667A2
公开(公告)日：2002-03-28
申请号：PCT/US0142288
申请日：2001-09-25
申请人： SYMETRIX CORP , MATSUSHITA ELECTRIC IND CO LTD , CHEN ZHENG , KATO YOSHIHISA , JOSHI VIKRAM , LIM MYOUNGHO , PAZ DE ARAUJO CARLOS A , MCMILLAN LARRY D , SHIMADA YASUHIRO , OTSUKI TATSUO
发明人： CHEN ZHENG , KATO YOSHIHISA , JOSHI VIKRAM , LIM MYOUNGHO , PAZ DE ARAUJO CARLOS A , MCMILLAN LARRY D , SHIMADA YASUHIRO , OTSUKI TATSUO
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric memory 636 includes a group of memory cells (645, 12, 201, 301, 401, 501), each cell having a ferroelectric memory element (44, 218, etc.), a drive line (122, 322, 422, 522 etc.) on which a voltage for writing information to the group of memory cells is placed, a bit line (25, 49, 125, 325, 425, 525, etc.) on which information to be read out of the group of memory cells is placed, a preamplifier (20, 42, 120, 320, 420, etc.) between the memory cells and the bit line, a set switch (14, 114, 314, 414, 514, etc.) connected between the drive line and the memory cells, and a reset switch (16, 116, 316, 416, 516, etc.) connected to the memory cells in parallel with the preamplifier. The memory is read by placing a voltage less than the coercive voltage of the ferroelectric memory element across a memory element. Prior to reading, noise from the group of cells is discharged by grounding both electrodes of the ferroelectric memory element.
摘要翻译：铁电存储器636包括一组存储单元（645,12,201,301,401,501），每个单元具有铁电存储元件（44,218等），驱动线（122,322,422等） 522等），在其上放置用于向该组存储器单元写入信息的电压;位线（25,49,125,325,425,525等），在该位线上将要从其中读出信息存储器单元被放置在存储器单元与位线之间的前置放大器（20,42,120,320,420等），连接在存储器单元与位线之间的置位开关（14,114,314,414,514等）驱动线和存储器单元，以及与前置放大器并联连接到存储器单元的复位开关（16,116,316,416,516等）。通过在存储元件上放置比铁电存储元件的矫顽电压小的电压来读取存储器。在读取之前，通过使铁电存储器元件的两个电极接地来放电来自电池组的噪声。

6. 发明申请

WO2004066307A3 STACKED MEMORY CELL HAVING DIFFUSION BARRIERS 审中-公开
标题翻译：具有扩展障碍的堆叠存储单元
公开(公告)号：WO2004066307A3
公开(公告)日：2004-09-23
申请号：PCT/US2004001391
申请日：2004-01-20
申请人： SYMETRIX CORP
发明人： JOSHI VIKRAM , SOLAYAPPAN NARAYAN , PAZ DE ARAUJO CARLOS A , MCMILLAN LARRY D
IPC分类号： C30B29/32 , C30B29/68 , G11C20060101 , H01L21/02 , H01L21/314 , H01L21/8246 , H01L23/64 , H01L27/115
CPC分类号： H01L27/11502 , C30B29/32 , C30B29/68 , H01L23/642 , H01L27/11507 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： A bottom electrode (238) and portion of an insulator layer (224) adjacent to the bottom electrode of a memory capacitor (540) are removed by etching to form sidewall (440) and a moat region (450) in the insulator. A nonconductive oxygen barrier layer (460) is deposited to cover the sidewall and bottom of the moat. The nonconductive oxygen barrier layer and a conductive diffusion barrier (444, 236) beneath the capacitor together provide a substantially continuous diffusion barrier between the capacitor and a switch (208). A nonconductive hydrogen barrier layer (508), the nonconductive oxygen barrier, and the conductive diffusion barrier substantially completely envelop the capacitor, in particular a ferroelectric thin film (490) in the capacitor.
摘要翻译：通过蚀刻去除底部电极（238）和与存储电容器（540）的底部电极相邻的绝缘体层（224）的部分，以在绝缘体中形成侧壁（440）和护环区域（450）。沉积非导电氧阻挡层（460）以覆盖护城河的侧壁和底部。电容器下方的非导电氧阻挡层和导电扩散阻挡层（444,236）一起在电容器和开关（208）之间提供基本上连续的扩散阻挡层。不导电氢阻挡层（508），非导电氧阻挡层和导电扩散阻挡层基本上完全包围电容器，特别是电容器中的铁电薄膜（490）。

7. 发明申请

WO0166834A3 CHEMICAL VAPOR DEPOSITION PROCESS FOR FABRICATING LAYERED SUPERLATTICE MATERIALS 审中-公开
标题翻译：用于制备层状超导材料的化学气相沉积工艺
公开(公告)号：WO0166834A3
公开(公告)日：2002-02-28
申请号：PCT/US0105572
申请日：2001-02-21
申请人： SYMETRIX CORP , MATSUSHITA ELECTRIC IND CO LTD
发明人： UCHIYAMA KIYOSHI , SOLAYAPPAN NARAYAN , PAZ DE ARAUJO CARLOS A
IPC分类号： C23C16/455 , C23C16/02 , C23C16/40 , C23C16/44 , H01L21/316 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L29/788 , H01L29/792 , C30B29/68 , C23C16/46 , C30B29/30 , H01L21/02 , H01L27/112 , H01L27/115
CPC分类号： C23C16/45561 , C23C16/0272 , C23C16/40 , C23C16/44 , Y10S438/935 , Y10S438/938
摘要： A first reactant gas is flowed (310) into a CVD reaction chamber (430) containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompose in the CVD reaction chamber to deposit a coating containing metal atoms on the heated integrated circuit substrate. The coating is treated (312) by RTP. Thereafter, a second reactant gas is flowed (316) into a CVD reaction chamber (430) containing the heated substrate. The second reactant gas contains a second precursor compound or a plurality of second precursor compounds, which decompose in the CVD reaction chamber to deposit more metal atoms on the substrate. Heat for reaction and crystallization of the deposited metal atoms to form a thin film (124, 226, 528, 758, 728) of layered superlattice material is provided by heating the substrate during CVD deposition, as well as by selected rapid thermal processing ("RTP") and furnace annealing steps.
摘要翻译：将第一反应气体（310）流入包含加热的集成电路基板的CVD反应室（430）中。第一反应气体含有第一前体化合物或多个第一前体化合物，第一前体化合物或化合物在CVD反应室中分解，以在被加热的集成电路衬底上沉积含有金属原子的涂层。通过RTP处理（312）涂层。此后，将第二反应气体（316）流入含有加热衬底的CVD反应室（430）中。第二反应气体含有第二前体化合物或多个第二前体化合物，其在CVD反应室中分解以在基底上沉积更多的金属原子。通过在CVD沉积期间加热衬底以及通过选择的快速热处理（“226”，“528,758,728”）的沉积金属原子反应和结晶以形成层状超晶格材料的薄膜（124,226,528,758,728） RTP“）和炉退火步骤。

8. 发明申请

WO0109930A3 THIN FILM CAPACITORS ON SILICON GERMANIUM SUBSTRATE AND PROCESS FOR MAKING THE SAME 审中-公开
标题翻译：硅锗基片上的薄膜电容器及其制造方法
公开(公告)号：WO0109930A3
公开(公告)日：2001-07-05
申请号：PCT/US0040344
申请日：2000-07-11
申请人： SYMETRIX CORP , MATSUSHITA ELECTRONICS CORP
发明人： MCMILLAN LARRY D , PAZ DE ARAUJO CARLOS A , ARITA KOJI , AZUMA MASAMICHI
IPC分类号： H01L21/02 , H01L21/82 , H01L29/12 , H01L29/92
CPC分类号： C23C18/1216 , C23C18/1245 , C23C18/1279 , C23C18/1283 , H01L28/55 , H01L28/60 , H01L28/75
摘要： An integrated circuit capacitor (10, 25, 30, 402) containing a thin film of dielectric metaloxide (20, 420) is formed above a silicon germanium substrate (12, 406). A silicon nitride diffusion barrier layer (24, 324, 414) is deposited on a silicon germanium substrate to prevent evaporation of the substrate in subsequent heating steps. A silicon dioxide stress reduction layer is deposited on the diffusion barrier layer. A bottom electrode (16, 418) is formed on the stress reduction layer, then a liquid precursor is spun on the bottom electrode, dried at about 400 DEG C, and annealed at between 600 DEG C and 850 DEG C to form a BST capacitor dielectric (20, 420). A top electrode (22, 422) is deposited on the dielectric and annealed. The integrated circuit may also include a BiCMOS device, a HBT device or a MOSFET.
摘要翻译：在硅锗基板（12,406）的上方形成包含介电金属氧化物（20,420）的薄膜的集成电路电容器（10,25,30,402）。氮化硅扩散阻挡层（24,324,414）沉积在硅锗衬底上以防止随后的加热步骤中衬底的蒸发。二氧化硅应力降低层沉积在扩散阻挡层上。在应力降低层上形成底部电极（16,418），然后在底部电极上旋转液体前体，在约400℃下干燥，并在600℃和850℃之间退火以形成BST电容器电介质（20,420）。顶部电极（22,422）沉积在电介质上并退火。集成电路还可以包括BiCMOS器件，HBT器件或MOSFET。

9. 发明申请

WO9630938A3 PROCESS FOR FABRICATING LAYERED SUPERLATTICE MATERIALS AND MAKING ELECTRONIC DEVICES INCLUDING SAME 审中-公开
标题翻译：用于制备层状超导材料并制造包括其的电子器件的方法
公开(公告)号：WO9630938A3
公开(公告)日：1996-12-05
申请号：PCT/US9603367
申请日：1996-03-12
申请人： SYMETRIX CORP , OLYMPUS OPTICAL CO
发明人： YOSHIMORI HIROYUKI , PAZ DE ARAUJO CARLOS A , ITO TAKESHI , SCOTT MICHAEL C , MCMILLAN LARRY D
IPC分类号： H01L21/8247 , B05D1/00 , B05D3/04 , B05D7/24 , C23C16/44 , C23C16/448 , C23C16/455 , C23C16/46 , C23C16/48 , C23C16/52 , C23C18/12 , C23C26/02 , C30B7/00 , H01C7/10 , H01L21/02 , H01L21/314 , H01L21/316 , H01L21/8242 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792 , H01L41/24 , H05K3/10 , H01L21/3205
CPC分类号： C23C18/1216 , B05D1/00 , B05D1/60 , B05D3/0493 , C23C16/4412 , C23C16/4486 , C23C16/45561 , C23C16/4558 , C23C16/46 , C23C16/482 , C23C16/52 , C23C18/1279 , C23C18/1283 , C23C18/1295 , C23C26/02 , C30B7/00 , C30B7/005 , C30B29/68 , H01C7/1013 , H01L21/314 , H01L21/31691 , H01L27/10805 , H01L27/11502 , H01L28/55 , H01L28/56 , H01L28/60 , H01L41/257 , H01L41/318 , H05K3/105
摘要： A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Special polyoxyalkylated precursor solutions are designed to optimize polarizability of the corresponding metal oxide materials by adding dopants including stoichiometric excess amounts of bismuth and tantalum. The RTP baking process is especially beneficial in optimizing the polarizability of the resultant metal oxide.

10. 发明申请

WO2004049441A3 LOW THERMAL BUDGET FABRICATION OF FERROELECTRIC MEMORY USING RTP 审中-公开
标题翻译：使用RTP的电热记忆的低热预算制造
公开(公告)号：WO2004049441A3
公开(公告)日：2004-09-02
申请号：PCT/US0337501
申请日：2003-11-20
申请人： SYMETRIX CORP
发明人： CELINSKA JOLANTA , JOSHI VIKRAM , SOLAYAPPAN NARAYAN , LIM MYOUNGHO , MCMILLAN LARRY D , PAZ DE ARAUJO CARLOS A
IPC分类号： C30B29/32 , C30B29/68 , H01L21/02 , H01L21/314 , H01L21/316 , H01L27/115 , H01L29/78
CPC分类号： H01L28/55 , C30B29/32 , C30B29/68
摘要： A layered superlattice material precursor is applied to a substrate (102). The precursor coating is rapid thermal processed (RTP) with a ramping rate of 100 °C/second at a hold temperature in a range of from 500 °C to 900 °C for a cumulative heating time not exceeding 30 minutes, and preferably less than 5 minutes. In fabricating a ferroelectric memory cell (100), the coating is heated in oxygen using RTP, then a top electrode layer (128) is formed, and then the substrate including the coating is heated using RTP in oxygen or in nonreactive gas after forming the top electrode layer. The thin film (126) preferably has a thickness in a range of from 25 nm to 120 nm. The process typically has a thermal budget value not exceeding 960,000 °C-sec, preferably less than 50,000 °C-sec.
摘要翻译：将层状超晶格材料前体施加到基底（102）上。前体涂层是在500℃至900℃范围内的保持温度下以100℃/秒的升高速率进行快速热处理（RTP），累积加热时间不超过30分钟，优选小于 5分钟。在制造铁电存储单元（100）时，使用RTP在氧气中加热涂层，然后形成顶部电极层（128），然后使用RTP在氧气中或在非反应性气体中形成包含涂层的基板，形成顶部电极层。薄膜（126）优选具有在25nm至120nm范围内的厚度。该方法通常具有不超过960,000℃-sec，优选小于50,000℃-sec的热预算值。

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