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1. 发明申请

WO0166834A3 CHEMICAL VAPOR DEPOSITION PROCESS FOR FABRICATING LAYERED SUPERLATTICE MATERIALS 审中-公开
标题翻译：用于制备层状超导材料的化学气相沉积工艺
公开(公告)号：WO0166834A3
公开(公告)日：2002-02-28
申请号：PCT/US0105572
申请日：2001-02-21
申请人： SYMETRIX CORP , MATSUSHITA ELECTRIC IND CO LTD
发明人： UCHIYAMA KIYOSHI , SOLAYAPPAN NARAYAN , PAZ DE ARAUJO CARLOS A
IPC分类号： C23C16/455 , C23C16/02 , C23C16/40 , C23C16/44 , H01L21/316 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L29/788 , H01L29/792 , C30B29/68 , C23C16/46 , C30B29/30 , H01L21/02 , H01L27/112 , H01L27/115
CPC分类号： C23C16/45561 , C23C16/0272 , C23C16/40 , C23C16/44 , Y10S438/935 , Y10S438/938
摘要： A first reactant gas is flowed (310) into a CVD reaction chamber (430) containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompose in the CVD reaction chamber to deposit a coating containing metal atoms on the heated integrated circuit substrate. The coating is treated (312) by RTP. Thereafter, a second reactant gas is flowed (316) into a CVD reaction chamber (430) containing the heated substrate. The second reactant gas contains a second precursor compound or a plurality of second precursor compounds, which decompose in the CVD reaction chamber to deposit more metal atoms on the substrate. Heat for reaction and crystallization of the deposited metal atoms to form a thin film (124, 226, 528, 758, 728) of layered superlattice material is provided by heating the substrate during CVD deposition, as well as by selected rapid thermal processing ("RTP") and furnace annealing steps.
摘要翻译：将第一反应气体（310）流入包含加热的集成电路基板的CVD反应室（430）中。第一反应气体含有第一前体化合物或多个第一前体化合物，第一前体化合物或化合物在CVD反应室中分解，以在被加热的集成电路衬底上沉积含有金属原子的涂层。通过RTP处理（312）涂层。此后，将第二反应气体（316）流入含有加热衬底的CVD反应室（430）中。第二反应气体含有第二前体化合物或多个第二前体化合物，其在CVD反应室中分解以在基底上沉积更多的金属原子。通过在CVD沉积期间加热衬底以及通过选择的快速热处理（“226”，“528,758,728”）的沉积金属原子反应和结晶以形成层状超晶格材料的薄膜（124,226,528,758,728） RTP“）和炉退火步骤。

2. 发明申请

WO02065536A3 RAPID-TEMPERATURE PULSING ANNEAL METHOD AT LOW TEMPERATURE FOR FABRICATING LAYERED SUPERLATTICE MATERIALS AND MAKING ELECTRONIC DEVICES INCLUDING SAME 审中-公开
标题翻译：用于制备层状超薄材料的低温快速压制方法和制造包括其的电子器件
公开(公告)号：WO02065536A3
公开(公告)日：2003-03-06
申请号：PCT/US0145240
申请日：2001-11-29
申请人： SYMETRIX CORP , MATSUSHITA ELECTRIC IND CO LTD
发明人： UCHIYAMA KIYOSHI , PAZ DE ARAUJO CARLOS A , TANAKA KEISUKE
IPC分类号： C23C18/12 , C30B33/00 , H01L21/28 , H01L21/314 , H01L21/316 , H01L29/78
CPC分类号： C23C18/1216 , C23C18/1225 , C23C18/1279 , C23C18/1283 , C30B29/68 , C30B33/00 , H01L21/02197 , H01L21/02282 , H01L21/28291 , H01L21/31691 , H01L29/78391
摘要： A liquid precursor for forming a layered superlattice material (124, 226, 610) is applied (324) to an integrated circuit substrate. The precursor coating is annealed in oxygen using a rapid-temperature pulsing anneal ("RPA") technique with a ramp rate of 30 DEG C/second at a hold temperature of 650 DEG C for a holding time of 30 minutes. The RPA technique includes applying a plurality (330, 340) of rapid-temperature heat pulses in sequence.
摘要翻译：用于形成层状超晶格材料（124,226,610）的液体前体（324）施加到集成电路基板上。使用快速温度脉冲退火（“RPA”）技术在650℃的保持温度下以30℃/秒的升温速率在氧气中退火前体涂层，保持时间为30分钟。 RPA技术包括依次应用多个（330,340）的快速热脉冲。

3. 发明申请

WO03005433A3 INTEGRATED CIRCUIT DEVICE INCLUDING A LAYERED SUPERLATTICE MATERIAL WITH AN INTERFACE BUFFER LAYER 审中-公开
标题翻译：集成电路器件，包括带有接口缓冲层的分层超级材料
公开(公告)号：WO03005433A3
公开(公告)日：2003-05-30
申请号：PCT/JP0206705
申请日：2002-07-02
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： UCHIYAMA KIYOSHI
IPC分类号： H01L21/02 , H01L21/316 , H01L21/8246 , H01L27/105
CPC分类号： H01L28/56 , H01L21/31691
摘要： An integrated circuit memory device (100, 200, 300) includes a thin film layered superlattice material layer (115) and an electrode (105 or 145). An interface buffer layer (120 or 205) is formed between said thin film layered superlattice material layer and said electrode. The interface buffer layer is selected from the group consisting of: 1) simple oxides, not including bismuth, of an A-site or a B-site metal; and 2) second layered superlattice materials different from the first layered superlattice material and containing at least one A-site or B-site metal that is the same as an A-site or B-site metal in the first layered superlattice material. The oxide not including bismuth can be a complex oxide including a plurality of metals or a simple oxide including only one metal. Most preferably, the interface buffer layer is selected from the group consisting of strontium tantalate, bismuth tantalate, strontium niobium tantalate, strontium bismuth tantalate niobate, titanium oxide, and tantalum pentoxide, other simple oxides of A-site and B-site metals, and other simple oxides of one or more A-site or B-site metals.
摘要翻译：集成电路存储器件（100,200,300）包括薄膜层状超晶格材料层（115）和电极（105或145）。界面缓冲层（120或205）形成在所述薄膜层状超晶格材料层和所述电极之间。界面缓冲层选自：1）A位或B位金属的简单氧化物，不包括铋; 和2）不同于第一层状超晶格材料且在第一层状超晶格材料中含有与A位或B位金属相同的至少一种A位或B位金属的第二层状超晶格材料。不含铋的氧化物可以是包含多种金属的复合氧化物或仅包含一种金属的简单氧化物。最优选地，接口缓冲层选自锶，钽，钽酸铋，锶铌，钽组成的组中，钽酸铋锶A位和B位的金属的铌酸，二氧化钛，和五氧化二钽，其他简单的氧化物，以及其他一种或多种A位或B位金属的简单氧化物。

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