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1. 发明申请

WO2005089407A3 DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS 审中-公开
标题翻译：用于通信信道的移动跟踪反馈
公开(公告)号：WO2005089407A3
公开(公告)日：2005-12-22
申请号：PCT/US2005008830
申请日：2005-03-16
申请人： RAMBUS INC , BEST SCOTT C , ABHYANKAR ABHIJIT M , CHANG KUN-YUNG , LAMBRECHT FRANK
发明人： BEST SCOTT C , ABHYANKAR ABHIJIT M , CHANG KUN-YUNG , LAMBRECHT FRANK
IPC分类号： G06F1/04 , H04L7/00 , H04L7/10 , H04L25/14
CPC分类号： G06F1/08 , G06F1/12 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50012 , H04L7/0004 , H04L7/0008 , H04L7/0033 , H04L7/0091 , H04L7/033 , H04L7/10 , H04L25/14
摘要： A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.
摘要翻译：通信信道包括具有耦合到正常信号源的发射器的第一组件和具有耦合到正常信号目的地的接收器的第二组件。通信链路耦合第一和第二组件。校准逻辑规定为通信信道的参数设置操作值，例如通过在链路初始化时执行穷举校准序列。包括监测功能的跟踪电路通过监测具有与通信信道中的漂移相关的特性的反馈信号来跟踪参数中的漂移，并且更新或指示需要更新参数的操作值响应监测功能。

2. 发明申请

WO2011106055A4 COORDINATING MEMORY OPERATIONS USING MEMORY-DEVICE GENERATED REFERENCE SIGNALS 审中-公开
标题翻译：使用存储器设备生成的参考信号协调存储器操作
公开(公告)号：WO2011106055A4
公开(公告)日：2011-11-03
申请号：PCT/US2010058542
申请日：2010-12-01
申请人： RAMBUS INC , BEST SCOTT C , SHAEFFER IAN
发明人： BEST SCOTT C , SHAEFFER IAN
IPC分类号： G06F13/16 , G06F13/38
CPC分类号： G06F13/1689 , G06F3/061 , G06F3/0659 , G06F3/0683 , G11C11/4076 , G11C11/409 , G11C11/4093 , Y02B60/1228 , Y02D10/14
摘要： A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.
摘要翻译：存储器系统包括耦合到多个存储器设备的存储器控制器。每个存储器设备包括振荡器，该振荡器生成内部参考信号，该内部参考信号以作为存储器设备内的物理设备结构的函数的频率振荡。内部参考信号的频率因此是设备特定的。每个存储器设备从其内部参考信号产生共享参考信号并将共享参考信号传送到公共存储器控制器。存储器控制器使用共享参考信号从每个存储器设备恢复设备特定的频率信息，然后以与相应的内部参考信号兼容的频率与每个存储器设备通信。

3. 发明申请

WO2012145117A3 MEMORY COMPONENTS AND CONTROLLERS THAT CALIBRATE MULTIPHASE SYNCHRONOUS TIMING REFERENCES 审中-公开
标题翻译：存储器组件和控制器，用于校准多个同步时序参考
公开(公告)号：WO2012145117A3
公开(公告)日：2013-01-17
申请号：PCT/US2012029893
申请日：2012-03-21
申请人： RAMBUS INC , GIOVANNINI THOMAS J , BEST SCOTT C , LUO LEI , SHAEFFER IAN
发明人： GIOVANNINI THOMAS J , BEST SCOTT C , LUO LEI , SHAEFFER IAN
IPC分类号： G11C7/22 , G11C7/10
CPC分类号： G11C7/222 , G11C7/227 , G11C29/023 , G11C29/028 , G11C29/50012 , G11C29/56
摘要： A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.
摘要翻译：第一定时参考信号和第二定时参考信号被发送到存储器件。第二定时参考信号相对于第一定时参考信号具有近似的正交相位关系。从存储装置接收多个串行数据模式。第一定时参考和第二定时参考的转换确定何时在多个数据模式的位之间发生转换。当从存储器装置接收到多个数据模式的位之间发生接收转换时相关联的定时指示符。时间指示器均使用单个采样器进行测量。基于定时指示器，确定并应用第一定时参考信号的第一占空比调整，第二定时参考信号的第二占空比调整和正交相位调整。

4. 发明申请

WO2010138480A3 STACKED SEMICONDUCTOR DEVICE ASSEMBLY 审中-公开
标题翻译：堆叠半导体器件组件
公开(公告)号：WO2010138480A3
公开(公告)日：2011-01-20
申请号：PCT/US2010036020
申请日：2010-05-25
申请人： RAMBUS INC , BEST SCOTT C
发明人： BEST SCOTT C
IPC分类号： H01L23/60 , H01L23/48 , H01L25/065
CPC分类号： G06F13/362 , G06F13/4068 , G11C11/408 , G11C11/409 , G11C11/4096 , G11C14/0018 , G11C16/10 , G11C16/26 , H01L23/48 , H01L23/481 , H01L23/50 , H01L23/60 , H01L24/09 , H01L25/0652 , H01L25/0657 , H01L27/0248 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/08145 , H01L2224/16145 , H01L2224/16225 , H01L2225/06503 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06544 , H01L2225/06555 , H01L2225/06562 , H01L2924/00014 , H01L2924/0002 , H01L2924/14 , H01L2924/1436 , H01L2924/15311 , H01L2224/05552 , H01L2924/00
摘要： The semiconductor device system includes multiple stacked substantially identical semiconductor devices each including a first side and an opposing second side. First and second pads are disposed at the first side of the semiconductor device, while third and fourth pads are disposed at the second side of the semiconductor device. First interface circuit is electrically coupled to the first pad and the third pad, while second interface circuit is electrically coupled to the second pad and the fourth pad. The second interface circuit is separate and distinct from the first interface circuit. At least one first semiconductor device of the multiple semiconductor devices is offset from other of the multiple semiconductor devices such that the fourth pad on the first semiconductor device is aligned with, and electrically connected to, the first pad on an adjacent one of the multiple semiconductor devices. In some embodiments, the first pad is associated with a first capacitance, while the second pad is associated with a second capacitance that is smaller than the first capacitance.
摘要翻译：半导体器件系统包括多个层叠的基本相同的半导体器件，每个半导体器件包括第一侧和相对的第二侧。第一和第二焊盘设置在半导体器件的第一侧，而第三和第四焊盘设置在半导体器件的第二侧。第一接口电路电耦合到第一焊盘和第三焊盘，而第二接口电路电耦合到第二焊盘和第四焊盘。第二接口电路与第一接口电路分离并且不同。多个半导体器件中的至少一个第一半导体器件偏离多个半导体器件中的其它半导体器件，使得第一半导体器件上的第四焊盘与多个半导体器件中相邻的半导体器件上的第一焊盘对准并电连接到第一焊盘设备。在一些实施例中，第一焊盘与第一电容相关联，而第二焊盘与小于第一电容的第二电容相关联。

5. 发明申请

WO2007064785A3 PULSED SIGNALING MULTIPLEXER 审中-公开
标题翻译：脉冲信号多路复用器
公开(公告)号：WO2007064785A3
公开(公告)日：2008-04-10
申请号：PCT/US2006045830
申请日：2006-11-30
申请人： RAMBUS INC , BEST SCOTT C
发明人： BEST SCOTT C
IPC分类号： H04J3/04 , H04L25/493
CPC分类号： H04J3/02 , H04J3/047 , H04L25/028 , H04L25/493
摘要： In one embodiment, a pulsed signaling multiplexer is described that comprises a first AC-coupled transmitter (104a) and a second AC-coupled transmitter. (104b) The first AC-coupled transmitter (104a) includes a first driver having a first input to receive first data and a first output. A first AC-coupling element (114) couples the first output to a common output node (106). The second AC-coupled transmitter includes a second driver having a second input to receive second data, and a second output. A second AC-coupling element couples the second output to the same first common output node. (106)
摘要翻译：在一个实施例中，描述了包括第一AC耦合发射机（104a）和第二AC耦合发射机的脉冲信令多路复用器。（104b）第一AC耦合发射机（104a）包括具有用于接收第一数据和第一输出的第一输入的第一驱动器。第一AC耦合元件（114）将第一输出耦合到公共输出节点（106）。第二AC耦合发射机包括具有用于接收第二数据的第二输入的第二驱动器和第二输出。第二AC耦合元件将第二输出耦合到相同的第一公共输出节点。（106）

6. 发明申请

WO2007011439B1 PROCESSOR CONTROLLED INTERFACE 审中-公开
标题翻译：处理器控制界面
公开(公告)号：WO2007011439B1
公开(公告)日：2007-04-26
申请号：PCT/US2006013922
申请日：2006-04-11
申请人： RAMBUS INC , BEST SCOTT C , TELL STEPHEN G , POULTON JOHN WOOD
发明人： BEST SCOTT C , TELL STEPHEN G , POULTON JOHN WOOD
IPC分类号： H04L7/02 , G06F13/42
CPC分类号： G06F1/26 , G06F1/10 , G06F12/0246 , G06F13/382 , G06F13/4072 , G06F2212/7201 , G11C7/1072 , H03K19/1776 , H04L7/02
摘要： Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor (54) may be coupled through one or more bus interfaces (60)(62) of a bus (52) to one or more corresponding interface timing and/or voltage comparison circuits (72) (74) and corresponding interface timing and/or voltage adjustment circuits (70) (66).
摘要翻译：描述了一种用于控制在设备之间传输的信号的接口时序和/或电压操作的系统和方法。处理器（54）可以通过总线（52）的一个或多个总线接口（60）（62）耦合到一个或多个对应的接口定时和/或电压比较电路（72）（74）和对应的接口定时 /或电压调节电路（70）（66）。

7. 发明申请

WO2007011439A3 PROCESSOR CONTROLLED INTERFACE 审中-公开
标题翻译：处理器控制界面
公开(公告)号：WO2007011439A3
公开(公告)日：2007-03-15
申请号：PCT/US2006013922
申请日：2006-04-11
申请人： RAMBUS INC , BEST SCOTT C , TELL STEPHEN G , POULTON JOHN WOOD
发明人： BEST SCOTT C , TELL STEPHEN G , POULTON JOHN WOOD
IPC分类号： H04L7/02 , G06F13/42
CPC分类号： G06F1/26 , G06F1/10 , G06F12/0246 , G06F13/382 , G06F13/4072 , G06F2212/7201 , G11C7/1072 , H03K19/1776 , H04L7/02
摘要： Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor (54) may be coupled through one or more bus interfaces (60(62) of a bus (52) to one or more corresponding interface timing and/or voltage comparison circuits (72) (74) and corresponding interface timing and/or voltage adjustment circuits (70) (66).
摘要翻译：描述了一种用于控制在设备之间传输的信号的接口时序和/或电压操作的系统和方法。处理器（54）可以通过总线（52）的一个或多个总线接口（60（62））耦合到一个或多个对应的接口定时和/或电压比较电路（72）（74）和对应的接口定时和/ 或电压调节电路（70）（66）。

8. 发明申请

WO2018106509A1 BACKSIDE SECURITY SHIELD 审中-公开
公开(公告)号：WO2018106509A1
公开(公告)日：2018-06-14
申请号：PCT/US2017063949
申请日：2017-11-30
申请人： CRYPTOGRAPHY RES INC , BEST SCOTT C
发明人： BEST SCOTT C
IPC分类号： H04L9/12 , G06F21/73 , G06K19/07
摘要： A physically unclonable function circuit (PUF) is used to generate a fingerprint value based on the uniqueness of the physical characteristics (e.g., resistance, capacitance, connectivity, etc.) of a tamper prevention (i.e., shielding) structure that includes through-silicon vias and metallization on the backside of the integrated circuit. The physical characteristics depend on random physical factors introduced during manufacturing. This causes the chip-to-chip variations in these physical characteristics to be unpredictable and uncontrollable which makes more difficult to duplicate, clone, or modify the structure without changing the fingerprint value. By including the through-silicon vias and metallization on the backside of the integrated circuit as part of the PUF, the backside of the chip can be protected from modifications that can be used to help learn the secure cryptographic keys and/or circumvent the secure cryptographic (or other) circuitry.

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