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1. 发明申请

WO2011049679A1 SRAM DELAY CIRCUIT THAT TRACKS BITCELL CHARACTERISTICS 审中-公开
标题翻译： SRAM延迟电路跟踪比特尔特性
公开(公告)号：WO2011049679A1
公开(公告)日：2011-04-28
申请号：PCT/US2010/048052
申请日：2010-09-08
申请人： INTERNATIONAL BUSINES MACHINES CORPORATION , ARSOVSKI, Igor , BRACERAS, George, M. , HOULE, Robert, M. , PILO, Harold
发明人： ARSOVSKI, Igor , BRACERAS, George, M. , HOULE, Robert, M. , PILO, Harold
IPC分类号： G11C11/413 , G11C7/04 , G11C11/419 , G11C7/22 , G11C7/14 , G11C7/08
CPC分类号： G11C11/419 , G11C7/04 , G11C7/08 , G11C7/14 , G11C7/22 , G11C7/222 , G11C7/227 , G11C11/413
摘要： An SRAM delay circuit (14) that tracks bitcell characteristics. A circuit is disclosed that includes an input node for receiving an input signal (13); a reference node (20) for capturing a reference current from a plurality of reference cells (12); a capacitance network (15) having a discharge that is controlled by the reference current; and an output circuit that outputs the input signal with a delay (16), wherein the delay is controlled by the discharge of the capacitance network (15).
摘要翻译：一种跟踪位单元特性的SRAM延迟电路（14）。公开了一种包括用于接收输入信号（13）的输入节点的电路; 用于从多个参考单元（12）捕获参考电流的参考节点（20）; 具有由所述参考电流控制的放电的电容网络（15）; 以及输出电路，其输出具有延迟（16）的输入信号，其中所述延迟由电容网络（15）的放电来控制。

2. 发明申请

WO2010111394A2 SELF-TIMING FOR A MULTI-PORTED MEMORY SYSTEM 审中-公开
标题翻译：多时间存储器系统的自适应
公开(公告)号：WO2010111394A2
公开(公告)日：2010-09-30
申请号：PCT/US2010/028508
申请日：2010-03-24
申请人： QUALCOMM INCORPORATED , RAO, Hari , JUNG, Chang Ho , CHEN, Nan , YOON, Sei Seung
发明人： RAO, Hari , JUNG, Chang Ho , CHEN, Nan , YOON, Sei Seung
IPC分类号： G06F13/16 , G06F12/00 , G06F1/04
CPC分类号： G11C7/1075 , G11C7/22 , G11C7/227 , G11C2207/007
摘要： Multi-ported memory systems (e.g., register files) employ self-timing for operational synchronization. Thus, rather than using a reference clock duty cycle for operational synchronization, as in conventional multi-ported register files, embodiments of the present disclosure employ self-timing for such operational synchronization. According to certain embodiments, self-timing is employed to synchronize all the internal events within the memory so that all the events are spaced in time for appropriate synchronization. For instance, the completion of one event leads to triggering another event, the completion of which leads to triggering another event, and so on. Thus, in one embodiment, the self-timing is achieved by referencing the operational events with the memory (or register file) to each other, rather than to a reference clock duty cycle.
摘要翻译：多端口存储器系统（例如，寄存器文件）采用用于操作同步的自定时。因此，如在传统的多端口寄存器文件中那样，不像使用用于操作同步的参考时钟占空比，本公开的实施例采用用于这种操作同步的自定时。根据某些实施例，采用自定时来同步存储器内的所有内部事件，使得所有事件在时间上被间隔开以进行适当的同步。例如，一个事件的完成导致触发另一个事件，其完成导致触发另一个事件，等等。因此，在一个实施例中，通过将存储器（或寄存器文件）的操作事件引用到彼此而不是参考时钟占空比来实现自定时。

3. 发明申请

WO2008151099A1 CLOCK AND CONTROL SIGNAL GENERATION FOR HIGH PERFORMANCE MEMORY DEVICES 审中-公开
标题翻译：用于高性能存储器件的时钟和控制信号生成
公开(公告)号：WO2008151099A1
公开(公告)日：2008-12-11
申请号：PCT/US2008/065448
申请日：2008-05-31
申请人： QUALCOMM Incorporated , CHEN, Zhiqin , JUNG, Chang Ho
发明人： CHEN, Zhiqin , JUNG, Chang Ho
IPC分类号： G11C11/418 , G11C11/419 , G11C7/22
CPC分类号： G11C11/418 , G11C7/222 , G11C7/227 , G11C11/419 , G11C2207/2281 , G11C2207/229
摘要： Techniques for generating clock and control signals to achieve good performance for read and write operations in memory devices are described. In one design, a clock and control signal generator within a memory device includes first and second clock generators, first and second control signal generators, and a reset circuit. The first clock generator generates a first clock signal used for read and write operations. The second clock generator generates a second clock signal used for write operations. The reset circuit generates at least one reset signal for the first and second clock generators. The reset signal(s) may have timing determined based on loading due to dummy cells. The first control signal generator generates control signals used for read and write operations based on the first clock signal. The second control signal generator generates control signals used for write operations based on the second clock signal.
摘要翻译：描述了用于产生时钟和控制信号以在存储器件中进行读和写操作的良好性能的技术。在一种设计中，存储器件内的时钟和控制信号发生器包括第一和第二时钟发生器，第一和第二控制信号发生器以及复位电路。第一个时钟发生器产生用于读和写操作的第一个时钟信号。第二个时钟发生器产生用于写入操作的第二个时钟信号。复位电路为第一和第二时钟发生器产生至少一个复位信号。复位信号可以具有基于由虚拟单元造成的负载而确定的定时。第一控制信号发生器基于第一时钟信号产生用于读和写操作的控制信号。第二控制信号发生器基于第二时钟信号生成用于写入操作的控制信号。

4. 发明申请

WO2005052944A1 セルフタイミング回路を有する半導体メモリ审中-公开
标题翻译：具有自适应电路的半导体存储器
公开(公告)号：WO2005052944A1
公开(公告)日：2005-06-09
申请号：PCT/JP2003/015318
申请日：2003-11-28
申请人：富士通株式会社 , 牧康彦 , 植竹俊行
发明人：牧康彦 , 植竹俊行
IPC分类号： G11C11/413
CPC分类号： H01L27/1104 , G11C7/06 , G11C7/08 , G11C7/14 , G11C7/22 , G11C7/227 , G11C11/413
摘要：半導体メモリのセルフタイミング回路（61）において、第１の状態に設定されたセルフタイミング用ダミーメモリセル（SDMC11、12）及び第１の状態と反対の第２の状態に設定された負荷用ダミーメモリセル（LDMC11、12）を有するダミービット線（XDBL1）と、第３の状態に設定されたセルフタイミング用ダミーメモリセル（SDMC21、22）及び前記第３の状態と同一の第４の状態に設定された負荷用ダミーメモリセル（LDMC21、22）を有するダミービット線（XDBL2）と、ダミービット線（XDBL1、XDBL2）の電位の変化速度の差に対応する期間だけ遅延させて、セルフタイミング信号（SLF）を出力するタイミング制御回路（62）とを備える。
摘要翻译：一种半导体存储器的自定时电路（61），包括设置为第一状态的自定时伪存储单元（SDMC 11,12）和负载虚拟存储单元（LDMC 11,12）的伪位线（XDBL1）到与第一状态相反的第二状态; 具有设置为第三状态的自定时伪存储单元（SDMC 21,22）的虚拟位线（XDBL2），并且将设置为与第三状态相同的第四状态的虚拟存储单元（LDMC 21,22）加载; 以及用于将自定时信号（SLF）延迟并输出与虚拟位线（XDBL1，XDBL2）的电位之间的变化速度差相对应的周期的定时控制电路（62）。

5. 发明申请

WO2003032322A2 ADJUSTABLE MEMORY SELF-TIMING CIRCUIT 审中-公开
标题翻译：可调存储器自适应电路
公开(公告)号：WO2003032322A2
公开(公告)日：2003-04-17
申请号：PCT/US2002/032120
申请日：2002-10-09
申请人： ANALOG DEVICES, INC.
发明人： DeMARIS, James, Edwin , EBY, Michael, D.
IPC分类号： G11C
CPC分类号： G11C7/08 , G11C7/06 , G11C7/14 , G11C7/227
摘要： A static Random Access Memory (RAM) has a sense enable circuit. A user-determinable number of timing cells produces a timing bit line output in response to a wordline enable input. A sense timing control circuit is triggered by the timing bit line output. The sense timing control circuit produces a sense enable signal for enabling a sensing amplifier to read the logic state of memory cells in communication with the sensing amplifier. A user can change the number of timing cells to optimize operation.
摘要翻译：静态随机存取存储器（RAM）具有感测使能电路。用户可确定数量的定时单元响应于字线使能输入产生定时位线输出。感测定时控制电路由定时位线输出触发。感测定时控制电路产生感测使能信号，以使感测放大器能够读取与感测放大器通信的存储器单元的逻辑状态。用户可以更改定时单元的数量以优化操作。

6. 发明申请

WO2014042732A1 USING A REFERENCE BIT LINE IN A MEMORY 审中-公开
标题翻译：在存储器中使用参考线
公开(公告)号：WO2014042732A1
公开(公告)日：2014-03-20
申请号：PCT/US2013/046291
申请日：2013-06-18
申请人： INTEL CORPORATION , HA, Chang Wan
发明人： HA, Chang Wan
IPC分类号： G11C7/12 , G11C5/14
CPC分类号： G11C7/12 , G11C7/227
摘要： Methods, memories and systems may include charging a sense node to a logic high voltage level, and supplying charge to a bit line and to a reference bit line for a precharge period that is based, at least in part, on a time for a voltage of the reference bit line to reach a reference voltage. A memory cell that is coupled to the bit line may be selected after the precharge period, and a clamp voltage may be set based, at least in part, on the voltage of the reference bit line. If a voltage level of the bit line is less than the clamp voltage level during a sense period, charge may be drained from the sense node, and a state of the memory cell may be determined based, at least in part, on a voltage level of the sense node near an end of the sense period.
摘要翻译：方法，存储器和系统可以包括将感测节点充电到逻辑高电压电平，以及将电荷提供给位线和参考位线用于预充电周期，所述预充电周期至少部分地基于电压的时间的参考位线达到参考电压。可以在预充电周期之后选择耦合到位线的存储单元，并且可以至少部分地基于参考位线的电压来设置钳位电压。如果位线的电压电平在感测周期期间小于钳位电压电平，则可以从感测节点排出电荷，并且可以至少部分地基于电压电平来确定存储器单元的状态的感觉节点在感觉周期的结束附近。

7. 发明申请

WO2014004011A1 APPARATUS FOR REDUCING WRITE MINIMUM SUPPLY VOLTAGE FOR MEMORY 审中-公开
标题翻译：用于减少存储器的最小供电电压的装置
公开(公告)号：WO2014004011A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/044362
申请日：2013-06-05
申请人： INTEL CORPORATION
发明人： KULKARNI, Jaydeep P. , KHELLAH, Muhammad M. , TSCHANZ, James W. , GEUSKENS, Bibiche M. , DE, Vivek K.
IPC分类号： G11C7/10 , G11C5/14
CPC分类号： G11C11/419 , G11C7/227 , G11C11/412 , G11C11/413
摘要： Described is an apparatus for self-induced reduction in write minimum supply voltage for a memory element. The apparatus comprises: a memory element having cross-coupled inverters coupled to a first supply node; a power device coupled to the first supply node and a second supply node, the second supply node coupled to power supply; and an access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a bit-line which is operable to be pre-discharged to a logical low level prior to write operation.
摘要翻译：描述了一种用于存储元件的写入最小电源电压的自感应降低的装置。该装置包括：具有耦合到第一电源节点的交叉耦合的反相器的存储元件; 耦合到所述第一供应节点和第二供应节点的功率设备，所述第二供应节点耦合到电源; 以及具有耦合到字线的栅极端子，耦合到存储器元件的第一端子和耦合到位线的第二端子的存取装置，该位线可操作以在写入之前预放电到逻辑低电平操作。

8. 发明申请

WO2013109680A1 MIMICKING MULTI-VOLTAGE DOMAIN WORDLINE DECODING LOGIC FOR A MEMORY ARRAY 审中-公开
标题翻译：用于存储阵列的多电平域域字线解码逻辑
公开(公告)号：WO2013109680A1
公开(公告)日：2013-07-25
申请号：PCT/US2013/021824
申请日：2013-01-17
申请人： QUALCOMM INCORPORATED
发明人： GE, Shaoping , CHAI, Chiaming , LILES, Stephen E. , NGUYEN, Lam V. , FISCHER, Jeffrey Herbert
IPC分类号： G11C8/08 , G11C8/10 , G11C7/22
CPC分类号： G11C8/08 , G11C7/12 , G11C7/22 , G11C7/227 , G11C8/10
摘要： Systems and methods for adaptively mimicking word line decoding logic for multi-voltage domain memory are disclosed. In one embodiment, the multi-voltage domain memory includes a memory array implemented in a high voltage domain and a multi-voltage domain control circuit. The multi-voltage domain control circuit includes multi-voltage domain decoding logic that generates a word line select signal for the memory array and a multi-voltage domain mimic logic that mimics the multi-voltage domain decoding logic to generate a dummy wordline signal. In one embodiment, the dummy word line signal is utilized to trigger an ending edge (e.g., a falling edge) of the word line select signal once the word line is asserted. In addition or alternatively, the dummy word line signal is utilized to generate one or more control signals for the memory array such as, for example, a pre-charge control signal and/or a sense amplifier enable signal.
摘要翻译：公开了用于自适应模拟用于多电压域存储器的字线解码逻辑的系统和方法。在一个实施例中，多电压域存储器包括以高电压域实现的存储器阵列和多电压域控制电路。多电压域控制电路包括产生用于存储器阵列的字线选择信号的多电压域解码逻辑和模拟多电压域解码逻辑以产生伪字线信号的多电压域模拟逻辑。在一个实施例中，一旦该字线被断言，该虚拟字线信号用于触发字线选择信号的结束边缘（例如，下降沿）。另外或替代地，伪字线信号用于产生用于存储器阵列的一个或多个控制信号，例如预充电控制信号和/或读出放大器使能信号。

9. 发明申请

WO2010111394A3 SELF-TIMING FOR A MULTI-PORTED MEMORY SYSTEM 审中-公开
标题翻译：多时间存储器系统的自适应
公开(公告)号：WO2010111394A3
公开(公告)日：2011-01-20
申请号：PCT/US2010028508
申请日：2010-03-24
申请人： QUALCOMM INC , RAO HARI , JUNG CHANG HO , CHEN NAN , YOON SEI SEUNG
发明人： RAO HARI , JUNG CHANG HO , CHEN NAN , YOON SEI SEUNG
IPC分类号： G06F13/16 , G06F1/04 , G06F12/00
CPC分类号： G11C7/1075 , G11C7/22 , G11C7/227 , G11C2207/007
摘要： Multi-ported memory systems (e.g., register files) employ self-timing for operational synchronization. Thus, rather than using a reference clock duty cycle for operational synchronization, as in conventional multi-ported register files, embodiments of the present disclosure employ self-timing for such operational synchronization. According to certain embodiments, self-timing is employed to synchronize all the internal events within the memory so that all the events are spaced in time for appropriate synchronization. For instance, the completion of one event leads to triggering another event, the completion of which leads to triggering another event, and so on. Thus, in one embodiment, the self-timing is achieved by referencing the operational events with the memory (or register file) to each other, rather than to a reference clock duty cycle.
摘要翻译：多端口存储器系统（例如，寄存器文件）采用用于操作同步的自定时。因此，如在传统的多端口寄存器文件中那样，不像使用用于操作同步的参考时钟占空比，本公开的实施例采用用于这种操作同步的自定时。根据某些实施例，采用自定时来同步存储器内的所有内部事件，使得所有事件在时间上被间隔开以进行适当的同步。例如，一个事件的完成导致触发另一个事件，其完成导致触发另一个事件，等等。因此，在一个实施例中，通过将存储器（或寄存器文件）的操作事件引用到彼此而不是参考时钟占空比来实现自定时。

10. 发明申请

WO2008103516A1 MEMORY HAVING A DUMMY BITLINE FOR TIMING CONTROL 审中-公开
标题翻译：具有时序控制功能的内存
公开(公告)号：WO2008103516A1
公开(公告)日：2008-08-28
申请号：PCT/US2008/051843
申请日：2008-01-24
申请人： FREESCALE SEMICONDUCTOR INC. , JETTON, Mark W. , CHILDS, Lawrence F. , LU, Olga R. , STARNES, Glenn E.
发明人： JETTON, Mark W. , CHILDS, Lawrence F. , LU, Olga R. , STARNES, Glenn E.
IPC分类号： G11C11/00
CPC分类号： G11C7/22 , G11C7/227
摘要： A memory having at least one memory array block (10), the at least one memory array block (10) comprising N wordlines, wherein N is greater than one, is provided. The memory comprises a plurality of sense amplifiers (28, 29) coupled to the at least one memory array block (10). The memory further comprises at least one dummy bitline (40, 41), wherein the at least one dummy bitline (40, 41) comprises M dummy bitcells (42, 43), wherein M is equal to N. The memory further comprises a timing circuit (20) coupled to the at least one dummy bitline (40, 41), wherein the timing circuit (20) comprises at least one stack of pull-down transistors (60, 61) coupled to a sense circuit (70) for generating a latch control output signal (104) used for timing control of memory accesses. Timing control may include generating a sense trigger signal (44) to enable the plurality of sense amplifiers (28, 29) for read operations and/or generating a local reset signal (100) for terminating memory accesses, such as disabling the plurality of write drivers (26, 27) for write operations.
摘要翻译：具有至少一个存储器阵列块（10）的存储器，提供包括N个字线的至少一个存储器阵列块（10），其中N大于1。存储器包括耦合到至少一个存储器阵列块（10）的多个读出放大器（28,29）。所述存储器还包括至少一个伪位线（40,41），其中所述至少一个伪位线（40,41）包括M个虚拟位单元（42,43），其中M等于N。所述存储器还包括定时电路（20），耦合到所述至少一个虚拟位线（40,41），其中所述定时电路（20）包括耦合到感测电路（70）的至少一个下拉晶体管堆叠（60,61），用于产生用于定时控制存储器存取的锁存控制输出信号（104）。定时控制可以包括生成感测触发信号（44）以使得多个读出放大器（28,29）能够进行读取操作和/或生成用于终止存储器访问的本地复位信号（100），例如禁用多个写入驱动程序（26,27）用于写操作。

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