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1. 发明申请

WO2007027881A2 MICROELECTRONIC IMAGING DEVICES AND ASSOCIATED METHODS FOR ATTACHING TRANSMISSIVE ELEMENTS 审中-公开
标题翻译：微电子成像装置和用于安装传输元件的相关方法
公开(公告)号：WO2007027881A2
公开(公告)日：2007-03-08
申请号：PCT/US2006/034012
申请日：2006-08-31
申请人： MICRON TECHNOLOGY, INC. , FARNWORTH, Warren, M. , WOOD, Alan, G.
发明人： FARNWORTH, Warren, M. , WOOD, Alan, G.
IPC分类号： H01L27/146
CPC分类号： H01L27/14687 , H01L27/14618 , H01L27/14623 , H01L27/14627 , H01L27/14632 , H01L27/14636 , H01L27/14685 , H01L31/0232 , H01L2224/13
摘要： Microelectronic imaging devices and associated methods for attaching transmissive elements are disclosed. A manufacturing method in accordance with one embodiment of the invention includes providing an imager workpiece having multiple image sensor dies configured to detect energy over a target frequency. The image sensor dies can include an image sensor and a corresponding lens device positioned proximate to the image sensor. The method can further include positioning standoffs adjacent to the lens devices while the image sensor dies are connected to each other via the imager workpiece. At least one transmissive element can be attached to the workpiece at least proximate to the standoffs so the lens devices are positioned between the corresponding image sensors and the at least one transmissive element. Accordingly, the at least one transmissive element can protect the image sensors while the image sensor dies are still connected. In a subsequent process, the image sensor dies can be separated from each other.
摘要翻译：公开了用于附接透射元件的微电子成像装置和相关方法。根据本发明的一个实施例的制造方法包括提供具有多个图像传感器管芯的成像器工件，所述多个图像传感器管芯被配置为检测目标频率上的能量。图像传感器管芯可以包括图像传感器和位于图像传感器附近的相应的透镜装置。该方法可以进一步包括在镜头装置附近定位支架，同时图像传感器芯片通过成像器工件彼此连接。至少一个透射元件可以至少靠近支座附接到工件，使得透镜装置位于对应的图像传感器和至少一个透射元件之间。因此，至少一个透射元件可以在图像传感器管芯仍然连接时保护图像传感器。在随后的过程中，图像传感器芯片可以彼此分离。

2. 发明申请

WO2007019199A1 METHODS OF FORMING THROUGH-WAFER INTERCONNECTS AND STRUCTURES RESULTING THEREFROM 审中-公开
标题翻译：形成通过波形互连的方法和结果
公开(公告)号：WO2007019199A1
公开(公告)日：2007-02-15
申请号：PCT/US2006/030167
申请日：2006-08-02
申请人： MICRON TECHNOLOGY, INC. , FARNWORTH, Warren, M. , WOOD, Alan, G.
发明人： FARNWORTH, Warren, M. , WOOD, Alan, G.
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76898 , B33Y80/00 , H01L23/481 , H01L2924/0002 , H01L2924/09701 , H01L2924/12044 , H01L2924/00
摘要： Methods for forming conductive vias or through-wafer interconnects in semiconductor substrates and resulting through wafer interconnect structures are disclosed. In one embodiment of the present invention, a method of forming a through wafer interconnect structure includes the acts of forming an aperture in a first surface of a substrate, depositing a first insulative or dielectric layer on an inner surface of the aperture, depositing an electrically conductive layer over the first dielectric layer, depositing a second insulative or dielectric layer on the inner surface of the aperture over the electrically conductive material, and exposing a portion of the electrically conductive layer through the second, opposing surface of the substrate. Semiconductor devices including through-wafer interconnects produced with the methods of the instant invention are also described.
摘要翻译：公开了用于在半导体衬底中形成导电通孔或贯穿晶片互连以及通过晶片互连结构形成的方法。在本发明的一个实施例中，形成贯穿晶片互连结构的方法包括在衬底的第一表面中形成孔的动作，在孔的内表面上沉积第一绝缘或电介质层，导电层，在所述导电材料的所述孔的内表面上沉积第二绝缘或电介质层，以及将所述导电层的一部分暴露于所述衬底的所述第二相对表面。还描述了包括用本发明的方法生产的晶片间互连的半导体器件。

3. 发明申请

WO2007133302A2 SEMICONDUCTOR COMPONENTS AND SYSTEMS HAVING ENCAPSULATED THROUGH WIRE INTERCONNECTS (TWI) AND WAFER LEVEL METHODS OF FABRICATION 审中-公开
标题翻译：具有通过线互连（TWI）封装的半导体元件和系统以及制造水平的制造方法
公开(公告)号：WO2007133302A2
公开(公告)日：2007-11-22
申请号：PCT/US2007/002336
申请日：2007-01-29
申请人： MICRON TECHNOLOGY, INC. , HEMBREE, David, R. , WOOD, Alan, G.
发明人： HEMBREE, David, R. , WOOD, Alan, G.
IPC分类号： H01J17/49
CPC分类号： H01L24/16 , G01R1/06716 , G01R1/07307 , H01L21/486 , H01L21/565 , H01L21/568 , H01L21/76877 , H01L21/76885 , H01L21/76898 , H01L23/481 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/78 , H01L24/81 , H01L24/85 , H01L25/0657 , H01L25/105 , H01L2224/02125 , H01L2224/0233 , H01L2224/02333 , H01L2224/02335 , H01L2224/02372 , H01L2224/02373 , H01L2224/02375 , H01L2224/0333 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05082 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05548 , H01L2224/05552 , H01L2224/05554 , H01L2224/05555 , H01L2224/05567 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/06181 , H01L2224/1134 , H01L2224/13009 , H01L2224/13024 , H01L2224/13082 , H01L2224/131 , H01L2224/16146 , H01L2224/45014 , H01L2224/45015 , H01L2224/451 , H01L2224/45116 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/45572 , H01L2224/45639 , H01L2224/45644 , H01L2224/45655 , H01L2224/45684 , H01L2224/45698 , H01L2224/48091 , H01L2224/4813 , H01L2224/48145 , H01L2224/48455 , H01L2224/48463 , H01L2224/4847 , H01L2224/48471 , H01L2224/48475 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/48824 , H01L2224/48847 , H01L2224/4899 , H01L2224/48992 , H01L2224/78301 , H01L2224/85051 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2224/85951 , H01L2225/06506 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2225/1058 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01088 , H01L2924/014 , H01L2924/07811 , H01L2924/10155 , H01L2924/10161 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/181 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/30105 , H01L2924/3011 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2224/45164 , H01L2924/013 , H01L2924/00013
摘要： A semiconductor component (10) includes a semiconductor substrate (12) having a substrate contact (20), and a through wire interconnect (TWI) (14) attached to the substrate contact (20). The through wire interconnect (14) provides a multi level interconnect having contacts (32, 48) on opposing first (17) and second (18) sides of the semiconductor substrate (12). The through wire interconnect (TWI) (14) includes a via (28) through the substrate contact (20) and the substrate (12), a wire (30) in the via (28) having a bonded connection (42) with the substrate contact (20), a first contact (32) on the wire proximate to the first side (17), and a second contact (46) on the wire (30) proximate to the second side (18). The through wire interconnect (TWI) (14) also includes a polymer layer (16) which partially encapsulates the through wire interconnect (TWI) (14) while leaving the first contact (32) exposed. The semiconductor component (10) can be used to fabricate stacked systems (54), module systems (74) and test systems (72). A method for fabricating the semiconductor component (10) can include a film assisted molding process for forming the polymer layer (16).
摘要翻译：半导体部件（10）包括具有衬底接触件（20）的半导体衬底（12）和连接到衬底接触件（20）的通孔互连（TWI）（14）。通线互连（14）提供在半导体衬底（12）的相对的第一（17）和第二（18）侧上具有触点（32,48）的多电平互连。通线互连（TWI）（14）包括穿过基板接触件（20）和基板（12）的通孔（28），通孔（28）中的导线（30）具有接合连接（42）基板触点（20），靠近第一侧（17）的导线上的第一触点（32）以及接近第二侧（18）的导线（30）上的第二触点（46）。通孔互连（TWI）（14）还包括聚合物层（16），其在使第一接触（32）暴露的同时部分地封装通孔互连（TWI）（14）。半导体部件（10）可用于制造堆叠系统（54），模块系统（74）和测试系统（72）。制造半导体部件（10）的方法可以包括用于形成聚合物层（16）的膜辅助成型工艺。

4. 发明申请

WO2006011897A1 PACKAGED MICROELECTRONIC IMAGERS AND METHODS OF PACKAGING MICROELECTRONIC IMAGERS 审中-公开
标题翻译：包装微电子图像和包装微电子图像的方法
公开(公告)号：WO2006011897A1
公开(公告)日：2006-02-02
申请号：PCT/US2004/037415
申请日：2004-11-09
申请人： MICRON TECHNOLOGY, INC. , AKRAM, Salman , WATKINS, Charles, M. , KIRBY, Kyle, K. , WOOD, Alan, G. , HIATT, William, M.
发明人： AKRAM, Salman , WATKINS, Charles, M. , KIRBY, Kyle, K. , WOOD, Alan, G. , HIATT, William, M.
IPC分类号： H01L27/146
CPC分类号： H01L27/146 , H01L21/76898 , H01L27/14618 , H01L27/148 , H01L31/02016 , H01L2224/48227 , H01L2924/01046 , H01L2924/01066 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/00
摘要： Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, first and second conductive layers deposited onto at least a portion of the dielectric liner, and a conductive fill material deposited into the passage over at least a portion of the second conductive layer and electrically coupled to the bond-pad.
摘要翻译：本文公开了微电子成像器，用于封装微电子成像器的方法，以及用于在微电子成像器中形成导电晶片间互连的方法。在一个实施例中，微电子成像管芯可以包括微电子衬底，集成电路和电耦合到集成电路的图像传感器。接合焊盘由衬底承载并电耦合到集成电路。导电晶片互连延伸穿过衬底并与接合焊盘接触。互连可以包括完全延伸穿过衬底和接合焊盘的通道，沉积到通道中并与衬底接触的电介质衬垫，沉积在电介质衬垫的至少一部分上的第一和第二导电层以及导电在第二导电层的至少一部分上沉积到通道中并且电耦合到接合焊盘的填充材料。

5. 发明申请

WO2012170129A2 SEMICONDUCTOR CONSTRUCTIONS HAVING THROUGH-SUBSTRATE INTERCONNECTS, AND METHODS OF FORMING THROUGH-SUBSTRATE INTERCONNECTS 审中-公开
标题翻译：具有通过基板互连的半导体结构及其形成通过基板互连的方法
公开(公告)号：WO2012170129A2
公开(公告)日：2012-12-13
申请号：PCT/US2012/036401
申请日：2012-05-03
申请人： MICRON TECHNOLOGY, INC. , WOOD, Alan, G. , IRELAND, Philip, J.
发明人： WOOD, Alan, G. , IRELAND, Philip, J.
IPC分类号： H01L21/28 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/76898 , H01L23/481 , H01L23/5283 , H01L24/03 , H01L24/05 , H01L2224/03444 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/0347 , H01L2224/0348 , H01L2224/03845 , H01L2224/05009 , H01L2224/05022 , H01L2224/05025 , H01L2224/05026 , H01L2224/05027 , H01L2224/05083 , H01L2224/05094 , H01L2224/05096 , H01L2224/05147 , H01L2224/05157 , H01L2224/05176 , H01L2224/05181 , H01L2224/05187 , H01L2224/05644 , H01L2224/05655 , H01L2924/04953 , H01L2924/0496 , H01L2924/01074 , H01L2924/04941
摘要： Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor substrate, and part of an interconnect may be formed within the opening. Another opening may be formed to extend from a second side of the substrate to the first part of the interconnect, and another part of the interconnect may be formed within such opening. Some embodiments include semiconductor constructions having a first part of a through-substrate interconnect extending partially through a semiconductor substrate from a first side of the substrate; and having a second part of the through-substrate interconnect extending from a second side of the substrate and having multiple separate electrically conductive fingers that all extend to the first part of the interconnect.
摘要翻译：一些实施例包括通过半导体衬底形成互连的方法。可以形成开口以在半导体衬底的中途延伸，并且可以在开口内形成一部分互连。另一个开口可以形成为从基板的第二侧延伸到互连的第一部分，并且互连的另一部分可以形成在该开口内。一些实施例包括半导体结构，其具有从衬底的第一侧部分延伸穿过半导体衬底的穿透衬底互连件的第一部分; 并且具有从所述衬底的第二侧延伸的所述贯通衬底互连件的第二部分，并且具有全部延伸到所述互连件的第一部分的多个分离的导电指状物。

6. 发明申请

WO2007092176A2 METHODS FOR FABRICATING AND FILLING CONDUCTIVE VIAS AND CONDUCTIVE VIAS SO FORMED 审中-公开
标题翻译：制造和填充导电VIAS和导电VIAS的方法
公开(公告)号：WO2007092176A2
公开(公告)日：2007-08-16
申请号：PCT/US2007/002150
申请日：2007-01-26
申请人： MICRON TECHNOLOGY, INC. , AKRAM, Salman , HIATT, William, Mark , OLIVER, Steve , WOOD, Alan, G. , RIGG, Sidney, B. , WARK, James, M. , KIRBY, Kyle, K.
发明人： AKRAM, Salman , HIATT, William, Mark , OLIVER, Steve , WOOD, Alan, G. , RIGG, Sidney, B. , WARK, James, M. , KIRBY, Kyle, K.
CPC分类号： H01L21/76898 , H01L23/481 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/13009 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/17181 , H01L2924/09701
摘要： Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with the protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.
摘要翻译：用于形成导电通孔的方法包括在衬底中形成一个或多个通孔。通孔孔可以用单个掩模形成，在蚀刻过程中去除光掩模的情况下，保护层，接合焊盘或衬底的其它特征用作硬掩膜。通孔可以被配置为便于将包括低K电介质材料的电介质涂层粘附到其表面上。可以在每个通孔的表面上形成阻挡层。可以形成可以包括种子材料的基层，以便于导电材料随后的选择性沉积在通孔的表面上。还公开了包括由这些方法产生的半导体器件的所得半导体器件，中间结构和组件以及电子器件。

7. 发明申请

WO2006124295A3 BACKSIDE METHOD AND SYSTEM FOR FABRICATING SEMICONDUCTOR COMPONENTS WITH CONDUCTIVE INTERCONNECTS 审中-公开
公开(公告)号：WO2006124295A3
公开(公告)日：2006-11-23
申请号：PCT/US2006/017036
申请日：2006-05-04
申请人： MICRON TECHNOLOGY INC. , WOOD, Alan, G. , HIATT, William, M. , HEMBREE, David, R.
发明人： WOOD, Alan, G. , HIATT, William, M. , HEMBREE, David, R.
IPC分类号： H01L21/265 , H01L21/425 , H01L21/44 , H01L21/261 , H01L21/4763 , H01L21/46 , H01L21/00 , H01L29/40 , H01L29/00 , H01L29/80 , H01L31/00 , H01L23/02
摘要： A backside method for fabricating a semiconductor component (50) with a conductive interconnect (44) includes the step of providing a semiconductor substrate (12) having a circuit side (14), a backside (16), and a substrate contact (18) on the circuit side (14). The method also includes the steps of forming a substrate opening (30) from the backside (16) to the substrate contact (18), and then bonding the conductive interconnect (44) to an inner surface (32) of the substrate contact (18). A system (62) for performing the method includes the semiconductor substrate (12), a thinning system (64) for thinning the semiconductor substrate (12), an etching system (66A) for forming the substrate opening (30), and a bonding system (38) for bonding the conductive interconnect (44) to the substrate contact (18). The semiconductor component (50) can be used to form module components (98), underfilled components (106), stacked components (116), and image sensor semiconductor components (50IS).

8. 发明申请

WO1996014660A1 METHOD FOR FABRICATING A SELF-LIMITING SILICON BASED INTERCONNECT FOR TESTING BARE SEMICONDUCTOR DICE 审中-公开
标题翻译：一种用于测试半导体半导体的自限制硅基互连的方法
公开(公告)号：WO1996014660A1
公开(公告)日：1996-05-17
申请号：PCT/US1995014483
申请日：1995-11-06
申请人： MICRON TECHNOLOGY, INC.
发明人： MICRON TECHNOLOGY, INC. , AKRAM, Salman , FARNWORTH, Warren, M. , WOOD, Alan, G.
IPC分类号： H01L21/66
CPC分类号： G01R1/06738 , G01R1/07314 , H01L2224/13019 , H05K1/0306 , H05K3/325 , H05K2201/0367 , H05K2201/0373 , H05K2201/09045 , Y10T29/49155 , Y10T29/49453
摘要： A method for forming a self-limiting, silicon based interconnect for making temporary electrical contact with bond pads on a semiconductor die is provided. The interconnect includes a silicon substrate having an array of contact members adapted to contact the bond pads on the die for test purposes (e.g., burn-in testing). The interconnect is fabricated by: forming the contact members on the substrate; forming a conductive layer on the tip of the contact members; and then forming conductive traces to the conductive layer. The conductive layer is formed by depositing a silicon containing layer (e.g., polysilicon, amorphous silicon) and a metal layer (e.g., titanium, tungsten, platinum) on the substrate and contact members. These layers are reacted to form a silicide. The unreacted metal and silicon containing layer are then etched selective to the conductive layer which remains on the tip of the contact members. Conductive traces are then formed in contact with the conductive layer using a suitable metallization process. Bond wires are attached to the conductive traces and may be attached to external test circuitry. Alternately, another conductive path such as external contacts (e.g., slide contacts) may provide a conductive path between the conductive traces and external circuitry. The conductive layer, conductive traces and bond wires provide a low resistivity conductive path from the tips of the contact members to external test circuitry.
摘要翻译：提供一种用于形成用于与半导体管芯上的接合焊盘暂时电接触的自限制硅基互连的方法。互连包括具有适于接触芯片上的接合焊盘的接触部件阵列的硅衬底用于测试目的（例如，老化测试）。互连通过以下方式制造：在衬底上形成接触构件; 在所述接触构件的尖端上形成导电层; 然后在导电层上形成导电迹线。通过在衬底和接触构件上沉积含硅层（例如，多晶硅，非晶硅）和金属层（例如，钛，钨，铂）形成导电层。这些层反应形成硅化物。然后将未反应的含金属和含硅层选择性地蚀刻到保留在接触构件的尖端上的导电层。然后使用合适的金属化工艺将导电迹线形成为与导电层接触。接合线连接到导电迹线，并且可以附接到外部测试电路。或者，诸如外部触点（例如，滑动触点）的另一导电路径可以在导电迹线和外部电路之间提供导电路径。导电层，导电迹线和接合线提供从接触构件的尖端到外部测试电路的低电阻率导电路径。

9. 发明申请

WO1996014659A1 METHOD FOR FORMING CONTACT PINS FOR SEMICONDUCTOR DICE AND INTERCONNECTS 审中-公开
标题翻译：用于形成半导体数字和互连的接触引脚的方法
公开(公告)号：WO1996014659A1
公开(公告)日：1996-05-17
申请号：PCT/US1995014482
申请日：1995-11-06
申请人： MICRON TECHNOLOGY, INC.
发明人： MICRON TECHNOLOGY, INC. , FARNWORTH, Warren, M. , AKRAM, Salman , WOOD, Alan, G.
IPC分类号： H01L21/66
CPC分类号： H01L24/12 , G01R1/06 , G01R31/2884 , G01R31/2886 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/742 , H01L2224/0401 , H01L2224/04042 , H01L2224/05568 , H01L2224/056 , H01L2224/05624 , H01L2224/05644 , H01L2224/05655 , H01L2224/1134 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/451 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45155 , H01L2224/48463 , H01L2224/48624 , H01L2224/48644 , H01L2224/48655 , H01L2224/48724 , H01L2224/48755 , H01L2224/48844 , H01L2224/48855 , H01L2224/742 , H01L2224/78301 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01039 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H05K3/328 , Y10T29/49149 , H01L2924/00014 , H01L2224/13099 , H01L2224/48824 , H01L2924/00 , H01L2224/48744 , H01L2924/00012
摘要： A method for forming contact pins adapted to form an electrical connection with a mating contact location is provided. In a first embodiment, the contact pins are formed on an interconnect used for testing a semiconductor die and are adapted to establish an electrical connection with the bond pads of the die. In a second embodiment, the contact pins are formed directly on the bond pads of a die and can be used for establishing a permanent or temporary electrical connection to the pads. The contact pins include a base portion attached to the die or interconnect, a compliant spring segment, and a contact ball at the tip. The contact pins are formed using a wire bonding process or a welding process in which a metal wire is simultaneously heated and shaped into a compliant structure as it is attached to the die or interconnect.
摘要翻译：提供一种用于形成适于与配合接触位置形成电连接的接触针的方法。在第一实施例中，接触针形成在用于测试半导体管芯的互连件上，并且适于与管芯的接合焊盘建立电连接。在第二实施例中，接触销直接形成在管芯的接合焊盘上，并且可以用于建立与焊盘的永久或临时的电连接。接触销包括附接到模具或互连件的基部，柔性弹簧段和尖端处的接触球。接触销使用引线接合工艺或焊接工艺形成，其中金属线同时被加热并且被成形为顺应结构，因为它附接到管芯或互连件。

10. 发明申请

WO1996035129A1 METHOD AND APPARATUS FOR TESTING SEMICONDUCTOR DICE 审中-公开
标题翻译：用于测试半导体切片的方法和装置
公开(公告)号：WO1996035129A1
公开(公告)日：1996-11-07
申请号：PCT/US1996006002
申请日：1996-04-30
申请人： MICRON TECHNOLOGY, INC.
发明人： MICRON TECHNOLOGY, INC. , WOOD, Alan, G. , FARNWORTH, Warren, M. , AKRAM, Salman , HEMBREE, David, R.
IPC分类号： G01R31/02
CPC分类号： G01R1/07314 , G01R1/0433 , G01R1/0466 , G01R1/0483 , G01R3/00 , G01R31/2863 , G01R31/2886 , G01R31/2889 , G01R31/2893 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/48 , H01L24/80 , H01L24/85 , H01L2224/16145 , H01L2224/48 , H01L2224/85001 , H01L2224/85205 , H01L2225/06562 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H05K3/0058 , H05K3/0067 , H05K3/4007 , H05K3/423 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H01L2224/78 , H01L2224/45099 , H01L2224/05599 , H01L2924/00
摘要： A method and apparatus for testing unpackaged semiconductor dice includes a mother board (10) and a plurality of interconnects (12) mounted on the mother board (10) and adapted to establish a temporary electrical connection with the dice (14). The interconnects (12) can be formed with a silicon substrate (20) and raised contact members (16) for contacting the bond pads (22) of a die (14). Alternately the interconnects (16) can be formed with micro bump contact members (16) mounted on an insulating film (74). The mother board (10) allows each die (14) to be tested separately for speed and functionality and to also be burn-in tested in parallel using standard burn-in ovens. In an alternate embodiment testing is performed using a mother board/daughter board arrangement. Each daughter board (82) includes interconnects (12) that allow the dice (14) to be tested individually for speed and functionality. Multiple daughter boards (82) can then be mounted to the mother board (10) for burn-in testing using standard burn-in ovens.
摘要翻译：用于测试未封装半导体晶片的方法和装置包括安装在母板（10）上的母板（10）和多个互连（12），并适于建立与芯片（14）的临时电连接。互连（12）可以形成有用于接触管芯（14）的接合焊盘（22）的硅衬底（20）和凸起的接触构件（16）。或者，互连（16）可以形成有安装在绝缘膜（74）上的微凸块接触构件（16）。母板（10）允许每个模具（14）单独测试速度和功能，并且还可以使用标准老化炉并行测试。在替代实施例中，使用母板/子板布置进行测试。每个子板（82）包括允许骰子（14）单独测试速度和功能的互连（12）。然后可以将多个子板（82）安装到母板（10）上，以使用标准老化烤箱进行老化测试。

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