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1. 发明申请

WO2007092176A2 METHODS FOR FABRICATING AND FILLING CONDUCTIVE VIAS AND CONDUCTIVE VIAS SO FORMED 审中-公开
标题翻译：制造和填充导电VIAS和导电VIAS的方法
公开(公告)号：WO2007092176A2
公开(公告)日：2007-08-16
申请号：PCT/US2007/002150
申请日：2007-01-26
申请人： MICRON TECHNOLOGY, INC. , AKRAM, Salman , HIATT, William, Mark , OLIVER, Steve , WOOD, Alan, G. , RIGG, Sidney, B. , WARK, James, M. , KIRBY, Kyle, K.
发明人： AKRAM, Salman , HIATT, William, Mark , OLIVER, Steve , WOOD, Alan, G. , RIGG, Sidney, B. , WARK, James, M. , KIRBY, Kyle, K.
CPC分类号： H01L21/76898 , H01L23/481 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/13009 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/17181 , H01L2924/09701
摘要： Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with the protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.
摘要翻译：用于形成导电通孔的方法包括在衬底中形成一个或多个通孔。通孔孔可以用单个掩模形成，在蚀刻过程中去除光掩模的情况下，保护层，接合焊盘或衬底的其它特征用作硬掩膜。通孔可以被配置为便于将包括低K电介质材料的电介质涂层粘附到其表面上。可以在每个通孔的表面上形成阻挡层。可以形成可以包括种子材料的基层，以便于导电材料随后的选择性沉积在通孔的表面上。还公开了包括由这些方法产生的半导体器件的所得半导体器件，中间结构和组件以及电子器件。

2. 发明申请

WO2006028715A2 SELECTIVE NICKEL PLATING OF ALUMINIUM, COPPER AND TUNGSTEN STRUCTURES 审中-公开
标题翻译：铝，铜和钨结构的选择性镍镀层
公开(公告)号：WO2006028715A2
公开(公告)日：2006-03-16
申请号：PCT/US2005/030228
申请日：2005-08-25
申请人： MICRON TECHNOLOGY, INC. , AKRAM, Salman , WARK, James, M. , HIATT, William, M.
发明人： AKRAM, Salman , WARK, James, M. , HIATT, William, M.
IPC分类号： C23C18/16
CPC分类号： H01L21/76879 , C23C18/1607 , C23C18/1637 , C23C18/1831 , C23C18/1834 , C23C18/34 , C23C18/36 , H01L21/288 , H01L21/76898 , H01L2924/00013 , Y10T428/12528 , Y10T428/24917 , H01L2224/29099
摘要： A method of selectively plating nickel on an intermediate semiconductor device structure. The method comprises providing an intermediate semiconductor device structure having at least one aluminum or copper structure and at least one tungsten structure. One of the aluminum or copper structure and the tungsten structure is nickel plated while the other remains unplated. The aluminum or copper structure or the tungsten structure may first be activated toward nickel plating. The activated aluminum or copper structure or the activated tungsten structure may then be nickel plated by immersing the intermediate semiconductor device structure in an electroless nickel plating solution. The unplated aluminum or copper structure or the unplated tungsten structure may subsequently be nickel plated by activating the unplated structure and nickel plating the activated structure. A method of simultaneously plating the aluminum or copper structure and the tungsten structure with nickel is also disclosed, as is an intermediate semiconductor device structure.
摘要翻译：在中间半导体器件结构上选择性镀镍的方法。该方法包括提供具有至少一个铝或铜结构和至少一个钨结构的中间半导体器件结构。铝或铜结构之一和钨结构是镀镍的，而另一个保持未镀层。可以首先将铝或铜结构或钨结构活化成镀镍。活化的铝或铜结构或活化的钨结构可以通过将中间半导体器件结构浸入无电镀镍溶液中而进行镀镍。然后通过激活未镀层的结构和镀镍活化的结构，可以将未镀覆的铝或铜结构或未镀覆的钨结构镀镍。还公开了一种用镍同时电镀铝或铜结构和钨结构的方法，以及中间半导体器件结构。

3. 发明申请

WO1998012706A1 DEVICE AND METHOD FOR TESTING INTEGRATED CIRCUIT DICE IN AN INTEGRATED CIRCUIT MODULE 审中-公开
标题翻译：用于在集成电路模块中测试集成电路的装置和方法
公开(公告)号：WO1998012706A1
公开(公告)日：1998-03-26
申请号：PCT/US1997014564
申请日：1997-08-20
申请人： MICRON TECHNOLOGY, INC.
发明人： MICRON TECHNOLOGY, INC. , FARNWORTH, Warren, M. , WARK, James, M. , NELSON, Eric, S. , DUESMAN, Kevin, G.
IPC分类号： G11C29/00
CPC分类号： H01L22/22 , G01R31/2884 , G11C29/46 , G11C29/785 , G11C29/80 , G11C29/808 , H01L2224/48091 , H04J2203/0062 , H01L2924/00014
摘要： An IC module (20), such as a Multi-Chip Module (MCM), includes multiple IC (12) dice each having a test mode enable bond pad (30), such as an output enable pad. A fuse incorporated into the MCM's substrate connects each dice's test mode enable pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable pads to one of the MCM's reference voltage pins. By applying a supply voltage to the test mode enable pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a reference voltage applied to the test mode enable pads through the reference voltage pins and the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging. A method for performing such testing once the test mode has been initiated and for repairing any failing elements found during testing, includes providing test signals to the dice, receiving response signals from the dice, evaluating the response signals to identify any failing elements in the dice, programming the failing elements addresses into anti-fuses in the dice with a programming voltage, confirming that the addresses are programmed by determining the resistance of the anti-fuses, re-testing the dice, receiving response signals from the re-tested dice, and evaluating the response signals to confirm all repairs.
摘要翻译：诸如多芯片模块（MCM）的IC模块（20）包括多个具有测试模式使能接合焊盘（30）的IC（12）芯片，诸如输出使能焊盘。集成到MCM基板中的保险丝将每个骰子的测试模式使能焊盘连接到MCM的无连接（N / C）引脚之一，并且连接到衬底中的电阻将测试模式使能焊盘连接到MCM的参考电压引脚之一。通过向测试模式使能焊盘通过N / C引脚施加电源电压，在骰子中启动测试模式。一旦测试完成，保险丝可能会被熔断，并且施加到测试模式的参考电压使得焊盘能够通过参考电压引脚，并且电阻器将禁用骰子中的测试模式并启动操作模式。因此，封装在IC模块中的裸片可以在封装后进行测试。一旦测试模式已经启动并且用于修复在测试期间发现的任何故障元件，执行这种测试的方法包括向骰子提供测试信号，从骰子接收响应信号，评估响应信号以识别骰子中的任何故障元件将故障元件地址编程为具有编程电压的骰子中的抗熔丝，通过确定抗熔丝的电阻，重新测试骰子，从重新测试的骰子接收响应信号来确认地址被编程，并评估响应信号以确认所有维修。

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