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1. 发明申请

WO2017155625A1 ELECTRONIC COMPONENTS HAVING THREE-DIMENSIONAL CAPACITORS IN A METALLIZATION STACK 审中-公开
标题翻译：在金属堆叠中具有三维电容器的电子元件
公开(公告)号：WO2017155625A1
公开(公告)日：2017-09-14
申请号：PCT/US2017/015513
申请日：2017-01-27
申请人： INTEL IP CORPORATION
发明人： REINGRUBER, Klaus , ALBERS, Sven , GEISSLER, Christian
IPC分类号： H01L49/02 , H01L27/08 , H01L23/522 , H01L21/768 , H01L23/00
摘要： Disclosed herein are electronic components having three-dimensional capacitors disposed in a metallization stack, as well as related methods and devices. In some embodiments, for example, an electronic component may include: a metallization stack and a capacitor disposed in the metallization stack wherein the capacitor includes a first conductive plate having a plurality of recesses, and a second conductive plate having a plurality of projections, wherein individual projections of the plurality of projections extend into corresponding individual recesses of the plurality of recesses without contacting the first conductive plate.
摘要翻译：这里公开了具有布置在金属化叠层中的三维电容器的电子部件以及相关的方法和装置。在一些实施例中，例如，电子部件可以包括：设置在金属化叠层中的金属化叠层和电容器，其中电容器包括具有多个凹槽的第一导电板和具有多个凸起的第二导电板，其中多个突起的单个突起延伸到多个凹槽的对应的单个凹槽中而不接触第一导电板。

2. 发明申请

WO2017105502A1 VERTICAL WIRE CONNECTIONS FOR INTEGRATED CIRCUIT PACKAGE 审中-公开
标题翻译：垂直导线连接集成电路封装
公开(公告)号：WO2017105502A1
公开(公告)日：2017-06-22
申请号：PCT/US2015/066766
申请日：2015-12-18
申请人： INTEL IP CORPORATION , GEISSLER, Christian , ALBERS, Sven
发明人： GEISSLER, Christian , ALBERS, Sven , SEIDEMANN, Georg , WOLTER, Andreas , REINGRUBER, Klaus , WAGNER, Thomas , DITTES, Marc
IPC分类号： H01L25/065 , H01L23/48
CPC分类号： H01L24/85 , H01L23/48 , H01L25/065 , H01L2224/16225 , H01L2224/45015 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45664 , H01L2224/48091 , H01L2224/73204 , H01L2224/85186 , H01L2924/181 , H01L2924/00012 , H01L2924/00014 , H01L2924/20751 , H01L2924/20752
摘要： A method includes aligning a wire with a package body having a contact pad and moving the wire through the package body to form electrical contact with the contact pad.
摘要翻译：一种方法包括将导线与具有接触焊盘的封装体对准并且移动导线穿过封装体以形成与接触焊盘的电接触。

3. 发明申请

WO2017048219A1 ADVANCED NODE COST REDUCTION BY ESD INTERPOSER 审中-公开
标题翻译：先进的节点降低ESD插件
公开(公告)号：WO2017048219A1
公开(公告)日：2017-03-23
申请号：PCT/US2015/049923
申请日：2015-09-14
申请人： INTEL IP CORPORATION
发明人： SEIDEMANN, Georg , GEISSLER, Christian , REINGRUBER, Klaus
IPC分类号： H01L23/60 , H01L27/02
CPC分类号： H01L27/0296 , H01L23/147 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L23/60 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0655 , H01L25/105 , H01L25/18 , H01L27/0255 , H01L28/00 , H01L2224/02166 , H01L2224/02372 , H01L2224/0401 , H01L2224/04042 , H01L2224/05548 , H01L2224/0557 , H01L2224/12105 , H01L2224/13007 , H01L2224/13024 , H01L2224/131 , H01L2224/16145 , H01L2224/16146 , H01L2224/16235 , H01L2224/16237 , H01L2224/16238 , H01L2224/17181 , H01L2224/24137 , H01L2224/32245 , H01L2224/48091 , H01L2224/48106 , H01L2224/48108 , H01L2224/48137 , H01L2224/48145 , H01L2224/48157 , H01L2224/73253 , H01L2224/73265 , H01L2224/81815 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/10253 , H01L2924/10271 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/19107 , H01L2924/014 , H01L2224/45099
摘要： An apparatus including an electrostatic discharge circuit including a first circuit portion coupled beneath a die contact pad of an integrated circuit die and a second circuit portion in an interposer separate from the integrated circuit die, the interposer including a first contact point coupled to the contact pad of the integrated circuit die and a second contact point operable for connection to an external source. A method including forming an integrated circuit die including a first electrostatic discharge structure beneath a contact pad of the die; and coupling the die to an interposer including an interposer contact and a second electrostatic discharge structure, wherein a signal at the contact pad of the die is operable to be routed through the interposer.
摘要翻译：一种包括静电放电电路的装置，包括耦合在集成电路管芯的管芯接触焊盘下方的第一电路部分和与集成电路管芯分开的插入器中的第二电路部分，所述插入器包括耦合到接触焊盘的第一接触点并且可操作用于连接到外部源的第二接触点。一种包括在芯片的接触焊盘下方形成包括第一静电放电结构的集成电路管芯的方法; 以及将所述管芯耦合到包括插入器接触件和第二静电放电结构的插入器，其中所述管芯的接触焊盘处的信号可操作地穿过所述插入件。

4. 发明申请

WO2018063530A1 FLEXIBLE BAND WEARABLE ELECTRONIC DEVICE 审中-公开
标题翻译：柔性带可佩戴电子设备
公开(公告)号：WO2018063530A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/046469
申请日：2017-08-11
申请人： INTEL IP CORPORATION
发明人： ALBERS, Sven , REINGRUBER, Klaus , WOLTER, Andreas , SEIDEMANN, Georg , GEISSLER, Christian , MEYER, Thorsten , OFNER, Gerald
IPC分类号： G06F1/16 , H05K3/46
CPC分类号： G06F1/163 , A44C5/00 , A44C5/02 , A44C5/105 , A45F5/00 , A45F2005/008 , A45F2200/0508 , A61B5/02055 , A61B5/021 , A61B5/02438 , A61B5/1112 , A61B5/681 , A61B2560/0257 , A61B2560/0443 , A61B2562/0219 , G04B37/1486 , G04B47/00 , H04B1/385
摘要： A flexible band wearable electronic device includes a plurality of rigid links. The flexible band wearable electronic device also includes a number of pivot joints coupling the plurality of rigid links together. The flexible band wearable electronic device further includes a first electronic device on a first of the plurality of rigid links, and a second electronic device on a second of the plurality of rigid links. The flexible band wearable electronic device still further includes an electrical communication pathway between first electronic device and the second electronic device and through at least a portion of one of the number of pivot joints.
摘要翻译：柔性带可穿戴电子装置包括多个刚性链接。柔性带可穿戴电子设备还包括将多个刚性连杆连接在一起的多个枢轴接头。柔性带可穿戴电子设备还包括在多个刚性连杆中的第一刚性连杆上的第一电子设备以及在多个刚性连杆中的第二刚性连杆上的第二电子设备。柔性带可穿戴电子设备还进一步包括在第一电子设备和第二电子设备之间并且通过多个枢转关节之一的至少一部分的电通信路径。

5. 发明申请

WO2017109537A1 AN ELECTRICAL DEVICE AND A METHOD FOR FORMING AN ELECTRICAL DEVICE 审中-公开
标题翻译：电气装置和形成电气装置的方法
公开(公告)号：WO2017109537A1
公开(公告)日：2017-06-29
申请号：PCT/IB2015/059833
申请日：2015-12-21
申请人： INTEL IP CORPORATION
发明人： GEISSLER, Christian , ALBERS, Sven , SEIDEMANN, Georg , WOLTER, Andreas , REINGRUBER, Klaus , WAGNER, Thomas , DITTES, Marc
IPC分类号： H01L21/768
CPC分类号： H01L21/768 , H01L23/525 , H01L23/53238 , H01L23/53252
摘要： An electrical device includes a redistribution layer structure, an inter-diffusing material contact structure and a vertical electrically conductive structure located between the redistribution layer structure and the inter-diffusing material contact structure. The vertical electrically conductive structure includes a diffusion barrier structure located adjacently to the inter- diffusing material contact structure. Further, the diffusion barrier structure and the redistribution layer structure comprise different lateral dimensions.
摘要翻译：电气装置包括再分布层结构，内部扩散材料接触结构和位于再分布层结构和内部扩散材料接触结构之间的垂直导电结构。垂直导电结构包括位于相互扩散材料接触结构附近的扩散阻挡结构。此外，扩散阻挡结构和再分配层结构包括不同的横向尺寸。

6. 发明申请

WO2017039630A1 LOW THERMAL RESISTANCE HANGING DIE PACKAGE 审中-公开
标题翻译：低耐热电阻包装
公开(公告)号：WO2017039630A1
公开(公告)日：2017-03-09
申请号：PCT/US2015/047819
申请日：2015-08-31
申请人： INTEL IP CORPORATION
发明人： GEISSLER, Christian , SEIDEMANN, Georg , KOLLER, Sonja , PROSCHWITZ, Jan
IPC分类号： H01L23/34 , H01L23/48
CPC分类号： H01L23/42 , H01L21/563 , H01L23/13 , H01L23/36 , H01L23/49816 , H01L23/49827 , H01L25/0652
摘要： Embodiments herein generally relate to the field of package assembly to facilitate thermal conductivity. A package may have a hanging die, and attach to a printed circuit board (PCB). The package may have an active side plane and an inactive side plane opposite the first active side plane. The package may also have a ball grid array (BGA) matrix having a height determined by a distance of a furthest point of the BGA matrix from the active side plane of the package. The package may have a hanging die attached to the active side plane of the package, the hanging die having a z-height greater than the BGA matrix height. When package is attached to the PCB, the hanging die may fit into an area on the PCB that is recessed or has been cut away, and a thermal conductive material may connect the hanging die and the PCB.
摘要翻译：本文的实施例通常涉及促进导热性的封装组件领域。包装可能有一个悬挂的模具，并附着到印刷电路板（PCB）上。封装可以具有与第一有源侧平面相对的有源侧平面和无效侧平面。封装还可以具有球形栅格阵列（BGA）矩阵，其具有由BGA矩阵的最远点与封装的有源侧平面之间的距离确定的高度。包装可以具有附接到包装的主动侧平面的悬挂模具，悬挂模具具有大于BGA矩阵高度的z高度。当包装连接到PCB上时，悬挂模具可以装配在PCB上凹陷或被切除的区域中，并且导热材料可以连接悬挂模具和PCB。

7. 发明申请

WO2017146848A1 REDISTRIBUTION LAYER LINES 审中-公开
标题翻译：再分配层线
公开(公告)号：WO2017146848A1
公开(公告)日：2017-08-31
申请号：PCT/US2017/014606
申请日：2017-01-23
申请人： INTEL IP CORPORATION
发明人： REINGRUBER, Klaus , ALBERS, Sven , GEISSLER, Christian
IPC分类号： H01L23/498 , H01L23/525 , H01L23/538 , H01L23/00
CPC分类号： H01L23/49838 , H01L21/4846 , H01L24/19 , H01L2224/04105
摘要： Embodiments herein may relate to a package with a dielectric layer having a first face and a second face opposite the first face. A conductive line of a patterned metal redistribution layer (RDL) may be coupled with the second face of the dielectric layer. The line may include a first portion with a first width and a second portion directly coupled to the first portion, the second portion having a second width. The first portion may extend beyond a plane of the second face of the dielectric layer, and the second portion may be positioned between the first face and the second face of the dielectric layer. Other embodiments may be described and/or claimed.
摘要翻译：这里的实施例可以涉及具有介电层的封装，该介电层具有第一面和与第一面相对的第二面。图案化金属再分布层（RDL）的导线可以与介电层的第二面耦合。该线可以包括具有第一宽度的第一部分和直接耦合到第一部分的第二部分，第二部分具有第二宽度。第一部分可以延伸超过介电层的第二面的平面，并且第二部分可以位于介电层的第一面和第二面之间。其他实施例可以被描述和/或要求保护。

8. 发明申请

WO2017108122A1 WAFER LEVEL PACKAGE STRUCTURE WITH INTERNAL CONDUCTIVE LAYER 审中-公开
标题翻译：具有内部导电层的晶片级封装结构
公开(公告)号：WO2017108122A1
公开(公告)日：2017-06-29
申请号：PCT/EP2015/081133
申请日：2015-12-23
申请人： INTEL IP CORPORATION , ALBERS, Sven , REINGRUBER, Klaus , SEIDEMANN, Georg , GEISSLER, Christian , PATTEN, Richard
发明人： ALBERS, Sven , REINGRUBER, Klaus , SEIDEMANN, Georg , GEISSLER, Christian , PATTEN, Richard
IPC分类号： H01L21/56 , H01L23/34 , H01L23/433 , H01L23/552
CPC分类号： H01L24/24 , H01L21/561 , H01L21/568 , H01L23/36 , H01L23/4334 , H01L23/552 , H01L24/82 , H01L24/96 , H01L24/97 , H01L2224/24226 , H01L2224/82005 , H01L2224/9222 , H01L2224/97 , H01L2924/15311 , H01L2924/3025 , H01L2224/82
摘要： An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.
摘要翻译：描述了在再分布层上包括再分布层和半导体管芯的设备。导电层位于半导体管芯上。复合模具位于导电层上。

9. 发明申请

WO2017105498A1 INTERPOSER WITH CONDUCTIVE ROUTING EXPOSED ON SIDEWALLS 审中-公开
标题翻译：具有导电路径的插入器暴露在侧壁上
公开(公告)号：WO2017105498A1
公开(公告)日：2017-06-22
申请号：PCT/US2015/066730
申请日：2015-12-18
申请人： INTEL IP CORPORATION
发明人： REINGRUBER, Klaus , GEISSLER, Christian , SEIDEMANN, Georg , KOLLER, Sonja
IPC分类号： H01L23/12
CPC分类号： H01L23/49827 , H01L23/12 , H01L23/13 , H01L23/49805 , H01L23/49838 , H05K1/183 , H05K3/403 , H05K2201/10378
摘要： An electronic assembly that includes an electronic component; and an interposer that includes a body having upper and lower surfaces and side walls extending between the upper and lower surfaces, the interposer further including conductive routings that are exposed on at least one of the side walls, wherein the electronic component is connected directly to the interposer. The conductive routings are exposed on each side wall and on the upper and lower surfaces. The electronic assembly may further includes a substrate having a cavity such that the interposer is within the cavity, wherein the cavity includes sidewalls and substrate includes conductive traces that are exposed from the sidewalls of the cavity, wherein the conductive traces that are exposed from the sidewalls of the cavity are electrically connected directly to the conductive routings that are exposed on at least one of the side walls of the interposer.
摘要翻译：包括电子组件的电子组件; 以及中介层，其包括主体，所述主体具有上表面和下表面以及在所述上表面和下表面之间延伸的侧壁，所述中介层还包括暴露在所述侧壁中的至少一个上的导电路径，其中所述电子元件直接连接到中介。导电路线暴露在每个侧壁上和上下表面上。所述电子组件还可以包括具有腔的衬底，使得所述介入物在所述腔内，其中所述腔包括侧壁，并且所述衬底包括从所述腔的所述侧壁暴露的导电迹线，其中所述导电迹线从所述侧壁的空腔直接电连接到在中介层的至少一个侧壁上暴露的导电路径。

10. 发明申请

WO2017172226A1 INTEGRATED CIRCUIT PACKAGES INCLUDING AN OPTICAL REDISTRIBUTION LAYER 审中-公开
标题翻译：集成电路封装，包括一个光学再分配层
公开(公告)号：WO2017172226A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/020278
申请日：2017-03-01
申请人： INTEL IP CORPORATION
发明人： SEIDEMANN, Georg , GEISSLER, Christian , ALBERS, Sven , WAGNER, Thomas , DITTES, Marc , REINGRUBER, Klaus , WOLTER, Andreas , PATTEN, Richard
IPC分类号： H01L23/522 , H01L23/00
CPC分类号： G02B6/428 , G02B6/12002 , G02B6/122 , G02B6/1221 , G02B6/132 , G02B6/30 , G02B6/4232 , G02B6/4238 , G02B6/43 , G02B2006/12197
摘要： Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.
摘要翻译：公开了一种封装，其包括具有图案化表面的衬底，所述图案化表面具有光学接触区域，光学再分布层（oDL）特征以及在衬底的图案化表面上延伸并且在其周围的积聚材料 ORDL特征的部分。在一些实施例中，包装包括覆盖ORDL特征的衬垫。在一些实施例中，ORDL特征延伸穿过积聚材料的外表面中的开口并且形成从外表面向外延伸的柱。在一些实施例中，封装包括电再分配层（eRDL）特征，其至少一部分与oDL特征的至少一些部分重叠。在一些实施例中，封装包括耦合到oRDL特征的光纤。

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