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1. 发明申请

WO2017155625A1 ELECTRONIC COMPONENTS HAVING THREE-DIMENSIONAL CAPACITORS IN A METALLIZATION STACK 审中-公开
标题翻译：在金属堆叠中具有三维电容器的电子元件
公开(公告)号：WO2017155625A1
公开(公告)日：2017-09-14
申请号：PCT/US2017/015513
申请日：2017-01-27
申请人： INTEL IP CORPORATION
发明人： REINGRUBER, Klaus , ALBERS, Sven , GEISSLER, Christian
IPC分类号： H01L49/02 , H01L27/08 , H01L23/522 , H01L21/768 , H01L23/00
摘要： Disclosed herein are electronic components having three-dimensional capacitors disposed in a metallization stack, as well as related methods and devices. In some embodiments, for example, an electronic component may include: a metallization stack and a capacitor disposed in the metallization stack wherein the capacitor includes a first conductive plate having a plurality of recesses, and a second conductive plate having a plurality of projections, wherein individual projections of the plurality of projections extend into corresponding individual recesses of the plurality of recesses without contacting the first conductive plate.
摘要翻译：这里公开了具有布置在金属化叠层中的三维电容器的电子部件以及相关的方法和装置。在一些实施例中，例如，电子部件可以包括：设置在金属化叠层中的金属化叠层和电容器，其中电容器包括具有多个凹槽的第一导电板和具有多个凸起的第二导电板，其中多个突起的单个突起延伸到多个凹槽的对应的单个凹槽中而不接触第一导电板。

2. 发明申请

WO2017105502A1 VERTICAL WIRE CONNECTIONS FOR INTEGRATED CIRCUIT PACKAGE 审中-公开
标题翻译：垂直导线连接集成电路封装
公开(公告)号：WO2017105502A1
公开(公告)日：2017-06-22
申请号：PCT/US2015/066766
申请日：2015-12-18
申请人： INTEL IP CORPORATION , GEISSLER, Christian , ALBERS, Sven
发明人： GEISSLER, Christian , ALBERS, Sven , SEIDEMANN, Georg , WOLTER, Andreas , REINGRUBER, Klaus , WAGNER, Thomas , DITTES, Marc
IPC分类号： H01L25/065 , H01L23/48
CPC分类号： H01L24/85 , H01L23/48 , H01L25/065 , H01L2224/16225 , H01L2224/45015 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45664 , H01L2224/48091 , H01L2224/73204 , H01L2224/85186 , H01L2924/181 , H01L2924/00012 , H01L2924/00014 , H01L2924/20751 , H01L2924/20752
摘要： A method includes aligning a wire with a package body having a contact pad and moving the wire through the package body to form electrical contact with the contact pad.
摘要翻译：一种方法包括将导线与具有接触焊盘的封装体对准并且移动导线穿过封装体以形成与接触焊盘的电接触。

3. 发明申请

WO2017095588A1 ELECTRONIC PACKAGE WITH COIL FORMED ON CORE 审中-公开
标题翻译：芯上形成线圈的电子封装
公开(公告)号：WO2017095588A1
公开(公告)日：2017-06-08
申请号：PCT/US2016/060254
申请日：2016-11-03
申请人： INTEL IP CORPORATION
发明人： ALBERS, Sven , REINGRUBER, Klaus , WOLTER, Andreas
IPC分类号： H01F17/00 , H01F17/04
CPC分类号： H01F27/2804 , H01F27/06 , H01F27/24 , H01F2027/065 , H01F2027/2809
摘要： An electronic package that includes a substrate; a first electronic component mounted on one side of the substrate; a second electronic component mounted on an opposing side of the substrate; a core mounted to the substrate, wherein the core extends through the substrate; a first wire electrically attached to at least one of the first electronic component and the substrate, wherein the first wire is wrapped around the core to form a first coil on the one side of the substrate; and a second wire electrically attached to at least one of the second electronic component and the substrate, wherein the second wire is wrapped around the core to form a second coil on the opposing side of the substrate.
摘要翻译：包括衬底的电子封装; 安装在所述基板的一侧上的第一电子部件; 安装在所述基板的相对侧上的第二电子部件; 安装到所述衬底的芯部，其中所述芯部延伸穿过所述衬底; 第一导线，所述第一导线电连接到所述第一电子部件和所述衬底中的至少一个，其中所述第一导线缠绕所述芯以在所述衬底的所述一侧上形成第一线圈; 以及电连接到所述第二电子部件和所述衬底中的至少一个的第二导线，其中所述第二导线缠绕所述芯以在所述衬底的相对侧上形成第二线圈。

4. 发明申请

WO2017048219A1 ADVANCED NODE COST REDUCTION BY ESD INTERPOSER 审中-公开
标题翻译：先进的节点降低ESD插件
公开(公告)号：WO2017048219A1
公开(公告)日：2017-03-23
申请号：PCT/US2015/049923
申请日：2015-09-14
申请人： INTEL IP CORPORATION
发明人： SEIDEMANN, Georg , GEISSLER, Christian , REINGRUBER, Klaus
IPC分类号： H01L23/60 , H01L27/02
CPC分类号： H01L27/0296 , H01L23/147 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L23/60 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0655 , H01L25/105 , H01L25/18 , H01L27/0255 , H01L28/00 , H01L2224/02166 , H01L2224/02372 , H01L2224/0401 , H01L2224/04042 , H01L2224/05548 , H01L2224/0557 , H01L2224/12105 , H01L2224/13007 , H01L2224/13024 , H01L2224/131 , H01L2224/16145 , H01L2224/16146 , H01L2224/16235 , H01L2224/16237 , H01L2224/16238 , H01L2224/17181 , H01L2224/24137 , H01L2224/32245 , H01L2224/48091 , H01L2224/48106 , H01L2224/48108 , H01L2224/48137 , H01L2224/48145 , H01L2224/48157 , H01L2224/73253 , H01L2224/73265 , H01L2224/81815 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/10253 , H01L2924/10271 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/19107 , H01L2924/014 , H01L2224/45099
摘要： An apparatus including an electrostatic discharge circuit including a first circuit portion coupled beneath a die contact pad of an integrated circuit die and a second circuit portion in an interposer separate from the integrated circuit die, the interposer including a first contact point coupled to the contact pad of the integrated circuit die and a second contact point operable for connection to an external source. A method including forming an integrated circuit die including a first electrostatic discharge structure beneath a contact pad of the die; and coupling the die to an interposer including an interposer contact and a second electrostatic discharge structure, wherein a signal at the contact pad of the die is operable to be routed through the interposer.
摘要翻译：一种包括静电放电电路的装置，包括耦合在集成电路管芯的管芯接触焊盘下方的第一电路部分和与集成电路管芯分开的插入器中的第二电路部分，所述插入器包括耦合到接触焊盘的第一接触点并且可操作用于连接到外部源的第二接触点。一种包括在芯片的接触焊盘下方形成包括第一静电放电结构的集成电路管芯的方法; 以及将所述管芯耦合到包括插入器接触件和第二静电放电结构的插入器，其中所述管芯的接触焊盘处的信号可操作地穿过所述插入件。

5. 发明申请

WO2017171696A1 OPTICAL FIBER CONNECTION ON PACKAGE EDGE 审中-公开
标题翻译：包装边上的光纤连接
公开(公告)号：WO2017171696A1
公开(公告)日：2017-10-05
申请号：PCT/US2016/024400
申请日：2016-03-28
申请人： INTEL IP CORPORATION
发明人： ALBERS, Sven , DITTES, Marc , WOLTER, Andreas , REINGRUBER, Klaus , SEIDEMANN, Georg , GEISSLER, Christian , WAGNER, Thomas , PATTEN, Richard
IPC分类号： G02B6/12 , G02B6/30 , G02B6/40
摘要： Embodiments of the disclosure are directed to a chip package that includes a base that includes a redistribution layer; an optical transducer circuit element on the base electrically connected to the redistribution layer; an optical element adjacent to the optical transducer circuit element and at an edge of the base; and an encasement encasing the optical transducer circuit element and a portion of the optical element, wherein one side of the optical element is exposed at an edge of the encasement and at the edge of the printed circuit board.
摘要翻译：本公开的实施例针对一种芯片封装，其包括：包括再分布层的基底; 在基座上的光学换能器电路元件，其电连接到再分布层; 邻近所述光学换能器电路元件且在所述基部的边缘处的光学元件; 以及包围光学换能器电路元件和光学元件的一部分的外壳，其中光学元件的一侧暴露在外壳的边缘和印刷电路板的边缘处。

6. 发明申请

WO2017111836A1 PACKAGE STACKING USING CHIP TO WAFER BONDING 审中-公开
标题翻译：堆叠堆叠使用芯片进行晶圆绑定
公开(公告)号：WO2017111836A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/000394
申请日：2015-12-26
申请人： INTEL IP CORPORATION
发明人： SEIDEMANN, Georg , REINGRUBER, Klaus , GEISSLER, Christian , ALBERS, Sven , WOLTER, Andreas , DITTES, Marc , PATTEN, Richard
IPC分类号： H01L25/065 , H01L23/48
CPC分类号： H01L23/48 , H01L21/561 , H01L21/568 , H01L23/3135 , H01L23/49816 , H01L24/19 , H01L24/20 , H01L24/25 , H01L24/96 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/16235 , H01L2224/16238 , H01L2224/2518 , H01L2224/73259 , H01L2224/81005 , H01L2224/92224 , H01L2224/97 , H01L2225/06524 , H01L2225/06541 , H01L2225/06548 , H01L2924/15311 , H01L2924/18161 , H01L2924/3511 , H01L2224/81
摘要： Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.
摘要翻译：实施例通常涉及使用芯片到晶片键合的封装堆叠。器件的一个实施例包括包含一个或多个半导体管芯，组件或两者的第一堆叠层，第一堆叠层进一步包括第一介电层，第一堆叠层被减薄到第一厚度; 以及一个或多个半导体管芯，部件或两者的第二堆叠层，第二堆叠层进一步包括第二介电层，第二堆叠层被制造在第一堆叠层上。

7. 发明申请

WO2017109536A1 SYSTEM-IN-PACKAGE DEVICES AND METHODS FOR FORMING SYSTEM-IN-PACKAGE DEVICES 审中-公开
标题翻译：用于形成系统封装器件的系统封装器件和方法
公开(公告)号：WO2017109536A1
公开(公告)日：2017-06-29
申请号：PCT/IB2015/059829
申请日：2015-12-21
申请人： INTEL IP CORPORATION
发明人： GEISSLER, Christian , ALBERS, Sven , SEIDEMANN, Georg , WOLTER, Andreas , REINGRUBER, Klaus , WAGNER, Thomas , DITTES, Marc
IPC分类号： H01L25/07 , H01L25/065 , H01L23/48
CPC分类号： H01L23/48 , H01L21/568 , H01L24/19 , H01L24/20 , H01L24/24 , H01L25/065 , H01L25/07 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/18 , H01L2224/24137 , H01L2224/24195 , H01L2924/19105
摘要： A system-in-package device includes at least three electrical device components arranged in a common package. A first electrical device component includes a first vertical dimension, a second electrical device component includes a second vertical dimension and a third electrical device component comprises a third vertical dimension. The first electrical device component and the second electrical device component are arranged side by side in the common package. Further, the third electrical device component is arranged on top of the first electrical device component in the common package. At least a part of the third electrical device component is arranged vertically between a front side level of the second electrical device component and a back side level of the second electrical device component.
摘要翻译：系统级封装器件包括布置在共同封装中的至少三个电子器件组件。第一电气装置部件包括第一竖直尺寸，第二电气装置部件包括第二竖直尺寸并且第三电气装置部件包括第三竖直尺寸。第一电气装置部件和第二电气装置部件并排布置在公共包装中。此外，第三电气装置部件布置在公共封装中的第一电气装置部件的顶部上。第三电气装置部件的至少一部分垂直地布置在第二电气装置部件的前侧水平和第二电气装置部件的后侧水平之间。

8. 发明申请

WO2018063530A1 FLEXIBLE BAND WEARABLE ELECTRONIC DEVICE 审中-公开
标题翻译：柔性带可佩戴电子设备
公开(公告)号：WO2018063530A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/046469
申请日：2017-08-11
申请人： INTEL IP CORPORATION
发明人： ALBERS, Sven , REINGRUBER, Klaus , WOLTER, Andreas , SEIDEMANN, Georg , GEISSLER, Christian , MEYER, Thorsten , OFNER, Gerald
IPC分类号： G06F1/16 , H05K3/46
CPC分类号： G06F1/163 , A44C5/00 , A44C5/02 , A44C5/105 , A45F5/00 , A45F2005/008 , A45F2200/0508 , A61B5/02055 , A61B5/021 , A61B5/02438 , A61B5/1112 , A61B5/681 , A61B2560/0257 , A61B2560/0443 , A61B2562/0219 , G04B37/1486 , G04B47/00 , H04B1/385
摘要： A flexible band wearable electronic device includes a plurality of rigid links. The flexible band wearable electronic device also includes a number of pivot joints coupling the plurality of rigid links together. The flexible band wearable electronic device further includes a first electronic device on a first of the plurality of rigid links, and a second electronic device on a second of the plurality of rigid links. The flexible band wearable electronic device still further includes an electrical communication pathway between first electronic device and the second electronic device and through at least a portion of one of the number of pivot joints.
摘要翻译：柔性带可穿戴电子装置包括多个刚性链接。柔性带可穿戴电子设备还包括将多个刚性连杆连接在一起的多个枢轴接头。柔性带可穿戴电子设备还包括在多个刚性连杆中的第一刚性连杆上的第一电子设备以及在多个刚性连杆中的第二刚性连杆上的第二电子设备。柔性带可穿戴电子设备还进一步包括在第一电子设备和第二电子设备之间并且通过多个枢转关节之一的至少一部分的电通信路径。

9. 发明申请

WO2018063512A1 INTERCONNECT STRUCTURE FOR A MICROELECTRONIC DEVICE 审中-公开
标题翻译：微电子器件的互连结构
公开(公告)号：WO2018063512A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/046027
申请日：2017-08-09
申请人： INTEL IP CORPORATION
发明人： REINGRUBER, Klaus , WOLTER, Andreas , SEIDEMANN, Georg , WAGNER, Thomas , WAIDHAS, Bernd
IPC分类号： H01L25/07 , H01L23/485 , H01L23/535
摘要： A microelectronic package with two semiconductor die coupled on opposite sides of a redistribution layer (108), and at least partially overlapping with one another. At least a first of the semiconductor die includes two sets of contacts, the first group of contacts arranged at a lesser pitch relative to one another than are a second group of contacts. The first group of contacts at the larger pitch are placed to engage contacts in a redistribution layer (108). The second group of contacts at the lesser pitch are placed to engage respective contacts at the same pitch on the second semiconductor die.
摘要翻译：具有耦合在再分布层（108）的相对侧上并且至少部分地彼此重叠的两个半导体管芯的微电子封装。至少第一半导体管芯包括两组触点，第一组触点相对于彼此以比第二组触点更小的间距布置。大间距处的第一组触点被放置成与再分配层（108）中的触点接合。以较小间距的第二组触点被放置成在第二半导体管芯上以相同间距接合相应触点。

10. 发明申请

WO2017171971A1 MICROELECTRONIC PACKAGE WITH ILLUMINATED BACKSIDE EXTERIOR 审中-公开
标题翻译：微电子包装带照明背面外观
公开(公告)号：WO2017171971A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/013060
申请日：2017-01-11
申请人： INTEL IP CORPORATION
发明人： DITTES, Marc Stephan , ALBERS, Sven , GEISSLER, Christian Georg , WOLTER, Andreas , REINGRUBER, Klaus , SEIDEMANN, Georg , WAGNER, Thomas , PATTEN, Richard
IPC分类号： H01L25/075 , H01L25/16 , H01L33/48 , H01L23/04 , H01L23/48 , H01L23/498
摘要： A microelectronic package is described with an illuminated backside exterior. In one example, the package has a package substrate, a die attached to the package substrate, a cover over the die and the package substrate, a lamp, and a screen over the die, externally visible and optically coupled to the lamp so that when the lamp is illuminated the illumination is externally visible through the screen.
摘要翻译：描述了具有照明后侧外部的微电子封装。在一个示例中，封装具有封装衬底，附接到封装衬底的管芯，管芯和封装衬底上的覆盖物，灯以及管芯上方的屏幕，外部可见且光学耦合到灯，使得当灯亮起，照明通过屏幕从外部可见。

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