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1. 发明申请

WO2011162949A2 PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES 审中-公开
标题翻译：平面CAVITY MEMS及相关结构，制造和设计结构的方法
公开(公告)号：WO2011162949A2
公开(公告)日：2011-12-29
申请号：PCT/US2011039560
申请日：2011-06-08
申请人： IBM , DANG DINH , DOAN THAI , DUNBAR GEORGE A , HE ZHONG-XIANG , HERRIN RUSSELL T , JAHNES CHRISTOPHER V , MALING JEFFREY C , MURPHY WILLIAM J , STAMPER ANTHONY K , TWOMBLY JOHN G , WHITE ERIC J
发明人： DANG DINH , DOAN THAI , DUNBAR GEORGE A , HE ZHONG-XIANG , HERRIN RUSSELL T , JAHNES CHRISTOPHER V , MALING JEFFREY C , MURPHY WILLIAM J , STAMPER ANTHONY K , TWOMBLY JOHN G , WHITE ERIC J
IPC分类号： B81B3/00 , B81C1/00 , H01H59/00
CPC分类号： B81C1/00365 , B81B3/0021 , B81B3/0072 , B81B2201/01 , B81B2201/014 , B81B2203/0118 , B81B2203/0315 , B81B2203/04 , B81C1/0015 , B81C1/00476 , B81C1/00619 , B81C1/00626 , B81C1/00666 , B81C2201/0109 , B81C2201/013 , B81C2201/0167 , B81C2201/017 , B81C2203/0136 , B81C2203/0172 , G06F17/5068 , G06F17/5072 , H01H1/0036 , H01H57/00 , H01H59/0009 , H01H2057/006 , H01L41/1136 , H01L2924/0002 , Y10S438/937 , Y10T29/42 , Y10T29/435 , Y10T29/49002 , Y10T29/49105 , Y10T29/49121 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/5313 , H01L2924/00
摘要： Planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structure are provided. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity (60a, 60b) having a planar surface using a reverse damascene process.
摘要翻译：提供了平面腔微机电系统（MEMS）结构，制造方法和设计结构。该方法包括使用反向镶嵌工艺形成具有平面表面的至少一个微机电系统（MEMS）腔（60a，60b）。

2. 发明申请

WO2010017031A1 THROUGH WAFER VIA AND METHOD OF MAKING SAME 审中-公开
标题翻译：通过WAFER方法和制作它的方法
公开(公告)号：WO2010017031A1
公开(公告)日：2010-02-11
申请号：PCT/US2009/051338
申请日：2009-07-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , DING, Hanyi , JOSEPH, Alvin , STAMPER, Anthony
发明人： DING, Hanyi , JOSEPH, Alvin , STAMPER, Anthony
IPC分类号： H01L21/8234 , H01L27/06
CPC分类号： H01L21/76898 , H01L21/6835 , H01L21/6836 , H01L23/481 , H01L25/0657 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , H01L2224/03002 , H01L2224/0401 , H01L2224/04026 , H01L2224/0405 , H01L2224/0557 , H01L2224/06181 , H01L2224/11002 , H01L2224/11003 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/81191 , H01L2224/81192 , H01L2225/06513 , H01L2225/06541 , H01L2924/01068 , H01L2924/1305 , H01L2924/13091 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/00
摘要： A through wafer via structure. The structure includes: a semiconductor substrate (100) having a top surface (105) and an opposite bottom surface (320); and an array of through wafer vias comprising at least one electrically conductive through wafer via (130) and at least one electrically non-conductive through wafer via (125), each through wafer via of the array of through wafer vias extending from the top surface (105) of the substrate (100) to between greater than halfway to and all the way to the bottom surface (320) of the substrate (100). Also methods for fabricating the though wafer via structure.
摘要翻译：通过晶片通孔结构。该结构包括：具有顶表面（105）和相对的底表面（320）的半导体衬底（100）; 以及包括至少一个导电的通过晶片通孔（130）和至少一个非导电的通过晶片通孔（125）的穿过晶片通孔的阵列，每个通过晶片通孔阵列的晶片通孔从顶表面（100）的底表面（105）之间的距离大于中间到所述基底（100）的底表面（320）的距离。也是用于制造晶片通孔结构的方法。

3. 发明申请

WO2008091923A3 REMOVAL OF ETCHING PROCESS RESIDUAL IN SEMICONDUCTOR FABRICATION 审中-公开
标题翻译：在半导体制造中去除蚀刻工艺残留
公开(公告)号：WO2008091923A3
公开(公告)日：2009-12-30
申请号：PCT/US2008051758
申请日：2008-01-23
申请人： IBM , HERRIN RUSSELL T , LINDGREN PETER J , STAMPER ANTHONY K
发明人： HERRIN RUSSELL T , LINDGREN PETER J , STAMPER ANTHONY K
IPC分类号： C11D7/00
CPC分类号： H01L23/5223 , H01L21/02063 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and methods for forming the same. A semiconductor fabrication method includes steps of providing a structure. A structure incl udes (a) a dielectric layer, (b) a first electrically conductive region buried in the dielectric layer, wherein the first electrically conductive region comprises a first electrically conductive material, and (c) a second electrically conductive region buried in the dielectric layer, wherein the second electrically conductive region comprises a second electrically conductive material being different from the first electrically conductive material. The method further includes the steps of creating a first hole and a second hole in the dielectric layer resulting in the first and second electrically conductive regions being exposed to a surrounding ambient through the first and second holes, respectively. Then, the method further includes the steps of introducing a basic solvent to bottom walls and side walls of the first and second holes.
摘要翻译：半导体结构及其形成方法。半导体制造方法包括提供结构的步骤。一种结构包括（a）介电层，（b）掩埋在所述电介质层中的第一导电区域，其中所述第一导电区域包括第一导电材料，和（c）第二导电区域，介电层，其中第二导电区域包括不同于第一导电材料的第二导电材料。该方法还包括以下步骤：在电介质层中形成第一孔和第二孔，导致第一和第二导电区域分别通过第一孔和第二孔暴露于周围环境。然后，该方法还包括将碱性溶剂引入第一孔和第二孔的底壁和侧壁的步骤。

4. 发明申请

WO2009137313A1 THROUGH SUBSTRATE VIA INCLUDING VARIABLE SIDEWALL PROFILE 审中-公开
标题翻译：通过基础包括可变的平台轮廓
公开(公告)号：WO2009137313A1
公开(公告)日：2009-11-12
申请号：PCT/US2009/042206
申请日：2009-04-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , COONEY, Edward, Crandal , LINDGREN, Peter, James , OSSENKOP, Dorreen, Jane , STAMPER, Anthony, Kendall
发明人： COONEY, Edward, Crandal , LINDGREN, Peter, James , OSSENKOP, Dorreen, Jane , STAMPER, Anthony, Kendall
IPC分类号： H01L21/441 , H01L29/417
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic structure, such as a semiconductor structure, and a method for fabricating the microelectronic structure, include an aperture (R1-RA) within a substrate. (16) Into the aperture is located and formed a via. The via may include a through substrate via. The aperture includes, progressing sequentially contiguously at least partially through the substrate: (1) a first comparatively wide region (R1) at a surface of the substrate; (2) a constricted region contiguous (R2) with the first comparatively wide region; (3) a second comparatively wide region contiguous (R3) with the constricted region; and (4) a tapered region contiguous (R4) with the second comparatively wide region. The structure of the aperture provides for ease in filling the aperture, as well as void isolation within the via.
摘要翻译：诸如半导体结构的微电子结构和用于制造微电子结构的方法包括在衬底内的孔（R1-RA）。（16）进入孔位于并形成通孔。通孔可以包括通孔基板通孔。所述孔包括，至少部分地依次连续地进行穿过所述基底：（1）在所述基底的表面处的第一相对较宽的区域（R1）（2）具有第一相对较宽区域的收缩区域连续（R2）; （3）与收缩区域相邻的第二相对宽的区域（R3）; 和（4）与第二较宽区域连续的（R4）的锥形区域。孔的结构提供了填充孔的容易性以及通孔内的空隙隔离。

5. 发明申请

WO2007131867B1 DUAL WIRED INTEGRATED CIRCUIT CHIPS 审中-公开
标题翻译：双线集成电路板
公开(公告)号：WO2007131867B1
公开(公告)日：2008-03-06
申请号：PCT/EP2007054077
申请日：2007-04-25
申请人： IBM , IBM UK , JAFFE MARK DAVID , DALTON TIMOTHY JOSEPH , GAMBINO JEFFREY PETER , KARTSCHOKE PAUL DAVID , STAMPER ANTHONY KENDALL , BERNSTEIN KERRY
发明人： JAFFE MARK DAVID , DALTON TIMOTHY JOSEPH , GAMBINO JEFFREY PETER , KARTSCHOKE PAUL DAVID , STAMPER ANTHONY KENDALL , BERNSTEIN KERRY
IPC分类号： H01L21/768 , H01L27/12
CPC分类号： H01L21/76898 , H01L21/768 , H01L21/84 , H01L23/481 , H01L23/522 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.
摘要翻译：具有相对侧的布线电平的半导体器件以及制造与相对侧的器件和布线电平接触的半导体结构的方法。该方法包括在绝缘体上硅衬底上制造器件，其中器件的第一接触和第一侧的第一接触处的布线电平，去除下硅层以暴露所述掩埋氧化物层，形成第二触点到器件通过掩埋氧化物层形成掩埋氧化物层上方的布线电平到第二触点。

6. 发明申请

WO2007084879A3 LOW RESISTANCE AND INDUCTANCE BACKSIDE THROUGH VIAS AND METHODS OF FABRICATING SAME 审中-公开
标题翻译：通过VIAS的低电阻和电感及其制造方法
公开(公告)号：WO2007084879A3
公开(公告)日：2008-02-21
申请号：PCT/US2007060544
申请日：2007-01-15
申请人： IBM , ERTURK METE , GROVES ROBERT A , JOHNSON JEFFREY B , JOSEPH ALVIN J , LIU QIZHI , SPROGIS EDMUND J , STAMPER ANTHONY K
发明人： ERTURK METE , GROVES ROBERT A , JOHNSON JEFFREY B , JOSEPH ALVIN J , LIU QIZHI , SPROGIS EDMUND J , STAMPER ANTHONY K
IPC分类号： H01L21/00 , H01L21/302 , H01L21/306 , H01L21/44 , H01L21/77
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation (250) in a substrate (100), the substrate (100) having a frontside and an opposing backside; forming a first dielectric layer (105) on the frontside of the substrate (100); forming a trench (265C) in the first dielectric layer (105), the trench (265C) aligned over and within a perimeter of the dielectric isolation (250) and extending to the dielectric isolation (250); extending the trench (265C) formed in the first dielectric layer (1 05) through the dielectric isolation (250) and into the substrate (1 00)to a depth (Dl ) less than a thickness of the substrate (1 00); filling the trench (265C) and co-planarizing a top surface of the trench (265C) with a top surface of the first dielectric layer (1 05) to form an electrically conductive through via (270C); and thinning the substrate (100) from a backside of the substrate (100) to expose the through via (270C).
摘要翻译：背面接触结构及其制造方法。该方法包括：在衬底（100）中形成绝缘隔离（250），所述衬底（100）具有前侧和相对的背面; 在所述基板（100）的前侧形成第一介电层（105）; 在所述第一电介质层（105）中形成沟槽（265C），所述沟槽（265C）在所述电介质隔离（250）的周边内并且在所述绝缘隔离（250）的周边内并且延伸到所述电介质隔离（250）; 将形成在第一电介质层（105）中的沟槽（265C）延伸通过电介质隔离（250）并延伸到衬底（100）中至小于衬底厚度（001）的深度（D1）。填充沟槽（265C）并且将沟槽（265C）的顶表面与第一介电层（105）的顶表面共平面化以形成导电通孔（270C）; 以及从所述衬底（100）的背面使所述衬底（100）变薄以暴露所述通孔（270C）。

7. 发明申请

WO2007137049A2 DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS 审中-公开
标题翻译：双面集成电路板
公开(公告)号：WO2007137049A2
公开(公告)日：2007-11-29
申请号：PCT/US2007/069002
申请日：2007-05-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , BERNSTEIN, Kerry , DALTON, Timothy, Joseph , GAMBINO, Jeffrey, Peter , JAFFE, Mark, David , KARTSCHOKE, Paul, David , LUCE, Stephen, Ellinwood , STAMPER, Anthony, Kendall
发明人： BERNSTEIN, Kerry , DALTON, Timothy, Joseph , GAMBINO, Jeffrey, Peter , JAFFE, Mark, David , KARTSCHOKE, Paul, David , LUCE, Stephen, Ellinwood , STAMPER, Anthony, Kendall
IPC分类号： H01L23/52 , H01L21/44
CPC分类号： H01L25/0657 , H01L21/76895 , H01L23/481 , H01L23/522 , H01L23/5329 , H01L25/50 , H01L27/0688 , H01L2225/06513 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon (110A and 110B) from two silicon-on- insulator wafers (110A and 100B), respectively, having devices (130A and 130B), respectively, fabricated therein and bonding them back to back utilizing the buried oxide layers (115). Contacts (210) are then formed in the upper wafer (I00B) to devices (130A) in the lower wafer (100A) and wiring levels (170) are formed on the upper wafer (100B). The lower wafer (100A) may include wiring levels (170). The lower wafer (100A) may include landing pads (230) for the contacts. Contacts to the silicon layer (120) of the lower wafer (100A) may be silicided.
摘要翻译：一种半导体结构及其制造方法。该方法包括从分别制造在其中的器件（130A和130B）的两个绝缘体上硅晶片（110A和100B）去除后侧硅（110A和110B），并使用掩埋氧化物层（115）。接触件（210）然后在上晶片（I00B）中形成到下晶片（100A）中的器件（130A），并且布线级（170）形成在上晶片（100B）上。下晶片（100A）可以包括布线层（170）。下晶片（100A）可以包括用于触点的着陆焊盘（230）。与下晶片（100A）的硅层（120）的接触可以被硅化。

8. 发明申请

WO2007084982A2 DUAL-DAMASCENE PROCESS TO FABRICATE THICK WIRE STRUCTURE 审中-公开
标题翻译：双镶嵌法制作厚丝结构
公开(公告)号：WO2007084982A2
公开(公告)日：2007-07-26
申请号：PCT/US2007060767
申请日：2007-01-19
申请人： IBM , COOLBAUGH DOUGLAS D , DOWNES KEITH E , LINDGREN PETER J , STAMPER ANTHONY K
发明人： COOLBAUGH DOUGLAS D , DOWNES KEITH E , LINDGREN PETER J , STAMPER ANTHONY K
IPC分类号： H01L21/8242 , H01L21/20 , H01L21/302 , H01L21/4763
CPC分类号： H01L23/481 , H01L21/76808 , H01L21/76813 , H01L21/76832 , H01L23/5223 , H01L28/60 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要： A method and semiconductor device. In the method, at least one partial via (26) is etched in a stacked structure and a border (32) is formed about the at least one partial via (26). The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer (22).
摘要翻译：一种方法和半导体器件。在该方法中，在堆叠结构中蚀刻至少一个部分通孔（26），并且围绕至少一个部分通孔（26）形成边界（32）。该方法进一步包括使用选择性蚀刻执行厚布线，同时经由蚀刻继续至少一个蚀刻停止层（22）。

9. 发明申请

WO2013012544A1 SAW FILTER HAVING PLANAR BARRIER LAYER AND METHOD OF MAKING 审中-公开
标题翻译：具有平面屏障层的SAW滤波器及其制造方法
公开(公告)号：WO2013012544A1
公开(公告)日：2013-01-24
申请号：PCT/US2012/044908
申请日：2012-06-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ADKISSON, James, W. , CANDRA, Panglijen , DUNBAR, Thomas, J. , GAMBINO, Jeffrey, P. , JAFFE, Mark, D. , STAMPER, Anthony, K. , WOLF, Randy, L.
发明人： ADKISSON, James, W. , CANDRA, Panglijen , DUNBAR, Thomas, J. , GAMBINO, Jeffrey, P. , JAFFE, Mark, D. , STAMPER, Anthony, K. , WOLF, Randy, L.
IPC分类号： H03H9/64
CPC分类号： H03H9/14538 , H03H3/08
摘要： Disclosed herein is a surface acoustic wave (SAW) filter and method of making the same. The SAW filter includes a piezoelectric substrate (110; Fig 3); a planar barrier layer (120) disposed above the piezoelectric substrate, and at least one conductor buried (130) in the piezoelectric substrate and the planar barrier layer.
摘要翻译：本文公开了一种表面声波（SAW）滤波器及其制造方法。 SAW滤波器包括压电基片（110;图3）; 设置在所述压电基板上方的平面阻挡层（120），以及在所述压电基板和所述平面阻挡层中埋设的至少一个导体（130）。

10. 发明申请

WO2012177304A2 MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) AND RELATED ACTUATOR BUMPS, METHOD OF MANUFACTURE AND DESIGN STRUCTURES 审中-公开
标题翻译：微电子机械系统（MEMS）及相关执行机构的制造，制造和设计结构的方法
公开(公告)号：WO2012177304A2
公开(公告)日：2012-12-27
申请号：PCT/US2012/029005
申请日：2012-03-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , JAHNES, Christopher, V. , STAMPER, Anthony, K.
发明人： JAHNES, Christopher, V. , STAMPER, Anthony, K.
IPC分类号： H02N1/00 , H05K13/00
CPC分类号： H01H59/0009 , B81B3/001 , B81B7/0006 , B81B2201/016 , B81B2203/0118 , B81B2203/04 , B81C1/0015 , B81C1/00293 , B81C2203/0145 , G06F17/5045 , G06F17/5068 , H01H1/0036 , H01H2001/0057 , Y10T29/49121
摘要： Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are provided. The method of forming a MEMS structure includes forming fixed actuator electrodes (115) and a contact point on a substrate. The method further includes forming a MEMS beam (100) over the fixed actuator electrodes and the contact point. The method further includes forming an array of actuator electrodes (105') in alignment with portions of the fixed actuator electrodes, which are sized and dimensioned to prevent the MEMS beam from collapsing on the fixed actuator electrodes after repeating cycling. The array of actuator electrodes are formed in direct contact with at least one of an underside of the MEMS beam and a surface of the fixed actuator electrodes.
摘要翻译：提供微机电系统（MEMS）结构，制造方法和设计结构。形成MEMS结构的方法包括在基板上形成固定的致动器电极（115）和接触点。该方法还包括在固定的致动器电极和接触点上形成MEMS光束（100）。该方法还包括形成与固定致动器电极的部分对准的致动器电极阵列（105'），其尺寸和尺寸被确定为防止MEMS梁在重复循环之后塌陷在固定的致动器电极上。致动器电极阵列形成为与MEMS光束的下侧和固定致动器电极的表面中的至少一个直接接触。

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