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1. 发明申请

WO2007084879A3 LOW RESISTANCE AND INDUCTANCE BACKSIDE THROUGH VIAS AND METHODS OF FABRICATING SAME 审中-公开
标题翻译：通过VIAS的低电阻和电感及其制造方法
公开(公告)号：WO2007084879A3
公开(公告)日：2008-02-21
申请号：PCT/US2007060544
申请日：2007-01-15
申请人： IBM , ERTURK METE , GROVES ROBERT A , JOHNSON JEFFREY B , JOSEPH ALVIN J , LIU QIZHI , SPROGIS EDMUND J , STAMPER ANTHONY K
发明人： ERTURK METE , GROVES ROBERT A , JOHNSON JEFFREY B , JOSEPH ALVIN J , LIU QIZHI , SPROGIS EDMUND J , STAMPER ANTHONY K
IPC分类号： H01L21/00 , H01L21/302 , H01L21/306 , H01L21/44 , H01L21/77
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation (250) in a substrate (100), the substrate (100) having a frontside and an opposing backside; forming a first dielectric layer (105) on the frontside of the substrate (100); forming a trench (265C) in the first dielectric layer (105), the trench (265C) aligned over and within a perimeter of the dielectric isolation (250) and extending to the dielectric isolation (250); extending the trench (265C) formed in the first dielectric layer (1 05) through the dielectric isolation (250) and into the substrate (1 00)to a depth (Dl ) less than a thickness of the substrate (1 00); filling the trench (265C) and co-planarizing a top surface of the trench (265C) with a top surface of the first dielectric layer (1 05) to form an electrically conductive through via (270C); and thinning the substrate (100) from a backside of the substrate (100) to expose the through via (270C).
摘要翻译：背面接触结构及其制造方法。该方法包括：在衬底（100）中形成绝缘隔离（250），所述衬底（100）具有前侧和相对的背面; 在所述基板（100）的前侧形成第一介电层（105）; 在所述第一电介质层（105）中形成沟槽（265C），所述沟槽（265C）在所述电介质隔离（250）的周边内并且在所述绝缘隔离（250）的周边内并且延伸到所述电介质隔离（250）; 将形成在第一电介质层（105）中的沟槽（265C）延伸通过电介质隔离（250）并延伸到衬底（100）中至小于衬底厚度（001）的深度（D1）。填充沟槽（265C）并且将沟槽（265C）的顶表面与第一介电层（105）的顶表面共平面化以形成导电通孔（270C）; 以及从所述衬底（100）的背面使所述衬底（100）变薄以暴露所述通孔（270C）。

2. 发明申请

WO2006034355A2 METHOD OF COLLECTOR FORMATION IN BiCMOS TECHNOLOGY 审中-公开
标题翻译： BiCMOS技术中收集物形成的方法
公开(公告)号：WO2006034355A2
公开(公告)日：2006-03-30
申请号：PCT/US2005033851
申请日：2005-09-20
申请人： IBM , GEISS PETER J , GRAY PETER B , JOSEPH ALVIN J , LIU QIZHI
发明人： GEISS PETER J , GRAY PETER B , JOSEPH ALVIN J , LIU QIZHI
IPC分类号： H01L31/109
CPC分类号： H01L29/0821 , H01L21/8249 , H01L27/0623 , H01L29/66242 , H01L29/66318
摘要： A heterobipolar transistor (HBT) for high-speed BiCMOS applications is provided in which the collector resistance, Rc, is lowered by providing a buried refractory metal silicide layer underneath the shallow trench isolation region on the subcollector of the device. Specifically, the HBT of the present invention includes a substrate (12) including at least a subcollector (13); a buried refractory metal silicide layer (28) located on the subcollector; and a shallow trench isolation region (30) located on a surface of the buried refractory metal silicide layer. The present invention also provides a method of fabricating such a HBT. The method includes forming a buried refractory metal silicide underneath the shallow trench isolation region on the subcollector of the device.
摘要翻译：提供了用于高速BiCMOS应用的异步双极晶体管（HBT），其中通过在器件的子集电极上的浅沟槽隔离区域的下面提供掩埋难熔金属硅化物层来降低集电极电阻Rc。具体地，本发明的HBT包括至少包括子集电极（13）的基板（12）。位于子集电极上的埋置难熔金属硅化物层（28）; 以及位于所述埋入难熔金属硅化物层的表面上的浅沟槽隔离区域（30）。本发明还提供一种制造这种HBT的方法。该方法包括在器件的子集电极上的浅沟槽隔离区域的下面形成埋置难熔金属硅化物。

3. 发明申请

WO2013006277A2 BIPOLAR JUNCTION TRANSISTORS WITH A LINK REGION CONNECTING THE INTRINSIC AND EXTRINSIC BASES 审中-公开
标题翻译：具有连接本地和特殊基础的连接区域的双极性连接晶体管
公开(公告)号：WO2013006277A2
公开(公告)日：2013-01-10
申请号：PCT/US2012043443
申请日：2012-06-21
申请人： IBM , CAMILLO-CASTILLO RENATA , GRAY PETER B , HARAME DAVID L , JOSEPH ALVIN J , KHATER MARWAN H , LIU QIZHI
发明人： CAMILLO-CASTILLO RENATA , GRAY PETER B , HARAME DAVID L , JOSEPH ALVIN J , KHATER MARWAN H , LIU QIZHI
CPC分类号： H01L29/73 , H01L21/8249 , H01L27/0623 , H01L29/0821 , H01L29/107 , H01L29/66272 , H01L29/7322
摘要： Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor (80) includes a dielectric layer (32) on an intrinsic base (84) and an extrinsic base (82) at least partially separated from the intrinsic base by the dielectric layer. An emitter opening (52) extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity (60a, 60b) between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer (64) that physically links the extrinsic base and the intrinsic base together.
摘要翻译：用于制造双极结晶体管的方法，通过该方法制造的双极结型晶体管以及双极结型晶体管的设计结构。双极结晶体管（80）包括在本征基极（84）上的介电层（32）和通过介电层至少部分地与本征基极分离的外部基极（82）。发射极开口（52）延伸穿过外部基极和电介质层。电介质层相对于发射极开口横向凹入以限定内部基极和外部基极之间的空腔（60a，60b）。空腔填充有将外部基极和固有基底物理连接在一起的半导体层（64）。

4. 发明申请

WO2005024900A3 BIPOLAR TRANSISTOR HAVING RAISED EXTRINSIC BASE WITH SELECTABLE SELF-ALIGNMENT AND METHODS OF FORMING SAME 审中-公开
标题翻译：具有可选择的自对准的提升的超级基座的双极晶体管及其形成方法
公开(公告)号：WO2005024900A3
公开(公告)日：2005-06-09
申请号：PCT/US2004021345
申请日：2004-07-01
申请人： IBM , KHATER MARWAN H , DUNN JAMES S , HARAME DAVID L , JOSEPH ALVIN J , LIU QIZHI , PAGETTE FRANCOIS , ST ONGE STEPHEN A , STRICKER ANDREAS D
发明人： KHATER MARWAN H , DUNN JAMES S , HARAME DAVID L , JOSEPH ALVIN J , LIU QIZHI , PAGETTE FRANCOIS , ST ONGE STEPHEN A , STRICKER ANDREAS D
IPC分类号： H01L21/331 , H01L29/10 , H01L29/732 , H01L29/737 , H01L23/62
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/66242 , H01L29/732 , H01L29/7378
摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter (106) is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer (102) of polysilicon or silicon on an intrinsic base (108). A dielectric landing pad (128) is then formed by lithography on the first extrinsic base layer (102). Next, a second extrinsic base layer (104) of polysilicon or silicon is formed on top of the dielectric landing pad (128) to finalize the raised extrinsic base total thickness. An emitter (106) opening is formed using lithography and RIE, where the second extrinsic base layer (104) is etched stopping on the dielectric landing pad (128). The degree of self-alignment between the emitter (106) and the raised extrinsic base is achieved by selecting the first extrinsic base layer (102) thickness, the dielectric landing pad (128) width, and the spacer width.
摘要翻译：公开了一种具有凸起的非本征基极和在本征基极和发射极（106）之间的可选自对准的双极晶体管。制造方法可以包括在内在基极（108）上形成多晶硅或硅的第一非本征基极层（102）的预定厚度。然后通过光刻在第一非本征基极层（102）上形成电介质着色焊盘（128）。接下来，在电介质着色焊盘（128）的顶部上形成多晶硅或硅的第二非本征基极层（104），以最终确定凸出的非本征基本总厚度。使用光刻和RIE形成发射器（106）开口，其中第二外部基极层（104）被蚀刻停止在电介质着色焊盘（128）上。通过选择第一非本征基极层（102）的厚度，电介质着陆焊盘（128）的宽度和间隔物宽度来实现发射极（106）和凸起的外在基极之间的自对准程度。

5. 发明申请

WO2005004201A3 BIPOLAR TRANSISTOR AND METHOD OF MAKING SAME 审中-公开
标题翻译：双极晶体管及其制造方法
公开(公告)号：WO2005004201A3
公开(公告)日：2005-05-12
申请号：PCT/US2004019906
申请日：2004-06-22
申请人： IBM , JOSEPH ALVIN J , LIU QIZHI
发明人： JOSEPH ALVIN J , LIU QIZHI
IPC分类号： H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/10 , H01L29/732 , H01L21/8222 , H01L27/082
CPC分类号： H01L29/66287 , H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L29/732
摘要： A high fT and fmax bipolar transistor (100) includes an emitter (104), a base (120), and a collector (116). The emitter has a lower portion (108) and an upper portion (1.12) that extends beyond the lower portion. The base includes an intrinsic base (140) and an extrinsic base (144). The intrinsic base is located between the lower portion of the emitter and the collector. The extrinsic base extends from the lower portion of the emitter beyond the upper portion of the emitter and includes a continuous conductor (148) that extends from underneath the upper portion of the emitter and out from underneath the upper portion of the emitter. The continuous conductor provides a low electrical resistance path from a base contact (not shown) to the intrinsic base. The transistor may include a second conductor (152) that does not extend underneath the upper portion of the emitter, but which further reduces the electrical resistance through the extrinsic base.
摘要翻译：高fT和fmax双极晶体管（100）包括发射极（104），基极（120）和集电极（116）。发射器具有延伸超出下部的下部（108）和上部（1.12）。基底包括本征基（140）和外基（144）。本征基极位于发射极的下部和集电极之间。外部基极从发射器的下部延伸超过发射器的上部，并且包括从发射器的上部下方延伸并从发射器的上部下方延伸的连续导体（148）。连续导体提供从底部触点（未示出）到本征基极的低电阻路径。晶体管可以包括第二导体（152），其不延伸在发射极的上部下方，但是通过外部基极进一步减小电阻。

6. 发明申请

WO2005104680A3 A METHOD OF BASE FORMATION IN A BICMOS PROCESS 审中-公开
标题翻译： BICMOS过程中基因形成的方法
公开(公告)号：WO2005104680A3
公开(公告)日：2007-07-05
申请号：PCT/US2005011711
申请日：2005-04-06
申请人： IBM , GEISS PETER J , JOSEPH ALVIN J , LIU QZHI , ORNER BRADLEY A
发明人： GEISS PETER J , JOSEPH ALVIN J , LIU QZHI , ORNER BRADLEY A
IPC分类号： H01L31/072 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/10
CPC分类号： H01L29/0804 , H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L29/66287
摘要： Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector (112), an intrinsic base (118) above the collector, shallow trench isolation regions (114) adjacent the collector, a raised extrinsic base (202) above the intrinsic base, a T-shaped emitter (800) above the extrinsic base, spacers (700) adjacent the emitter, and a silicide (400) layer that is separated from the emitter by the spacers.
摘要翻译：公开了一种双极互补金属氧化物半导体（BiCMOS）或NPN / PNP器件，其具有集电极（112），集电极上方的本征基极（118），与集电极相邻的浅沟槽隔离区域（114），凸起的外部基极 202），在外部基极之上的T形发射极（800），与发射极相邻的间隔物（700）以及通过间隔物与发射极分离的硅化物（400）层。

7. 发明申请

WO2011066035A3 SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS, DESIGN STRUCTURE AND METHOD 审中-公开
标题翻译：用于降低谐波的硅绝缘体（SOI）结构，设计结构和方法
公开(公告)号：WO2011066035A3
公开(公告)日：2011-07-28
申请号：PCT/US2010050805
申请日：2010-09-30
申请人： IBM , BOTULA ALAN B , ELLIS-MONAGHAN JOHN J , JOSEPH ALVIN J , LEVY MAX G , PHELPS RICHARD A , SLINKMAN JAMES A
发明人： BOTULA ALAN B , ELLIS-MONAGHAN JOHN J , JOSEPH ALVIN J , LEVY MAX G , PHELPS RICHARD A , SLINKMAN JAMES A
IPC分类号： H01L27/12
CPC分类号： H01L29/78603 , H01L21/84 , H01L27/1203
摘要： Disclosed is semiconductor structure (100) with an insulator layer (120) on a semiconductor substrate (110) and a device layer (130) is on the insulator layer. The substrate (110) is doped with a relatively low dose of a dopant (111) having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion (102) of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant (111), a different dopant (112) having the same conductivity type or a combination thereof (111 and 112). Optionally, micro-cavities (122, 123) are created within this same portion (102) so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.
摘要翻译：公开了在半导体衬底（110）上具有绝缘体层（120）并且器件层（130）位于绝缘体层上的半导体结构（100）。衬底（110）掺杂有相对低剂量的具有给定导电类型的掺杂剂（111），使得其具有相对高的电阻率。此外，紧邻绝缘体层的半导体衬底的一部分（102）可以用稍高剂量的相同掺杂剂（111），具有相同导电类型的不同掺杂剂（112）或其组合（111 和112）。可选地，在该相同部分（102）内形成微腔（122,123），以平衡电导率的任何增加以及电阻率的相应增加。增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度提高了任何得到的寄生电容器的阈值电压（Vt），从而降低了谐波行为。在此还公开了用于这种半导体结构的方法和设计结构的实施例。

8. 发明申请

WO2011028385A3 METHOD, STRUCTURE, AND DESIGN STRUCTURE FOR A THROUGH-SILICON-VIA WILKINSON POWER DIVIDER 审中-公开
标题翻译：通硅威威尔金森功分器的方法，结构和设计结构
公开(公告)号：WO2011028385A3
公开(公告)日：2011-06-23
申请号：PCT/US2010045249
申请日：2010-08-12
申请人： IBM , DING HANYI , JOSEPH ALVIN J , WOODS WAYNE H
发明人： DING HANYI , JOSEPH ALVIN J , WOODS WAYNE H
IPC分类号： H01P5/12
CPC分类号： G06F17/5077 , H01L23/481 , H01L2924/0002 , H01L2924/3011 , H01P5/16 , H01P11/007 , H01L2924/00
摘要： A method, structure, and design structure for a through-silicon- via Wilkinson power divider (100). A method includes: forming an input (105) on a first side of a substrate(200); forming a first leg (110a) comprising a first through-silicon- via (120a) formed in the substrate, wherein the first leg electrically connects the input and a first output (115a); forming a second leg (110b) comprising a second through-silicon- via (120b) formed in the substrate, wherein the second leg electrically connects the input and a second output (115b), and forming a resistor (125) electrically connected between the first output and the second output.
摘要翻译：通过威尔金森功率分配器（100）的硅通孔的方法，结构和设计结构。一种方法包括：在衬底（200）的第一侧上形成输入（105）; 形成包括形成在所述衬底中的第一硅通孔（120a）的第一腿（110a），其中所述第一腿电连接所述输入和第一输出（115a）; 形成包括形成在所述衬底中的第二硅通孔（120b）的第二腿（110b），其中所述第二腿电连接所述输入和第二输出（115b），并且形成电连接在所述第一硅通孔第一个输出和第二个输出。

9. 发明申请

WO2011008359A3 SCALING OF BIPOLAR TRANSISTORS 审中-公开
标题翻译：双极晶体管的放大
公开(公告)号：WO2011008359A3
公开(公告)日：2011-03-10
申请号：PCT/US2010037149
申请日：2010-06-03
申请人： IBM , JOSEPH ALVIN J , MALLADI RAMANA M , SLINKMAN JAMES A
发明人： JOSEPH ALVIN J , MALLADI RAMANA M , SLINKMAN JAMES A
IPC分类号： H01L21/331 , H01L29/73
CPC分类号： H01L29/66272 , G06F17/5009 , G06F17/5036 , G06F17/5068 , G06F2217/12 , H01L21/02532 , H01L21/02595 , H01L21/31111 , H01L21/76224 , H01L21/76229 , H01L21/76232 , H01L21/8249 , H01L27/0207 , H01L29/7322 , Y02P90/265
摘要： Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor (240 of FIG. 18); scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor (245); determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling (250); and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design (255) to generate a stress compensated scaled design of the bipolar transistor (260).
摘要翻译：双极晶体管结构，双极晶体管的设计和制造方法，设计具有双极晶体管的电路的方法。设计双极晶体管的方法包括：选择双极晶体管（图18的240）的初始设计; 缩放双极晶体管的初始设计以产生双极晶体管（245）的缩放设计; 确定在缩放之后双极晶体管的发射极的尺寸（250）是否需要双极晶体管的缩放设计的应力补偿; 并且如果需要对双极晶体管的缩放设计的应力补偿，则调整缩放设计的沟槽隔离布局级别相对于缩放设计（255）的发射器布局级别的布局的布局，以产生应力补偿缩放双极晶体管（260）的设计。

10. 发明申请

WO2014077936A3 COMPENSATION FOR A CHARGE IN A SILICON SUBSTRATE 审中-公开
标题翻译：补偿硅衬底中的电荷
公开(公告)号：WO2014077936A3
公开(公告)日：2014-07-24
申请号：PCT/US2013057962
申请日：2013-09-04
申请人： IBM
发明人： BOTULA ALAN B , JAFFE MARK D , JOSEPH ALVIN J , PHELPS RICHARD A , SLINKMAN JAMES , WOLF RANDY L
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L29/0603 , H01L21/26513 , H01L21/7624 , H01L21/84 , H01L22/14 , H01L22/20 , H01L27/1203 , H01L29/16 , H01L2924/0002 , H01L2924/00
摘要： A silicon device 100 includes an active silicon layer 106, a buried oxide (BOX) layer 104 beneath the active silicon layer 106 and a high-resistivity silicon layer 102 beneath the BOX layer. The device also includes a harmonic suppression layer 110 at a boundary of the BOX layer 104 and the high-resistivity silicon layer 102.
摘要翻译：硅器件100包括有源硅层106，有源硅层106下方的掩埋氧化物（BOX）层104和BOX层下面的高电阻率硅层102。该装置还包括在BOX层104和高电阻率硅层102的边界处的谐波抑制层110。

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