专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2010017031A1 THROUGH WAFER VIA AND METHOD OF MAKING SAME 审中-公开
标题翻译：通过WAFER方法和制作它的方法
公开(公告)号：WO2010017031A1
公开(公告)日：2010-02-11
申请号：PCT/US2009/051338
申请日：2009-07-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , DING, Hanyi , JOSEPH, Alvin , STAMPER, Anthony
发明人： DING, Hanyi , JOSEPH, Alvin , STAMPER, Anthony
IPC分类号： H01L21/8234 , H01L27/06
CPC分类号： H01L21/76898 , H01L21/6835 , H01L21/6836 , H01L23/481 , H01L25/0657 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , H01L2224/03002 , H01L2224/0401 , H01L2224/04026 , H01L2224/0405 , H01L2224/0557 , H01L2224/06181 , H01L2224/11002 , H01L2224/11003 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/81191 , H01L2224/81192 , H01L2225/06513 , H01L2225/06541 , H01L2924/01068 , H01L2924/1305 , H01L2924/13091 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/00
摘要： A through wafer via structure. The structure includes: a semiconductor substrate (100) having a top surface (105) and an opposite bottom surface (320); and an array of through wafer vias comprising at least one electrically conductive through wafer via (130) and at least one electrically non-conductive through wafer via (125), each through wafer via of the array of through wafer vias extending from the top surface (105) of the substrate (100) to between greater than halfway to and all the way to the bottom surface (320) of the substrate (100). Also methods for fabricating the though wafer via structure.
摘要翻译：通过晶片通孔结构。该结构包括：具有顶表面（105）和相对的底表面（320）的半导体衬底（100）; 以及包括至少一个导电的通过晶片通孔（130）和至少一个非导电的通过晶片通孔（125）的穿过晶片通孔的阵列，每个通过晶片通孔阵列的晶片通孔从顶表面（100）的底表面（105）之间的距离大于中间到所述基底（100）的底表面（320）的距离。也是用于制造晶片通孔结构的方法。

2. 发明申请

WO2010017062A1 METAL WIRING STRUCTURE FOR INTEGRATION WITH THROUGH SUBSTRATE VIAS 审中-公开
标题翻译：通过基板VIAS集成的金属接线结构
公开(公告)号：WO2010017062A1
公开(公告)日：2010-02-11
申请号：PCT/US2009/051908
申请日：2009-07-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , COLLINS, David, S. , JOSEPH, Alvin , LINDGREN, Peter, J. , STAMPER, Anthony, K. , WATSON, Kimball, M.
发明人： COLLINS, David, S. , JOSEPH, Alvin , LINDGREN, Peter, J. , STAMPER, Anthony, K. , WATSON, Kimball, M.
IPC分类号： H01L23/522
CPC分类号： H01L23/522 , H01L23/481 , H01L23/528 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： An array of through substrate vias (TSVs) (20) is formed through a semiconductor substrate (12) and a contact- via-level dielectric layer (50) thereupon. A metal-wire-level dielectric layer (60) and a line-level metal wiring structure (80) embedded therein are formed directly on the contact-via-level dielectric layer (50). The line-level metal wiring structure (80) includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer (60). In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs (20) to maximize the contact area between the TSVs (20) and the line-level metal wiring structure (80). In another embodiment, a set of cheesing holes overlying an entirety of seams (18) in the array of TSVs (20) is formed to prevent trapping of any plating solution in the seams (19)of the TSVs (20) during plating to prevent corrosion of the TSVs (20)at the seams (19).
摘要翻译：穿过衬底通孔（TSV）（20）的阵列通过半导体衬底（12）和接触通过级介电层（50）在其上形成。直接在接触通路层电介质层（50）上形成金属线层介电层（60）和嵌入其中的线状金属布线结构（80）。线状金属布线结构（80）包括填充有金属线层介电层（60）的隔离部分的奶酪孔。在一个实施例中，整个烘干孔位于TSV（20）阵列的区域的外侧，以最大化TSV（20）和线路级金属布线结构（80）之间的接触面积。在另一个实施例中，形成了覆盖在TSV（20）阵列中的整个接缝（18）的一组烘干孔，以防止在电镀期间捕获TSV（20）的接缝（19）中的任何电镀溶液以防止接缝处的TSV（20）的腐蚀（19）。

3. 发明申请

WO2002097896A1 PROCESS FOR MAKING A HIGH VOLTAGE NPN BIPOLAR DEVICE WITH IMPROVED AC PERFORMANCE 审中-公开
标题翻译：制造具有改进的交流性能的高压NPN双极器件的工艺
公开(公告)号：WO2002097896A1
公开(公告)日：2002-12-05
申请号：PCT/GB2002/002350
申请日：2002-05-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED
发明人： JOHNSON, Jeffrey , JOSEPH, Alvin , RAMACHANDRAN, Vidhya
IPC分类号： H01L29/08
CPC分类号： H01L29/66242 , H01L29/0821 , H01L29/7378
摘要： A method of improving the speed of a heterojunction bipolar device without negatively impacting ruggedness of the device is provided. This method includes the steps of providing a structure that includes at least a bipolar device region, the bipolar device region comprising at least a collector region (14) formed over a sub-collector region (12); and forming an n-type dopant region within the collector region, wherein the n-type dopant region (18) within the collector region, wherein the n-type dopant region has a vertical width that is less than about 200 nm (2000 Å) and a peak concentration that is greater than a peak concentration of the collector region. The present invention also provides a method of fabricating a heterojunction bipolar transistor device as well as the device itself which can be used in various applications including as a component for a mobile phone, a component of a personal digital assistant and other like applications wherein speed and ruggedness are required.
摘要翻译：提供了一种提高异质结双极器件的速度而不会不利地影响器件耐用性的方法。该方法包括提供包括至少双极器件区域的结构的步骤，所述双极器件区域至少包括形成在子集电极区域（12）上的集电极区域（14）。以及在所述集电极区域内形成n型掺杂剂区域，其中所述集电极区域内的所述n型掺杂剂区域（18），其中所述n型掺杂剂区域具有小于约200nm的垂直宽度（2000）并且峰浓度大于集电极区域的峰值浓度。本发明还提供了一种制造异质结双极晶体管器件的方法以及可用于各种应用的器件本身，包括用作移动电话的组件，个人数字助理的组件以及其它类似的应用，其中速度和需要坚固性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式