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1. 发明申请

WO9630933A3 SOLDER BUMP FABRICATION METHODS AND STRUCTURE INCLUDING A TITANIUM BARRIER LAYER 审中-公开
标题翻译：焊膏制造方法和结构，包括钛白垩纪层
公开(公告)号：WO9630933A3
公开(公告)日：1996-11-28
申请号：PCT/US9603657
申请日：1996-03-18
申请人： MCNC , MIS JOSEPH DANIEL , ADEMA GRETCHEN MAERKER , KELLAM MARK D , ROGERS W BOYD
发明人： MIS JOSEPH DANIEL , ADEMA GRETCHEN MAERKER , KELLAM MARK D , ROGERS W BOYD
IPC分类号： H01L21/288 , H01L21/60 , H01L23/485 , H01L
CPC分类号： H01L24/03 , H01L21/2885 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05027 , H01L2224/05147 , H01L2224/05171 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/10145 , H01L2224/11001 , H01L2224/11462 , H01L2224/11472 , H01L2224/11474 , H01L2224/11849 , H01L2224/13116 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/05042 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/00014 , H01L2224/29099 , H01L2924/00 , H01L2224/05552
摘要： A method for fabricating solder bumps on a microelectronic device having contact pads includes the steps of depositing a titanium barrier layer on the device, forming an under bump metallurgy layer on the titanium barrier layer, and forming one or more solder bumps on the under bump metallurgy layer. The solder bump or bumps define exposed portions of the under bump metallurgy layer which are removed, and then the exposed portion of the titanium barrier layer is removed. The titanium barrier layer protects the underlying microelectronic device from the etchants used to remove the under bump metallurgy layer. The titanium layer also prevents the under bump metallurgy layer from forming a residue on the underlying microelectronic device. Accordingly, the titanium barrier layer allows the under bump metallurgy layer to be quickly removed without leaving residual matter, thereby reducing the possibility of electrical shorts between solder bumps.
摘要翻译：一种用于在具有接触焊盘的微电子器件上制造焊料凸块的方法包括以下步骤：在该器件上沉积钛阻挡层，在该钛阻挡层上形成凸块下的冶金层，以及在该凸起下的冶金学上形成一个或多个焊料凸点层。焊料凸块或凸点限定突出的冶金层的暴露部分被去除，然后去除钛阻挡层的暴露部分。钛阻挡层保护下面的微电子器件不被用于去除凸块下金属层的蚀刻剂。钛层还防止下凸块冶金层在下面的微电子器件上形成残留物。因此，钛阻挡层允许下凸块冶金层快速去除而不留下残留物，从而减少焊料凸块之间的电短路的可能性。

2. 发明申请

WO1996008040A1 FIELD EFFECT TRANSISTORS AND METHOD OF FABRICATING SAME 审中-公开
标题翻译：场效应晶体管及其制造方法
公开(公告)号：WO1996008040A1
公开(公告)日：1996-03-14
申请号：PCT/US1995011095
申请日：1995-09-05
申请人： MCNC , KELLAM, Mark, D.
发明人： MCNC
IPC分类号： H01L29/772
CPC分类号： H01L29/6659 , H01L29/1045 , H01L29/1083 , H01L29/6656 , H01L29/7833
摘要： A field effect transistor includes a pair of buried centroid regions in a semiconductor substrate at a predetermined depth from the substrate face and having a doping concentration opposite the source and drain regions. A gradient region surrounds each of the pair of buried centroid regions. The gradient regions have decreasing doping concentration in all directions away from the associated centroid region. Source and drain extension regions may also be provided. The buried centroid/gradient regions operate to screen charge on the source and drain regions facing the channel to prevent this charge from interacting with the channel. Short channel effects are thereby reduced or minimized. The threshold voltage of the device can also be adjusted without the need for threshold adjusting implants. The buried centroid/gradient regions and source and drain extension regions may be fabricated in a self-aligned process using the gate and gate sidewall spacers as a mask.
摘要翻译：场效应晶体管包括在距离衬底表面预定深度处的半导体衬底中的一对掩埋重心区域，并具有与源区和漏区相对的掺杂浓度。一个梯度区围绕着一对掩埋的重心区域。梯度区域在离相关重心区域的所有方向上具有降低的掺杂浓度。还可以提供源极和漏极延伸区域。埋置的质心/梯度区域用于屏蔽面向通道的源极和漏极区域上的电荷，以防止该电荷与沟道相互作用。从而减少或最小化短信道效应。也可以调节器件的阈值电压，而不需要阈值调整植入物。掩埋的重心/梯度区域和源极和漏极延伸区域可以使用栅极和栅极侧壁间隔物作为掩模以自对准工艺制造。

3. 发明申请

WO2013028376A2 RESISTIVE RAM DEVICE HAVING IMPROVED SWITCHING CHARACTERISTICS 审中-公开
标题翻译：具有改进的开关特性的电阻RAM设备
公开(公告)号：WO2013028376A2
公开(公告)日：2013-02-28
申请号：PCT/US2012/050363
申请日：2012-08-10
申请人： RAMBUS INC. , KELLAM, Mark, D. , BRONNER, Gary, B.
发明人： KELLAM, Mark, D. , BRONNER, Gary, B.
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L45/085 , G11C13/0011 , H01L27/2472 , H01L45/1233 , H01L45/1266 , H01L45/1273 , H01L45/142 , H01L45/143 , H01L45/145 , H01L45/146 , H01L45/1675
摘要： A resistive RAM device, comprising a first electrode, a second electrode, an electrolyte layer located between the first electrode and the second electrode. The first electrode has a central region surrounded by a peripheral region in a plane parallel to the electrolyte layer, and the first electrode comprises a protrusion extending into the electrolyte layer by a greater extent in the central region than in the peripheral region so that the electrolyte layer is thinner in the central region than in the peripheral region.
摘要翻译：一种电阻RAM装置，包括第一电极，第二电极，位于第一电极和第二电极之间的电解质层。第一电极具有由与电解质层平行的平面中的周边区域围绕的中心区域，第一电极包括在中心区域比在周边区域中更大程度地延伸到电解质层中的突起，使得电解质中心区域的层比外围区域薄。

4. 发明申请

WO2012178114A2 RESISTANCE MEMORY CELL 审中-公开
标题翻译：电阻存储单元
公开(公告)号：WO2012178114A2
公开(公告)日：2012-12-27
申请号：PCT/US2012/043884
申请日：2012-06-22
申请人： RAMBUS INC. , KELLAM, Mark, D. , BRONNER, Gary, B.
发明人： KELLAM, Mark, D. , BRONNER, Gary, B.
IPC分类号： G11C13/00 , G11C7/10 , G11C7/20
CPC分类号： G11C13/004 , G11C13/00 , G11C13/0011 , G11C13/003 , G11C13/0069 , G11C13/0097 , G11C2013/0052 , G11C2013/0073 , G11C2013/0083 , G11C2213/72 , H01L27/2409 , H01L27/2418 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/143
摘要： A resistance memory includes a resistance memory cell having a resistance memory element and a two-terminal access device in series. The two-terminal access device affects the current-voltage characteristic of the resistance memory cell. The resistance memory additionally includes a circuit to apply across the resistance memory cell a set pulse having a set polarity to set the resistance memory cell to a low- resistance state that is retained after application of the set pulse, a reset pulse having a reset polarity, opposite to the set polarity, to reset the resistance memory cell to a high-resistance state that is retained after application of the reset pulse, and a read pulse of the reset polarity and smaller in magnitude than the reset pulse to determine the resistance state of the resistance memory cell without changing the resistance state of the resistance memory cell.
摘要翻译：电阻存储器包括具有电阻存储元件和串联的两端存取装置的电阻存储单元。双端子存取装置影响电阻存储单元的电流 - 电压特性。电阻存储器还包括一个电路，在电阻存储单元两端施加具有设定极性的设定脉冲，将电阻存储单元设置为在施加设定脉冲后保持的低电阻状态，具有复位极性的复位脉冲与设定的极性相反，将电阻存储单元复位到施加复位脉冲之后保持的高电阻状态，以及复位极性的读取脉冲和幅度比复位脉冲更小以确定电阻状态的电阻存储单元，而不改变电阻存储单元的电阻状态。

5. 发明申请

WO2011056281A1 THREE-DIMENSIONAL MEMORY ARRAY STACKING STRUCTURE 审中-公开
标题翻译：三维存储阵列堆叠结构
公开(公告)号：WO2011056281A1
公开(公告)日：2011-05-12
申请号：PCT/US2010/046831
申请日：2010-08-26
申请人： RAMBUS INC. , KELLAM, Mark D. , BRONNER, Gary B.
发明人： KELLAM, Mark D. , BRONNER, Gary B.
IPC分类号： G11C5/02 , G11C7/18 , G11C8/14 , H01L27/115
CPC分类号： G11C5/063 , G11C5/02 , H01L27/2409 , H01L27/2418 , H01L27/2454 , H01L27/249 , H01L45/085 , H01L45/1226 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/145 , H01L45/146
摘要： A memory device includes a planar substrate, a plurality of horizontal conductive planes above the planar substrate, and a plurality of horizontal insulating layers interleaved with the plurality of horizontal conductive planes. An array of vertical conductive columns, perpendicular to the pluralities of conductive planes and insulating layers, passes through apertures in the pluralities of conductive planes and insulating layers. The memory device includes a plurality of programmable memory elements, each of which couples one of the horizontal conductive planes to a respective vertical conductive column.
摘要翻译：存储装置包括平面基板，平面基板上方的多个水平导电平面以及与多个水平导电平面交错的多个水平绝缘层。垂直于多个导电平面和绝缘层的垂直导电柱阵列穿过多个导电平面和绝缘层中的孔。存储器件包括多个可编程存储器元件，每个可编程存储器元件将一个水平导电平面耦合到相应的垂直导电柱。

6. 发明申请

WO2009017871A1 NON-VOLATILE MEMORY DEVICE WITH REDUCED WRITE-ERASE CYCLE TIME 审中-公开
标题翻译：具有减少写擦除周期时间的非易失性存储器件
公开(公告)号：WO2009017871A1
公开(公告)日：2009-02-05
申请号：PCT/US2008/064246
申请日：2008-05-20
申请人： RAMBUS INC. , KELLAM, Mark D.
发明人： KELLAM, Mark D.
IPC分类号： H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L29/7883 , H01L29/0649 , H01L29/512 , H01L29/66825 , H01L29/66833 , H01L29/792
摘要： A transistor includes a substrate having a surface, where a first region and a second region of the substrate are doped with a first type of dopant, and where a third region of the substrate between the first region and the second region is doped with a second type of dopant. An insulator layer is deposited above a portion of the surface, which includes the third region, and a gate layer is deposited above the insulator layer. An encapsulation layer encloses ends of the gate layer, thereby defining gaps between ends of the insulator layer and the encapsulation layer. These gaps have a depth relative to the ends of the gate layer, with one end of the insulator layer proximate to a boundary between the first region and the third region and another end of the insulator layer proximate to a boundary between the second region and the third region.
摘要翻译：晶体管包括具有表面的衬底，其中衬底的第一区域和第二区域掺杂有第一类型的掺杂剂，并且其中第一区域和第二区域之间的衬底的第三区域掺杂有第二区域掺杂剂类型。在包括第三区域的表面的一部分上方沉积绝缘体层，并且在绝缘体层上方沉积栅极层。封装层封闭栅极层的端部，从而在绝缘体层的端部和封装层之间限定间隙。这些间隙具有相对于栅极层的端部的深度，绝缘体层的一端靠近第一区域和第三区域之间的边界，绝缘体层的另一端靠近第二区域和第二区域之间的边界第三区。

7. 发明申请

WO2013028376A3 RESISTIVE RAM DEVICE HAVING IMPROVED SWITCHING CHARACTERISTICS 审中-公开
标题翻译：具有改进开关特性的电阻性RAM器件
公开(公告)号：WO2013028376A3
公开(公告)日：2013-07-11
申请号：PCT/US2012050363
申请日：2012-08-10
申请人： RAMBUS INC , KELLAM MARK D , BRONNER GARY B
发明人： KELLAM MARK D , BRONNER GARY B
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L45/085 , G11C13/0011 , H01L27/2472 , H01L45/1233 , H01L45/1266 , H01L45/1273 , H01L45/142 , H01L45/143 , H01L45/145 , H01L45/146 , H01L45/1675
摘要： A resistive RAM device, comprising a first electrode, a second electrode, an electrolyte layer located between the first electrode and the second electrode. The first electrode has a central region surrounded by a peripheral region in a plane parallel to the electrolyte layer, and the first electrode comprises a protrusion extending into the electrolyte layer by a greater extent in the central region than in the peripheral region so that the electrolyte layer is thinner in the central region than in the peripheral region.
摘要翻译：一种电阻式RAM器件，包括第一电极，第二电极，位于第一电极和第二电极之间的电解质层。第一电极具有由平行于电解质层的平面中的周边区域围绕的中心区域，并且第一电极包括在中心区域中比在周边区域中更大程度地延伸到电解质层中的突起，使得电解质层在中心区域比在外围区域更薄。

8. 发明申请

WO2011068737A2 PLANAR MOSFET WITH TEXTURED CHANNEL AND GATE 审中-公开
标题翻译：具有纹理通道和栅极的平面MOSFET
公开(公告)号：WO2011068737A2
公开(公告)日：2011-06-09
申请号：PCT/US2010/058069
申请日：2010-11-24
申请人： RAMBUS INC. , KELLAM, Mark, D.
发明人： KELLAM, Mark, D.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66575 , H01L29/1037 , H01L29/1054 , H01L29/165 , H01L29/66787 , H01L29/78
摘要： A semiconductor device is disclosed that includes a semiconductor substrate having a channel region and respective source and drain regions formed on opposite sides of the channel region. The channel region includes at least one pore. A gate is formed on the semiconductor substrate between the source and drain regions and includes at least one pin received by respective ones of the at least one pore. A dielectric layer is disposed between the gate and the semiconductor substrate.
摘要翻译：公开了一种半导体器件，其包括具有沟道区和形成在沟道区的相对侧上的相应源极和漏极区的半导体衬底。沟道区域包括至少一个孔。栅极形成在源极和漏极区域之间的半导体衬底上，并且包括由至少一个孔隙中的相应孔隙接收的至少一个管脚。电介质层设置在栅极和半导体衬底之间。

9. 发明申请

WO2010110938A2 PULSE CONTROL FOR NONVOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器的脉冲控制
公开(公告)号：WO2010110938A2
公开(公告)日：2010-09-30
申请号：PCT/US2010/022605
申请日：2010-01-29
申请人： RAMBUS INC. , KELLAM, Mark, D. , HAUKNESS, Brent, Steven , BRONNER, Gary, B. , DONNELLY, Kevin
发明人： KELLAM, Mark, D. , HAUKNESS, Brent, Steven , BRONNER, Gary, B. , DONNELLY, Kevin
IPC分类号： G11C16/32 , G11C16/30 , G11C16/08
CPC分类号： G11C16/10 , G11C16/0408 , G11C16/12 , G11C16/26 , G11C16/3459
摘要： This disclosure provides a nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage (selected in response to the bitline) is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about (20) nanoseconds, while a "rest period" between pulses typically is chosen to be on the order of about a hundred nanoseconds or greater (e.g., one microsecond). Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of (50) nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); if desired, segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.
摘要翻译：本公开提供了一种非易失性存储器件，其使用脉冲控制和休止时间来减轻缺陷前兆的形成。第一实施例使用脉冲位线控制，其中当期望改变相关联的存储器单元中的状态时，存储器单元沟道与参考电压（响应于位线而选择）之间的耦合被脉冲化。每个脉冲可以被选择为小于大约（20）纳秒，而“休息时段” 通常选择脉冲之间的时间约为几百纳秒或更大（例如，一微秒）。由于使用了位线控制，因此可以启用非常短的上升时间，从而可以生成（50）纳秒或更短的脉冲持续时间。在其他实施例中，这些方法也可以更一般地应用于其他导体（例如，用于编程或擦除操作的字线或衬底）; 如果需要的话，也可以使用分段的字线或位线，以最小化RC负载并使足够短的上升时间使脉冲稳健。

10. 发明申请

WO2011068737A3 PLANAR MOSFET WITH TEXTURED CHANNEL AND GATE 审中-公开
标题翻译：具有纹理通道和门的平面MOSFET
公开(公告)号：WO2011068737A3
公开(公告)日：2011-11-24
申请号：PCT/US2010058069
申请日：2010-11-24
申请人： RAMBUS INC , KELLAM MARK D
发明人： KELLAM MARK D
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66575 , H01L29/1037 , H01L29/1054 , H01L29/165 , H01L29/66787 , H01L29/78
摘要： A semiconductor device is disclosed that includes a semiconductor substrate having a channel region and respective source and drain regions formed on opposite sides of the channel region. The channel region includes at least one pore. A gate is formed on the semiconductor substrate between the source and drain regions and includes at least one pin received by respective ones of the at least one pore. A dielectric layer is disposed between the gate and the semiconductor substrate.
摘要翻译：公开了一种半导体器件，其包括具有形成在沟道区的相对侧上的沟道区和相应的源极和漏极区的半导体衬底。通道区域包括至少一个孔。栅极形成在源极和漏极区域之间的半导体衬底上，并且包括由至少一个孔中的相应孔接收的至少一个销。介电层设置在栅极和半导体衬底之间。

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