专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2011056281A1 THREE-DIMENSIONAL MEMORY ARRAY STACKING STRUCTURE 审中-公开
标题翻译：三维存储阵列堆叠结构
公开(公告)号：WO2011056281A1
公开(公告)日：2011-05-12
申请号：PCT/US2010/046831
申请日：2010-08-26
申请人： RAMBUS INC. , KELLAM, Mark D. , BRONNER, Gary B.
发明人： KELLAM, Mark D. , BRONNER, Gary B.
IPC分类号： G11C5/02 , G11C7/18 , G11C8/14 , H01L27/115
CPC分类号： G11C5/063 , G11C5/02 , H01L27/2409 , H01L27/2418 , H01L27/2454 , H01L27/249 , H01L45/085 , H01L45/1226 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/145 , H01L45/146
摘要： A memory device includes a planar substrate, a plurality of horizontal conductive planes above the planar substrate, and a plurality of horizontal insulating layers interleaved with the plurality of horizontal conductive planes. An array of vertical conductive columns, perpendicular to the pluralities of conductive planes and insulating layers, passes through apertures in the pluralities of conductive planes and insulating layers. The memory device includes a plurality of programmable memory elements, each of which couples one of the horizontal conductive planes to a respective vertical conductive column.
摘要翻译：存储装置包括平面基板，平面基板上方的多个水平导电平面以及与多个水平导电平面交错的多个水平绝缘层。垂直于多个导电平面和绝缘层的垂直导电柱阵列穿过多个导电平面和绝缘层中的孔。存储器件包括多个可编程存储器元件，每个可编程存储器元件将一个水平导电平面耦合到相应的垂直导电柱。

2. 发明申请

WO2009042298A1 FLASH MEMORY REFRESH 审中-公开
标题翻译：闪存记忆刷新
公开(公告)号：WO2009042298A1
公开(公告)日：2009-04-02
申请号：PCT/US2008/072917
申请日：2008-08-12
申请人： RAMBUS INC. , HAUKNESS, Brent S. , BRONNER, Gary B.
发明人： HAUKNESS, Brent S. , BRONNER, Gary B.
IPC分类号： G11C16/34
CPC分类号： G11C16/3431 , G11C16/349
摘要： Embodiments of a circuit are described. This circuit includes storage cells having a data retention time that progressively decreases from an initial data retention time to a substantially reduced data retention time as operations are performed on at least a subset of the storage cells. Moreover, the circuit includes a refresh circuit, which is coupled to the storage cells, that refreshes data stored in one or more of the storage cells after a first refresh interval that is short enough to ensure data retention even after the data retention time of the one or more of the storage cells has decreased to the substantially reduced data retention time.
摘要翻译：描述电路的实施例。该电路包括具有从初始数据保留时间逐渐减小到基本上减少的数据保留时间的数据保留时间的存储单元，因为在存储单元的至少一个子集上执行操作。此外，电路包括与存储单元耦合的刷新电路，其刷新在第一刷新间隔之后存储在一个或多个存储单元中的数据，该第一刷新间隔足够短以确保即使在数据保留时间一个或多个存储单元已经减少到显着减少的数据保留时间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式