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1. 发明申请

WO1996008040A1 FIELD EFFECT TRANSISTORS AND METHOD OF FABRICATING SAME 审中-公开
标题翻译：场效应晶体管及其制造方法
公开(公告)号：WO1996008040A1
公开(公告)日：1996-03-14
申请号：PCT/US1995011095
申请日：1995-09-05
申请人： MCNC , KELLAM, Mark, D.
发明人： MCNC
IPC分类号： H01L29/772
CPC分类号： H01L29/6659 , H01L29/1045 , H01L29/1083 , H01L29/6656 , H01L29/7833
摘要： A field effect transistor includes a pair of buried centroid regions in a semiconductor substrate at a predetermined depth from the substrate face and having a doping concentration opposite the source and drain regions. A gradient region surrounds each of the pair of buried centroid regions. The gradient regions have decreasing doping concentration in all directions away from the associated centroid region. Source and drain extension regions may also be provided. The buried centroid/gradient regions operate to screen charge on the source and drain regions facing the channel to prevent this charge from interacting with the channel. Short channel effects are thereby reduced or minimized. The threshold voltage of the device can also be adjusted without the need for threshold adjusting implants. The buried centroid/gradient regions and source and drain extension regions may be fabricated in a self-aligned process using the gate and gate sidewall spacers as a mask.
摘要翻译：场效应晶体管包括在距离衬底表面预定深度处的半导体衬底中的一对掩埋重心区域，并具有与源区和漏区相对的掺杂浓度。一个梯度区围绕着一对掩埋的重心区域。梯度区域在离相关重心区域的所有方向上具有降低的掺杂浓度。还可以提供源极和漏极延伸区域。埋置的质心/梯度区域用于屏蔽面向通道的源极和漏极区域上的电荷，以防止该电荷与沟道相互作用。从而减少或最小化短信道效应。也可以调节器件的阈值电压，而不需要阈值调整植入物。掩埋的重心/梯度区域和源极和漏极延伸区域可以使用栅极和栅极侧壁间隔物作为掩模以自对准工艺制造。

2. 发明申请

WO1998006118A1 ENCAPSULATED MICRO-RELAY MODULES AND METHODS OF FABRICATING SAME 审中-公开
标题翻译：封装的微型继电器模块及其制造方法
公开(公告)号：WO1998006118A1
公开(公告)日：1998-02-12
申请号：PCT/US1997014332
申请日：1997-07-30
申请人： MCNC , KELLAM, Mark, D. , BERRY, Michele, J.
发明人： MCNC
IPC分类号： H01H01/00
CPC分类号： H01H50/005 , H01H1/66 , H01H2050/025
摘要： A micro-relay module includes a substrate and a lid in spaced apart relation, and a solder ring which bonds the lid to the substrate to define a chamber therebetween. A micromachined relay is integrally formed on the substrate or on the lid within the chamber. A gas is contained in the chamber at a gas pressure which is above atmospheric pressure. Input/output pads are included outside the chamber and electrically connected to the micromachined relay. Large numbers of encapsulated modules may be fabricated on a single substrate by integrally forming an array of relays on a face of a first substrate. A second substrate is placed adjacent the face with a corresponding array of solder rings therebetween, such that a respective solder ring surrounds a respective relay. The solder rings are reflowed in a gas atmosphere which is above atmospheric pressure to thereby form an array of high pressure gas encapsulating chambers. The first and second substrates are then singulated for from a plurality of individual micro-relay modules.
摘要翻译：微型继电器模块包括基板和间隔开的盖子，以及焊接环，其将盖子结合到基板以在其间限定室。微机械继电器一体地形成在基板上或室内的盖上。气体在高于大气压的气体压力下容纳在腔室中。输入/输出焊盘包括在室外，并电连接到微加工继电器。通过在第一衬底的表面上整合形成继电器阵列，可以在单个衬底上制造大量的封装模块。第二衬底被放置成与面对相邻的焊接环阵列相邻，使得相应的焊锡环围绕相应的继电器。焊锡环在高于大气压的气体气氛中回流，从而形成高压气体封装室阵列。然后将第一和第二基板从多个单独的微型继电器模块分离。

3. 发明申请

WO1996030933A2 SOLDER BUMP FABRICATION METHODS AND STRUCTURE INCLUDING A TITANIUM BARRIER LAYER 审中-公开
标题翻译：焊膏制造方法和结构，包括钛白垩纪层
公开(公告)号：WO1996030933A2
公开(公告)日：1996-10-03
申请号：PCT/US1996003657
申请日：1996-03-18
申请人： MCNC , MIS, Joseph, Daniel , ADEMA, Gretchen, Maerker , KELLAM, Mark, D. , ROGERS, W., Boyd
发明人： MCNC
IPC分类号： H01L00/00
CPC分类号： H01L24/03 , H01L21/2885 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05027 , H01L2224/05147 , H01L2224/05171 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/10145 , H01L2224/11001 , H01L2224/11462 , H01L2224/11472 , H01L2224/11474 , H01L2224/11849 , H01L2224/13116 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/05042 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/00014 , H01L2224/29099 , H01L2924/00 , H01L2224/05552
摘要： A method for fabricating solder bumps on a microelectronic device having contact pads includes the steps of depositing a titanium barrier layer on the device, forming an under bump metallurgy layer on the titanium barrier layer, and forming one or more solder bumps on the under bump metallurgy layer. The solder bump or bumps define exposed portions of the under bump metallurgy layer which are removed, and then the exposed portion of the titanium barrier layer is removed. The titanium barrier layer protects the underlying microelectronic device from the etchants used to remove the under bump metallurgy layer. The titanium layer also prevents the under bump metallurgy layer from forming a residue on the underlying microelectronic device. Accordingly, the titanium barrier layer allows the under bump metallurgy layer to be quickly removed without leaving residual matter, thereby reducing the possibility of electrical shorts between solder bumps.
摘要翻译：一种用于在具有接触焊盘的微电子器件上制造焊料凸块的方法包括以下步骤：在该器件上沉积钛阻挡层，在该钛阻挡层上形成凸块下的冶金层，以及在该凸起下的冶金学上形成一个或多个焊料凸点层。焊料凸块或凸点限定突出的冶金层的暴露部分被去除，然后去除钛阻挡层的暴露部分。钛阻挡层保护下面的微电子器件不被用于去除凸块下金属层的蚀刻剂。钛层还防止下凸块冶金层在下面的微电子器件上形成残留物。因此，钛阻挡层允许下凸块冶金层快速去除而不留下残留物，从而减少焊料凸块之间电短路的可能性。

4. 发明申请

WO1998014299A1 TACKING PROCESSES AND SYSTEMS FOR SOLDERING 审中-公开
标题翻译：焊接过程和系统
公开(公告)号：WO1998014299A1
公开(公告)日：1998-04-09
申请号：PCT/US1997018158
申请日：1997-09-30
申请人： MCNC , KOOPMAN, Nicholas, G. , NANGALIA, Sundeep
发明人： MCNC
IPC分类号： B23K01/06
CPC分类号： B23K1/06 , H05K3/3436
摘要： A first component is soldered to a second component by placing the first component on the second component with solder therebetween, then ultrasonically vibrating at least one of the first and second components to thereby tack the solder to at least one of the first and second components, and by reflowing the solder. Ultrasonic vibration of at least one of the first and second components to thereby tack the solder is preferably performed for less than one second. A component placer places the first component on the second component with solder therebetween. An ultrasonic vibrator ultrasonically vibrates at least one of the placed first and second components, to thereby tack the solder to at least one of the placed first and second components. A solder reflower reflows the tacked solder to thereby solder the first component to the second component.
摘要翻译：将第一部件焊接到第二部件上，通过将第一部件放置在第二部件上，在其间具有焊料，然后超声振动第一和第二部件中的至少一个，从而将焊料固定到第一和第二部件中的至少一个，并通过回流焊料。第一和第二组分中的至少一个的超声波振动优选地进行少于1秒。组件放置器将第一部件放置在第二部件上，其间具有焊料。超声波振动器超声振动放置的第一和第二部件中的至少一个，从而将焊料固定到所放置的第一和第二部件中的至少一个。焊料回流焊机将固定的焊料回流，从而将第一部件焊接到第二部件。

5. 发明申请

WO1993018536A1 VERTICAL MICROELECTRONIC FIELD EMISSION DEVICES AND METHODS OF MAKING SAME 审中-公开
标题翻译：垂直微电子场发射装置及其制造方法
公开(公告)号：WO1993018536A1
公开(公告)日：1993-09-16
申请号：PCT/US1993001727
申请日：1993-03-03
申请人： MCNC
发明人： MCNC , JONES, Gary, Wayne , SUNE, Ching-Tzong
IPC分类号： H01J01/30
CPC分类号： H01J3/021 , H01J1/3042 , H01J9/025 , H01J2201/319
摘要： A vertical microelectronic field emitter (10) includes a conductive top portion (15) and a resistive bottom portion (16) in an elongated column (12) which extends vertically from a horizontal substrate (11). An emitter electrode (17) may be formed at the base of the column, and an extraction electrode (18) may be formed adjacent the top of the column. The elongated column reduces the parasitic capacitance of the microelectronic field emitter to provide high speed operation, while providing uniform column-to-column resistance. The field emitter may be formed by first forming tips (15) on the face of a substrate and then forming trenches (22) in the substrate (11) around the tips to form columns (12) in the substrate, with the tips lying on top of the columns. The trenches are filled with a dielectric (19) and a conductor layer (18) is formed on the dielectric. Alternatively, trenches may be formed in the face of the substrate (11) with the trenches defining columns (12) in the substrate. Then, tips (15) are formed on top of the columns. The trenches are filled with dielectric and the conductor layers is formed on the dielectric to form the extraction electrodes.
摘要翻译：垂直微电子场发射器（10）包括从水平衬底（11）垂直延伸的细长柱（12）中的导电顶部（15）和电阻底部（16）。可以在塔的底部形成发射电极（17），并且可以在柱的顶部附近形成引出电极（18）。细长柱减小了微电子场发射器的寄生电容，以提供高速操作，同时提供均匀的柱对列电阻。场发射器可以通过在衬底的表面上首先形成尖端（15）然后在衬底（11）周围的尖端上形成沟槽（22）而形成，以在衬底中形成柱（12），其中尖端位于列的顶部。沟槽填充有电介质（19），并且在电介质上形成导体层（18）。或者，可以在衬底（11）的表面上形成沟槽，其中沟槽在衬底中限定柱（12）。然后，顶部（15）形成在柱的顶部。沟槽被电介质填充，并且导体层形成在电介质上以形成提取电极。

6. 发明申请

WO1996031905A1 A SOLDER BUMP STRUCTURE FOR A MICROELECTRONIC SUBSTRATE 审中-公开
标题翻译：微电子基板的焊接结构
公开(公告)号：WO1996031905A1
公开(公告)日：1996-10-10
申请号：PCT/US1996003751
申请日：1996-03-21
申请人： MCNC , RINNE, Glenn, A. , MIS, Joseph, Daniel
发明人： MCNC
IPC分类号： H01L23/485
CPC分类号： H01L24/13 , H01L24/11 , H01L2224/0231 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05171 , H01L2224/05647 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30107 , Y10T29/49144 , Y10T29/49149 , Y10T29/49155 , H01L2924/00014 , H01L2924/013
摘要： A method for forming integrated redistribution routing conductors (17) and solder bumps (21) on a microelectronic substrate (15) comprises the steps of forming an under bump metallurgy layer (16) on the substrate and forming a solder structure on the under bump metallurgy layer wherein the solder structure includes an elongate portion (22B) and an enlarged width portion (22A). The portions of the under bump metallurgy layer not covered by the solder structure can be selectively removed using the solder structure as a mask. In addition, the solder is caused to flow from the elongate portion of the solder structure to the enlarged width solder portion thereby forming a raised solder bump. This step is preferably performed by heating the solder structure above its liquidus temperature allowing surface tension induced internal pressures to affect the flow. Various solder structures are also disclosed.
摘要翻译：一种用于在微电子衬底（15）上形成集成再分配布线导体（17）和焊料凸块（21）的方法包括以下步骤：在衬底上形成凸块下金属层（16），并在凸块下金属上形成焊料结构层，其中焊料结构包括细长部分（22B）和扩大的宽度部分（22A）。可以使用焊料结构作为掩模来选择性地去除不被焊料结构覆盖的凸块下冶金层的部分。此外，使焊料从焊料结构的细长部分流向扩大的宽度焊料部分，从而形成凸起的焊料凸块。该步骤优选通过将焊料结构加热到高于其液相线温度来进行，从而允许表面张力引起的内部压力影响流动。还公开了各种焊料结构。

7. 发明申请

WO1991003833A1 ELECTROSTATIC HANDLING DEVICE 审中-公开
标题翻译：静电处理装置
公开(公告)号：WO1991003833A1
公开(公告)日：1991-03-21
申请号：PCT/US1990005002
申请日：1990-09-04
申请人： MCNC
发明人： MCNC , BOBBIO, Stephen, Michael
IPC分类号： H01L21/00
CPC分类号： H01L21/6831 , H01L21/6833
摘要： An electrostatic handling device (10) for a wafer (40) having a pair of faces (41, 42), includes a dielectric region (20) having a top face (21) which is adapted to accept one of the pair of wafer faces (41, 42) thereagainst. Conductors (30) are positioned in the dielectric region (20). The conductors (30) are arranged in the dielectric region (20) to generate electrostatic force between the conductors (30) and the wafer (40) to hold the wafer (40) against the top face (21) of the dielectric region (20). The conductors (30) are further arranged in the dielectric region (20) to generate substantially no net electrostatic force at the opposite one of the pair of wafer faces (41, 42) to thereby reduce electrostatic force interference thereat.

8. 发明申请

WO1993006620A1 SOLDER BUMP FABRICATION METHOD AND SOLDER BUMPS FORMED THEREBY 审中-公开
标题翻译：焊膏制造方法和形成的焊料
公开(公告)号：WO1993006620A1
公开(公告)日：1993-04-01
申请号：PCT/US1992007722
申请日：1992-09-11
申请人： MCNC
发明人： MCNC , YUNG, Edward, K.
IPC分类号： H01L21/60
CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/1147 , H01L2224/11502 , H01L2224/11849 , H01L2224/119 , H01L2224/13018 , H01L2224/13023 , H01L2224/13099 , H01L2924/01007 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H05K3/3452 , H05K3/3457 , Y10T29/49117
摘要： The base of solder bumps is preserved by converting the under-bump metallurgy between the solder bump and contact pad into an intermetallic of the solder and the solderable component of the under-bump metallurgy prior to etching the under-bump metallurgy. The intermetallic is resistant to etchants which are used to etch the under-bump metallurgy between the contact pads. Accordingly, minimal undercutting of the solder bumps is produced, and the base size is preserved. The solder may be plated on the under-bump metallurgy over the contact pad through a patterned solder dam layer having a solder accumulation region thereon. The solder dam is preferably a thin film layer which may be accurately aligned to the underlying contact pad to confine the wetting of the molten solder during reflow. Misalignment between the solder bump and contact pad is thereby reduced. The solder bumps so formed include an intermetallic layer which extends beyond the bump to form a lip around the base of the bump. This lip provides extra protection for the solder bump.
摘要翻译：在蚀刻凸块下金属之前，通过将焊料凸块和接触焊盘之间的凸块下金属冶化转变成焊料的金属间化合物和凸块下冶金的可焊接组分来保存焊料凸块的基底。金属间化合物耐腐蚀剂，其用于蚀刻接触焊盘之间的凸起下冶金。因此，产生焊料凸块的最小的底切，并保持基体尺寸。焊料可以通过在其上具有焊料积聚区域的图案化焊料层在接触焊盘上电镀在凸块下金属之上。焊料坝优选是薄膜层，其可以准确地对准下面的接触焊盘，以限制熔融焊料在回流期间的润湿。焊料凸点与接触垫之间的偏移由此减小。如此形成的焊料凸块包括延伸超过凸块的金属间层，以形成围绕凸块的基部的唇缘。该唇缘为焊料凸块提供额外的保护。

9. 发明申请

WO1991006982A1 PASSIVATED POLYCRYSTALLINE SEMICONDUCTORS AND QUANTUM WELL/SUPERLATTICE STRUCTURES FABRICATED THEREOF 审中-公开
标题翻译：钝化多晶硅半导体和量子阱/超导结构
公开(公告)号：WO1991006982A1
公开(公告)日：1991-05-16
申请号：PCT/US1990006122
申请日：1990-10-23
申请人： MCNC
发明人： MCNC , NICOLLIAN, Edward, H. , REISMAN, Arnold , TSU, Raphael
IPC分类号： H01L29/16
CPC分类号： H01L21/324 , H01L21/3245 , H01L29/154 , H01L29/1604
摘要： The internal grain boundaries and intergranular spaces of polycrystalline semiconductor material may be passivated with an amorphous material, to substantially eliminate the dangling bonds at the internal grain boundaries. The passivated polycrystalline material of the present invention exhibits a lower electrically active defect density at the grain boundaries and intergranular space compared to unpassivated polycrystalline material. Moreover, large classes of amorphous passivating materials may be used for each known semiconductor material so that the passivating process may be readily adapted to existing process parameters and other device constraints. Passivated polycrystalline material may be employed to form the well or low energy bandgap layer of a quantum well device or superlattice, while still maintaining the required tunneling effect.

10. 发明申请

WO1991003014A2 METHOD AND APPARATUS FOR HIGH PRECISION WEIGHTED RANDOM PATTERN GENERATION 审中-公开
标题翻译：用于高精度加权随机图形生成的方法和装置
公开(公告)号：WO1991003014A2
公开(公告)日：1991-03-07
申请号：PCT/US1990004832
申请日：1990-08-24
申请人： MCNC , NORTHERN TELECOM LIMITED
发明人： MCNC , NORTHERN TELECOM LIMITED , BRGLEZ, Franc , KEDEM, Gershon , GLOSTER, Clay, Samuel, Jr.
IPC分类号： G06F07/58
CPC分类号： G06F1/03 , G01R31/31813 , G01R31/318385 , G06F7/58 , G06F2101/14
摘要： A high precision weighted random pattern generation system generates any desired probability of individual bit within a weighted random bit pattern. The system includes a circular memory having a series of weighting factors stored therein, with each weighting factor representing the desired probability of a bit in the weighted random pattern being binary ONE. The random bits from a random number generator and a weighting factor are combined to form a single weighted random bit. The random bits and weighting factor are combined in a series of interconnected multiplexor gates. Each multiplexor gate has two data inputs, one being a bit from the weighting factor, the other being the output of the preceding multiplexor gate. The random number bit controls the output of the multiplexor. For example, when the control input (random bit) is high, the multiplexor output is the weighting factor bit. When the control input (random bit) is low, the multiplexor output is the output of the preceding multiplexor. The output of the final multiplexor gate in the series is the weighted bit.

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