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81. 发明申请

WO2013070307A1 COMPOSITION OF MEMORY CELL WITH RESISTANCE-SWITCHING LAYERS 审中-公开
标题翻译：具有电阻切换层的记忆体组成
公开(公告)号：WO2013070307A1
公开(公告)日：2013-05-16
申请号：PCT/US2012/053860
申请日：2012-09-06
申请人： SANDISK 3D LLC , ZHANG, Tong , MINVIELLE, Timothy, James , CHEN, Yung-Tin
发明人： ZHANG, Tong , MINVIELLE, Timothy, James , CHEN, Yung-Tin
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： G11C13/0007 , G11C5/02 , G11C8/10 , G11C13/0002 , G11C13/0004 , G11C13/0069 , G11C2013/0073 , G11C2213/55 , G11C2213/71 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/1608
摘要： A memory cell is proposed that includes a first electrode, a second electrode, and at least a first resistance-switching layer located be tween the first and second electrodes, wherein the resistance-switching layer comprises amorphous hafnium silicon oxynitride. Manufacturing of said memory cell may comprise deposition of a hafnium silicon oxide film followed by nitridation of said film to form the resistance-switching layer.
摘要翻译：提出一种存储单元，其包括第一电极，第二电极和位于第一和第二电极之间的至少第一电阻切换层，其中电阻切换层包括无定形的铪硅氮氧化物。所述存储单元的制造可以包括沉积氧化铪膜，然后氮化所述膜以形成电阻切换层。

82. 发明申请

WO2012118618A1 THREE DIMENSIONAL MEMORY SYSTEM WITH COLUMN PIPELINE 审中-公开
标题翻译：具有柱管的三维存储系统
公开(公告)号：WO2012118618A1
公开(公告)日：2012-09-07
申请号：PCT/US2012/025171
申请日：2012-02-15
申请人： SANDISK 3D LLC , YAN, Tianhong , BALAKRISHNAN, Gopinath , LEE, Jeffrey, Koon Yee , LIU, Tz-yi
发明人： YAN, Tianhong , BALAKRISHNAN, Gopinath , LEE, Jeffrey, Koon Yee , LIU, Tz-yi
IPC分类号： G11C7/10 , G11C7/18 , G11C13/00 , G11C17/16
CPC分类号： G11C7/1006 , G11C7/1012 , G11C7/1039 , G11C7/18 , G11C8/08 , G11C8/18 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/0069 , G11C17/16
摘要： A monolithic three dimensional array of non-volatile storage elements is arranged in blocks. The non-volatile storage elements are connected to bit lines and word lines. The bit lines for each block are grouped into columns of bit lines. The columns of bit lines include top columns of bit lines that are connected to selection circuits on a top side of a respective block and bottom columns of bit lines that are connected to selection circuits on a bottom side of the respective block. Programming of data is pipelined between two or more columns of bit lines in order to increase programming speed. One embodiment of the programming process includes selectively connecting two columns of bit lines to a set of one or more selection circuits, using the one or more selection circuits to selectively connect one of the two columns of bit lines to one or more signal sources, programming non-volatile storage elements for the column of bit lines that is currently connected to the one or more signal sources, and changing one of the columns of bit lines connected to the set of one or more selection circuits while another column of bit lines is being programmed.
摘要翻译：非易失性存储元件的单片三维阵列以块状排列。非易失性存储元件连接到位线和字线。每个块的位线被分组成位线列。位线列包括连接到相应块的顶侧上的选择电路的顶列和位于相应块的底侧上的选择电路的位线的底列。数据的编程在两列或更多列的位线之间流水线化，以提高编程速度。编程过程的一个实施例包括使用一个或多个选择电路选择性地将两列位线连接到一组或多个选择电路，以选择性地将两列位线中的一列连接到一个或多个信号源，编程用于当前连接到一个或多个信号源的位线列的非易失性存储元件，以及改变连接到一组或多个选择电路的位线的列之一，而另一列位线正在被程序。

83. 发明申请

WO2011159583A4 COMPOSITION OF MEMORY CELL WITH RESISTANCE-SWITCHING LAYERS 审中-公开
标题翻译：具有电阻切换层的存储器单元的组成
公开(公告)号：WO2011159583A4
公开(公告)日：2012-08-02
申请号：PCT/US2011040105
申请日：2011-06-10
申请人： SANDISK 3D LLC , KREUPL FRANZ , BANDYOPADHYAY ABHIJIT , CHEN YUNG-TIN , FU CHU-CHEN , JAYASEKARA WIPUL PEMSIRI , KAI JAMES , MAKALA RAGHUVEER S , RABKIN PETER , SAMACHISA GEORGE , ZHANG JINGYAN
发明人： KREUPL FRANZ , BANDYOPADHYAY ABHIJIT , CHEN YUNG-TIN , FU CHU-CHEN , JAYASEKARA WIPUL PEMSIRI , KAI JAMES , MAKALA RAGHUVEER S , RABKIN PETER , SAMACHISA GEORGE , ZHANG JINGYAN
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L27/2409 , G11C11/16 , G11C11/1659 , G11C13/0007 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2481 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.
摘要翻译：三维读写存储器中的存储器件包括存储器单元。每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧具有第一和第二电阻转换层，并且在RSME的任一端具有第一和第二电极。第一和第二电阻切换层都可以具有双极性或单极性切换特性。在存储器单元的置位或复位操作中，离子电流在电阻切换层中流动，从而有助于切换机制。由于导电中间层的散射，对开关机构没有贡献的电子流被减少，以避免损坏导向元件。提供了用于RSME的不同层的特定材料和材料的组合。

84. 发明申请

WO2012087518A3 CHARGE PUMP SYSTEM THAT DYNAMICALLY SELECTS NUMBER OF ACTIVE STAGES 审中-公开
公开(公告)号：WO2012087518A3
公开(公告)日：2012-06-28
申请号：PCT/US2011/062662
申请日：2011-11-30
申请人： SANDISK 3D LLC , CAZZANIGA, Marco , LIU, Tz-Yi
发明人： CAZZANIGA, Marco , LIU, Tz-Yi
IPC分类号： H02M3/07 , G11C5/14
摘要： A multi-stage charge pump selects the number of active stages dynamically. In the exemplary embodiment, this is done by having a multi-stage master charge pump section (703) in which the number of active stages is settable and a slave charge pump section (723) that is of the same design as the master section. The master section (703) is used drive the external load (Vout), while the slave section drives an adjustable internal load (733). The adjustable load is set by control logic (749) by comparing the operation of the two sections. The control logic then operates the slave sections with a different number of active stages than the master stage in order to determine whether the master stage is using the optimal number of active stages. The control logic (749) can then change the number of active stages accordingly.

85. 发明申请

WO2012082770A1 NON-VOLATILE MEMORY HAVING 3D ARRAY OF READ/WRITE ELEMENTS WITH LOW CURRENT STRUCTURES AND METHODS THEREOF 审中-公开
标题翻译：具有低电流结构的读/写元件的三维阵列的非易失性存储器及其方法
公开(公告)号：WO2012082770A1
公开(公告)日：2012-06-21
申请号：PCT/US2011/064695
申请日：2011-12-13
申请人： SANDISK 3D LLC , SAMACHISA, George , ALSMEIER, Johann
发明人： SAMACHISA, George , ALSMEIER, Johann
IPC分类号： G11C13/00
CPC分类号： H01L27/11551 , G11C5/025 , G11C13/0002 , G11C13/0026 , G11C13/0028 , G11C2213/71 , H01L21/306 , H01L21/76224 , H01L27/11578 , H01L27/11582 , H01L27/2409 , H01L27/2454 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/1226 , H01L45/1273 , H01L45/144 , H01L45/146 , H01L45/149 , H01L45/1616
摘要： A three-dimensional array read/write (R/W) memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. It is preferable to operate the R/W elements with low current and high resistive states. The resistance of these resistive states depends also on the dimension of the R/W elements and is predetermined by the process technology. A sheet (400) electrode in series with the R/W element (430) and a method of forming it provide another degree of freedom to adjust the resistance of the R/W memory element (430). The thickness of the sheet electrode (400) is adjusted to obtain a reduced cross - sectional contact in the circuit path from the word line (470) to the bit line (440). This allows the R/W memory element (430) to have a much increased resistance and therefore to operate with much reduced currents. The sheet electrode (400) is formed with little increase in cell size.
摘要翻译：在位于半导体衬底上方不同距离的多个平面层上形成三维阵列读/写（R / W）存储元件。优选以低电流和高电阻状态操作R / W元件。这些电阻状态的电阻也取决于R / W元件的尺寸，并且由工艺技术预先确定。与R / W元件（430）串联的片（400）电极及其形成方法提供另一自由度来调节R / W存储元件（430）的电阻。调整片状电极（400）的厚度，以便在从字线（470）到位线（440）的电路中获得减小的横截面接触。这允许R / W存储器元件（430）具有大大增加的电阻，因此以大大减小的电流工作。片状电极（400）的形状几乎不增加电池的尺寸。

86. 发明申请

WO2012051159A1 THREE DIMENSIONAL HORIZONTAL DIODE NON-VOLATILE MEMORY ARRAY AND METHOD OF MAKING THEREOF 审中-公开
标题翻译：三维水平二极管非易失性存储器阵列及其制造方法
公开(公告)号：WO2012051159A1
公开(公告)日：2012-04-19
申请号：PCT/US2011/055721
申请日：2011-10-11
申请人： SANDISK 3D LLC , NGUYEN, Natalie , POON, Paul Wai Kie , RADIGAN, Steven J. , KONEVECKI, Michael , MAKALA, Raghuveer S.
发明人： NGUYEN, Natalie , POON, Paul Wai Kie , RADIGAN, Steven J. , KONEVECKI, Michael , MAKALA, Raghuveer S.
IPC分类号： H01L27/10 , H01L27/102
CPC分类号： H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/249
摘要： A non-volatile memory device contains a three dimensional stack of horizontal diodes located in a trench in an insulating material, a plurality of storage elements, a plurality of word lines extending substantially vertically, and a plurality of bit lines. Each of the plurality of bit lines has a first portion that extends up along at least one side of the trench and a second portion that extends substantially horizontally through the three dimensional stack of the horizontal diodes. Each of the horizontal diodes is a steering element of a respective non-volatile memory cell of the non-volatile memory device, and each of the plurality of storage elements is located adjacent to a respective steering element.
摘要翻译：非易失性存储器件包含位于绝缘材料沟槽中的水平二极管的三维堆叠，多个存储元件，基本垂直延伸的多条字线和多个位线。多个位线中的每一个具有沿着沟槽的至少一侧向上延伸的第一部分和基本水平延伸穿过水平二极管的三维叠层的第二部分。每个水平二极管是非易失性存储器件的相应非易失性存储单元的转向元件，并且多个存储元件中的每一个位于相应的转向元件附近。

87. 发明申请

WO2011159581A3 MEMORY CELL WITH RESISTANCE-SWITCHING LAYERS 审中-公开
标题翻译：具有电阻切换层的存储单元
公开(公告)号：WO2011159581A3
公开(公告)日：2012-04-19
申请号：PCT/US2011040103
申请日：2011-06-10
申请人： SANDISK 3D LLC , KREUPL FRANZ , COSTA XIYING , KAI JAMES , MAKALA RAGHUVEER S
发明人： KREUPL FRANZ , COSTA XIYING , KAI JAMES , MAKALA RAGHUVEER S
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L27/2409 , G11C11/16 , G11C11/1659 , G11C13/0007 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2481 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an electric field is applied across the first and second electrodes. An ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.
摘要翻译： 3-D读写存储器中的存储器件包括存储器单元。每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧上具有第一和第二电阻切换层，在RSME的任一端具有第一和第二电极。第一和第二电阻切换层都可以具有双极或单极开关特性。在存储单元的置位或复位操作中，跨越第一和第二电极施加电场。离子电流在电阻切换层中流动，有助于切换机构。由于导电中间层的散射，对切换机构无贡献的电子流减少，以避免损坏转向元件。提供了用于RSME不同层的材料和材料的组合。

88. 发明申请

WO2012044473A1 COUNTER DOPING COMPENSATION METHODS TO IMPROVE DIODE PERFORMANCE 审中-公开
标题翻译：计数器补偿方法提高二极管性能
公开(公告)号：WO2012044473A1
公开(公告)日：2012-04-05
申请号：PCT/US2011/051988
申请日：2011-09-16
申请人： SANDISK 3D, LLC , COSTA, Xiying , BANDYOPADHYAY, Abhijit , HOU, Kun , LE, Brian , CHEN, Yung-Tin
发明人： COSTA, Xiying , BANDYOPADHYAY, Abhijit , HOU, Kun , LE, Brian , CHEN, Yung-Tin
IPC分类号： H01L27/102 , H01L27/24 , H01L45/00
CPC分类号： H01L27/1021 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/149 , H01L45/1675
摘要： A method of forming a memory cell is provided, the method including forming a diode including a first region having a first conductivity type, counter-doping the diode to change the first region to a second conductivity type, and forming a memory element coupled in series with the diode. Other aspects are also provided.
摘要翻译：提供一种形成存储单元的方法，所述方法包括形成二极管，该二极管包括具有第一导电类型的第一区域，对二极管进行反掺杂以将第一区域改变为第二导电类型，以及形成串联耦合的存储元件与二极管。还提供其他方面。

89. 发明申请

WO2012024237A1 SINGLE DEVICE DRIVER CIRCUIT TO CONTROL THREE-DIMENSIONAL MEMORY ELEMENT ARRAY 审中-公开
标题翻译：单个设备驱动电路控制三维存储元件阵列
公开(公告)号：WO2012024237A1
公开(公告)日：2012-02-23
申请号：PCT/US2011/047788
申请日：2011-08-15
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy
发明人： SCHEUERLEIN, Roy
IPC分类号： G11C13/00
CPC分类号： G11C13/0026 , B82Y10/00 , G11C7/12 , G11C13/0004 , G11C13/0007 , G11C13/0028 , G11C13/0038 , G11C13/025 , G11C17/165 , G11C2013/0073 , G11C2213/35 , G11C2213/71 , G11C2213/72 , H01L27/0688
摘要： A memory device includes diode plus resistivity switching element memory cells coupled between bit and word lines, single device bit line drivers (163) with gates coupled to a bit line decoder (120) control lead (322), sources/drains coupled to a bit line driver (304), and drains/sources coupled to bit lines, single device word line drivers with gates coupled to a word line decoder control lead, sources/drains coupled to a word line driver output, and drains/sources coupled to word lines, a first bleeder diode (300) coupled between a bit line and a first bleeder diode controller (314), and a second bleeder diode coupled between a word line and a second bleeder diode controller. The first bleeder diode controller (314) connects the first bleeder diode (300) to low voltage (305) in response to a bit line decoder signal. The second bleeder diode controller connects the second bleeder diode to high voltage in response to a word line decoder signal.
摘要翻译：存储器件包括耦合在位线和字线之间的二极管加上电阻率开关元件存储单元，单个器件位线驱动器（163），其栅极耦合到位线解码器（120）控制引线（322），耦合到位线路驱动器（304），以及耦合到位线的漏极/源极，具有耦合到字线解码器控制引线的栅极的单个器件字线驱动器，耦合到字线驱动器输出的源极/漏极以及耦合到字线的漏极/源极耦合在位线和第一泄放二极管控制器（314）之间的第一泄放二极管（300）和耦合在字线和第二泄放二极管控制器之间的第二泄放二极管（300）。响应于位线解码器信号，第一泄放二极管控制器（314）将第一泄放二极管（300）连接到低电压（305）。第二泄放二极管控制器响应于字线解码器信号将第二泄放二极管连接到高电压。

90. 发明申请

WO2011159584A1 MEMORY CELL WITH RESISTANCE-SWITCHING LAYERS INCLUDING BREAKDOWN LAYER 审中-公开
标题翻译：具有电阻切换层的存储单元，包括断层
公开(公告)号：WO2011159584A1
公开(公告)日：2011-12-22
申请号：PCT/US2011/040107
申请日：2011-06-10
申请人： SANDISK 3D LLC , KREUPL, Franz , FU, Chu-Chen , NIAN, Yibo
发明人： KREUPL, Franz , FU, Chu-Chen , NIAN, Yibo
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L27/2409 , G11C11/16 , G11C11/1659 , G11C13/0007 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2481 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has a resistance-switching layer, a conductive intermediate layer, and first and second electrodes at either end of the RSME. A breakdown layer is electrically between, and in series with, the second electrode and the intermediate layer. The breakdown layer maintains a resistance of at least about 1-10 ΜΩ while in a conductive state. In a set or reset operation of the memory cell, an ionic current flows in the resistance- switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.
摘要翻译： 3-D读写存储器中的存储器件包括存储器单元。每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME具有电阻切换层，导电中间层以及在RSME的任一端的第一和第二电极。击穿层在第二电极和中间层之间电连接并与其串联。在导通状态下，击穿层保持至少约1-10Ω的电阻。在存储单元的置位或复位操作中，离子电流在电阻切换层中流动，有助于切换机制。由于导电中间层的散射，对切换机构无贡献的电子流减少，以避免损坏转向元件。提供了用于RSME不同层的材料和材料的组合。

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