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1. 发明申请

WO2009045347A1 METHOD FOR REDUCING PILLAR STRUCTURE DIMENSIONS OF A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：减少半导体器件的支柱结构尺寸的方法
公开(公告)号：WO2009045347A1
公开(公告)日：2009-04-09
申请号：PCT/US2008/011215
申请日：2008-09-26
申请人： SANDISK 3D LLC , CHEN, Yung-tin , CHAN, Michael , POON, Paul , RADIGAN, Steven, J.
发明人： CHEN, Yung-tin , CHAN, Michael , POON, Paul , RADIGAN, Steven, J.
IPC分类号： H01L21/027 , G03F7/40
CPC分类号： H01L21/0274 , G03F7/40
摘要： A method creates pillar structures on a semiconductor wafer and includes the steps of providing a layer of semiconductor. A layer of photoresist is applied over the layer of semiconductor. The layer of photoresist is exposed with an initial pattern of light to effect the layer of photoresist. The photoresist layer is then etched away to provide a photoresist pattern to create the pillar structures. The photoresist pattern is processed in the layer of photoresist after the step of exposing the layer of photoresist and prior to the step of etching to reduce the dimensions of the photoresist pattern in the layer of photoresist.
摘要翻译：一种方法在半导体晶片上形成柱结构，并且包括提供半导体层的步骤。一层光致抗蚀剂被施加在半导体层上。光致抗蚀剂层用初始图案曝光以实现光致抗蚀剂层。然后蚀刻掉光致抗蚀剂层以提供光致抗蚀剂图案以产生柱结构。在曝光光致抗蚀剂层的步骤之前和蚀刻步骤之前，在光致抗蚀剂层中处理光致抗蚀剂图案，以减小光致抗蚀剂层中的光刻胶图案的尺寸。

2. 发明申请

WO2006105326A1 MASKING OF REPEATED OVERLAY AND ALIGNMENT MARKS TO ALLOW REUSE OF PHOTOMASKS IN A VERTICAL STRUCTURE 审中-公开
标题翻译：重复覆盖和对准标记的掩蔽以允许在垂直结构中重新使用光刻胶
公开(公告)号：WO2006105326A1
公开(公告)日：2006-10-05
申请号：PCT/US2006/011715
申请日：2006-03-31
申请人： SANDISK 3D, LLC , CHEN, Yung-Tin , PETTI, Christopher, J. , RADIGAN, Steven, J. , KUMAR, Tanmay
发明人： CHEN, Yung-Tin , PETTI, Christopher, J. , RADIGAN, Steven, J. , KUMAR, Tanmay
IPC分类号： G03F9/00 , G03F7/20 , H01L23/00
CPC分类号： H01L27/0688 , G03F7/70633 , G03F9/7084 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/5446
摘要： In formation of monolithic three dimensional memory arrays, a photomask may be used more than once. Reuse of a photomask creates second, third or more instances of reference marks used by the stepper to achieve alignment (alignment marks) and to measure alignment achieved (overlay marks) directly above prior instances of the same reference mark. The prior instances of the same reference mark may cause interference with the present instance of the reference mark, complicating alignment and measurement. Using the methods of the present invention, blocking structure is created vertically interposed between subsequent instances of the same reference mark, preventing interference.
摘要翻译：在形成单片三维存储器阵列时，可以使用光掩模多于一次。重新使用光掩模创建步进器使用的第二，第三或更多个参考标记实例，以实现对齐（对齐标记）并且直接在相同参考标记的先前实例之上测量对齐（覆盖标记）。相同参考标记的先前实例可能引起对参考标记的当前实例的干扰，使对准和测量复杂化。使用本发明的方法，垂直地插入相同参考标记的后续实例之间的阻挡结构，以防止干扰。

3. 发明申请

WO2009078896A1 METHOD FOR FABRICATING PITCH-DOUBLING PILLAR STRUCTURES 审中-公开
标题翻译：用于制作PITCH-DOUBLING PILLAR STRUCTURES的方法
公开(公告)号：WO2009078896A1
公开(公告)日：2009-06-25
申请号：PCT/US2008/012476
申请日：2008-11-05
申请人： SANDISK 3D LLC , PETTI, Christopher, J. , RADIGAN, Steven, J.
发明人： PETTI, Christopher, J. , RADIGAN, Steven, J.
IPC分类号： H01L27/102 , H01L21/033 , H01L21/308
CPC分类号： H01L27/102 , H01L21/0337
摘要： A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature, selectively removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the at least one device layer using the first feature, the filler feature and the second feature as a mask.
摘要翻译：制造半导体器件的方法包括在衬底上形成至少一个器件层，在所述至少一个器件层上形成至少两个间隔开的特征，在所述至少两个特征上形成侧壁间隔物，填充第一侧壁第一特征上的间隔物和具有填充物特征的第二特征上的第二侧壁间隔物，选择性地移除侧壁间隔物以留下第一特征，填料特征和第二特征彼此间隔开，并且蚀刻至少一个装置层，使用第一特征，填充特征和第二特征作为掩模。

4. 发明申请

WO2009003091A1 METHOD FOR FABRICATING A 3-D INTEGRATED CIRCUIT USING A HARD MASK OF SILICON-OXYNITRIDE ON AMORPHOUS CARBON 审中-公开
标题翻译：使用硅氧烷在非晶碳上的硬掩模制造三维集成电路的方法
公开(公告)号：WO2009003091A1
公开(公告)日：2008-12-31
申请号：PCT/US2008/068307
申请日：2008-06-26
申请人： SANDISK CORPORATION , RADIGAN, Steven, J. , KONEVECKI, Michael, W.
发明人： RADIGAN, Steven, J. , KONEVECKI, Michael, W.
IPC分类号： H01L21/331 , H01L21/82 , H01L29/76
CPC分类号： H01L27/1021 , H01L23/5252 , H01L27/0688 , H01L29/8615 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a 3-D monolithic memory device. Silicon- oxynitride (Si x O y N z ) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide, and tungsten. A silicon-oxynitride layer is etched using a photoresist layer, and the resulting etched Si x O y N z layer is used to etch an amorphous carbon layer. Silicon, oxide, and/or tungsten layers are etched using the amorphous carbon layer. In one implementation, conductive rails of the 3-D monolithic memory device are formed by etching an oxide layer such as silicon dioxide (SiO 2 ) using the patterned amorphous carbon layer as a hard mask. Memory cell diodes are formed as pillars in polysilicon between the conductive rails by etching a polysilicon layer using another patterned amorphous carbon layer as a hard mask. Additional levels of conductive rails and memory cell diodes are formed similarly to build the 3-D monolithic memory device.
摘要翻译：一种用于制造3-D单片存储器件的方法。无定形碳上的氮氧化硅（SixOyNz）被用作对硅，氧化物和钨具有高选择性的有效的，容易移除的硬掩模。使用光致抗蚀剂层蚀刻硅 - 氧氮化物层，并且使用所得到的蚀刻的六方氮化物层来蚀刻无定形碳层。使用无定形碳层蚀刻硅，氧化物和/或钨层。在一个实施方案中，通过使用图案化的非晶碳层作为硬掩模来蚀刻诸如二氧化硅（SiO 2）的氧化物层来形成3-D单片存储器件的导电轨道。通过使用另一图案化的非晶碳层作为硬掩模蚀刻多晶硅层，在导电轨道之间的多晶硅中形成存储单元二极管。与构建3-D单片存储器件类似地形成附加电平的导电轨和存储单元二极管。

5. 发明申请

WO2011008767A3 METHOD OF MAKING DAMASCENE DIODES USING SACRIFICIAL MATERIAL 审中-公开
标题翻译：使用真空材料制备大分子二极体的方法
公开(公告)号：WO2011008767A3
公开(公告)日：2011-12-29
申请号：PCT/US2010041836
申请日：2010-07-13
申请人： SANDISK 3D LLC , MAKALA RAGHUVEER , DUNTON VANCE , TANAKA YOICHIRO , MAXWELL STEVEN , ZHANG TONG , RADIGAN STEVEN J
发明人： MAKALA RAGHUVEER , DUNTON VANCE , TANAKA YOICHIRO , MAXWELL STEVEN , ZHANG TONG , RADIGAN STEVEN J
IPC分类号： H01L27/10 , H01L27/24
CPC分类号： H01L27/1021 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/149 , H01L45/16
摘要： A method of making a semiconductor device includes forming a first layer comprising a seed material over an underlying layer, forming a second layer comprising a sacrificial material over the first layer, the sacrificial material being different from the seed material, patterning the first layer and the second layer into a plurality of separate features, forming an insulating filling material between the plurality of the separate features, removing the sacrificial material from the separate features to form a plurality of openings in the insulating filling material such that the seed material is exposed in the plurality of openings, and growing a semiconductor material on the exposed seed material in the plurality of openings.
摘要翻译：制造半导体器件的方法包括在下层上形成包括种子材料的第一层，在第一层上形成包括牺牲材料的第二层，牺牲材料不同于种子材料，图案化第一层和在多个单独的特征之间形成绝缘填充材料，从所述分离的特征中移除所述牺牲材料以在所述绝缘填充材料中形成多个开口，使得所述种子材料暴露在所述第二层中多个开口，以及在多个开口中的暴露的种子材料上生长半导体材料。

6. 发明申请

WO2011008767A2 METHOD OF MAKING DAMASCENE DIODES USING SACRIFICIAL MATERIAL 审中-公开
标题翻译：使用牺牲材料制造大马士革二极管的方法
公开(公告)号：WO2011008767A2
公开(公告)日：2011-01-20
申请号：PCT/US2010/041836
申请日：2010-07-13
申请人： SANDISK 3D LLC , MAKALA, Raghuveer , DUNTON, Vance , TANAKA, Yoichiro , MAXWELL, Steven , ZHANG, Tong , RADIGAN, Steven, J.
发明人： MAKALA, Raghuveer , DUNTON, Vance , TANAKA, Yoichiro , MAXWELL, Steven , ZHANG, Tong , RADIGAN, Steven, J.
IPC分类号： H01L27/10
CPC分类号： H01L27/1021 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/149 , H01L45/16
摘要： A method of making a semiconductor device includes forming a first layer comprising a seed material over an underlying layer, forming a second layer comprising a sacrificial material over the first layer, the sacrificial material being different from the seed material, patterning the first layer and the second layer into a plurality of separate features, forming an insulating filling material between the plurality of the separate features, removing the sacrificial material from the separate features to form a plurality of openings in the insulating filling material such that the seed material is exposed in the plurality of openings, and growing a semiconductor material on the exposed seed material in the plurality of openings.
摘要翻译：制造半导体器件的方法包括：在底层上形成包括种子材料的第一层;在第一层上形成包括牺牲材料的第二层，牺牲材料不同于种子将第一层和第二层图案化成多个分离的特征;在多个分离的特征之间形成绝缘填充材料;从分离的特征移除牺牲材料以在绝缘填充材料中形成多个开口; 种子材料暴露在多个开口中，并且在暴露的种子材料上在多个开口中生长半导体材料。

7. 发明申请

WO2009045348A1 LINER FOR TUNGSTEN/SILICON DIOXIDE INTERFACE IN MEMORY 审中-公开
标题翻译：内存中的TUNGSTEN /二氧化硅界面
公开(公告)号：WO2009045348A1
公开(公告)日：2009-04-09
申请号：PCT/US2008/011216
申请日：2008-09-26
申请人： SANDISK 3D LLC , TANAKA, Yoichiro , RADIGAN, Steven, J. , RAGHURAM, Usha
发明人： TANAKA, Yoichiro , RADIGAN, Steven, J. , RAGHURAM, Usha
IPC分类号： H01L27/102
CPC分类号： H01L27/101 , H01L27/1021
摘要： A semiconductor wafer assembly includes a base of dielectric. A layer of silicon is deposited thereover. A metal hard mask is deposited over the silicon. A dielectric hard mask is deposited over the metal hard mask. Photoresist is deposited over the dielectric hard mask, whereby a plurality of sacrificial columns is formed from the layer of metal hard mask through the photoresist such that the sacrificial columns extend out from the silicon layer. An interface layer is disposed between the layer of conductive material and the layer of hard mask to enhance adhesion between each of the plurality of sacrificial columns and the layer of conductive material to optimize the formation of junction diodes out of the silicon by preventing the plurality of sacrificial columns from being detached from the layer of silicon prematurely due to the sacrificial columns peeling or falling off.
摘要翻译：半导体晶片组件包括电介质基体。一层硅沉积在其上。金属硬掩模沉积在硅上。电介质硬掩模沉积在金属硬掩模上。光致抗蚀剂沉积在电介质硬掩模上，由此通过光致抗蚀剂从金属硬掩模层形成多个牺牲柱，使得牺牲柱从硅层延伸出来。界面层设置在导电材料层和硬掩模层之间，以增强多个牺牲柱和导电材料层之间的粘附力，以通过防止多个牺牲柱由于牺牲柱脱落或脱落而过早地与硅层分离。

8. 发明申请

WO2007143387A2 CONDUCTIVE HARD MASK TO PROTECT PATTERNED FEATURES DURING TRENCH ETCH 审中-公开
标题翻译：导电硬掩模，以保护在TRENCH ETCH期间的图案特征
公开(公告)号：WO2007143387A2
公开(公告)日：2007-12-13
申请号：PCT/US2007069450
申请日：2007-05-22
申请人： SANDISK 3D LLC , RADIGAN STEVEN J , RAGHURAM USHA , DUNTON SAMUEL V , KONEVECKI MICHAEL W
发明人： RADIGAN STEVEN J , RAGHURAM USHA , DUNTON SAMUEL V , KONEVECKI MICHAEL W
IPC分类号： H01L27/102 , H01L21/768
CPC分类号： H01L23/5252 , H01L27/1021 , H01L29/6609 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for forming patterned features using a conductive hard mask, where the conductive hard mask protects those features during a subsequent trench etch to form Damascene conductors providing electrical connection to those features from above. The thickness of the hard mask provides a margin to avoid overetch during the trench etch which may be harmful to device performance. The method is advantageously used in formation of a monolithic three dimensional memory array.
摘要翻译：提供了一种使用导电硬掩模形成图案化特征的方法，其中导电硬掩模在随后的沟槽蚀刻期间保护这些特征以形成提供从上方到那些特征的电连接的大马士革导体。硬掩模的厚度提供了一个余量，以避免在沟槽蚀刻期间的过蚀刻，这可能对器件性能有害。该方法有利地用于形成单片三维存储器阵列。

9. 发明申请

WO2012051159A1 THREE DIMENSIONAL HORIZONTAL DIODE NON-VOLATILE MEMORY ARRAY AND METHOD OF MAKING THEREOF 审中-公开
标题翻译：三维水平二极管非易失性存储器阵列及其制造方法
公开(公告)号：WO2012051159A1
公开(公告)日：2012-04-19
申请号：PCT/US2011/055721
申请日：2011-10-11
申请人： SANDISK 3D LLC , NGUYEN, Natalie , POON, Paul Wai Kie , RADIGAN, Steven J. , KONEVECKI, Michael , MAKALA, Raghuveer S.
发明人： NGUYEN, Natalie , POON, Paul Wai Kie , RADIGAN, Steven J. , KONEVECKI, Michael , MAKALA, Raghuveer S.
IPC分类号： H01L27/10 , H01L27/102
CPC分类号： H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/249
摘要： A non-volatile memory device contains a three dimensional stack of horizontal diodes located in a trench in an insulating material, a plurality of storage elements, a plurality of word lines extending substantially vertically, and a plurality of bit lines. Each of the plurality of bit lines has a first portion that extends up along at least one side of the trench and a second portion that extends substantially horizontally through the three dimensional stack of the horizontal diodes. Each of the horizontal diodes is a steering element of a respective non-volatile memory cell of the non-volatile memory device, and each of the plurality of storage elements is located adjacent to a respective steering element.
摘要翻译：非易失性存储器件包含位于绝缘材料沟槽中的水平二极管的三维堆叠，多个存储元件，基本垂直延伸的多条字线和多个位线。多个位线中的每一个具有沿着沟槽的至少一侧向上延伸的第一部分和基本水平延伸穿过水平二极管的三维叠层的第二部分。每个水平二极管是非易失性存储器件的相应非易失性存储单元的转向元件，并且多个存储元件中的每一个位于相应的转向元件附近。

10. 发明申请

WO2011088050A2 PATTERNING METHOD FOR HIGH DENSITY PILLAR STRUCTURES 审中-公开
标题翻译：高密度支柱结构的方法
公开(公告)号：WO2011088050A2
公开(公告)日：2011-07-21
申请号：PCT/US2011/020848
申请日：2011-01-11
申请人： SANDISK 3D LLC , NGUYEN, Natalie , POON, Paul Wai Kie , RADIGAN, Steven J. , KONEVECKI, Michael , CHEN, Yung-Tin , MAKALA, Raghuveer , DUNTON, Vance
发明人： NGUYEN, Natalie , POON, Paul Wai Kie , RADIGAN, Steven J. , KONEVECKI, Michael , CHEN, Yung-Tin , MAKALA, Raghuveer , DUNTON, Vance
IPC分类号： H01L21/027
CPC分类号： H01L21/0274 , H01L21/0337 , H01L27/1021 , Y10S438/947 , Y10S438/948 , Y10S438/949
摘要： A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.
摘要翻译：制造器件的方法包括在牺牲层上形成第一光致抗蚀剂层，图案化第一光致抗蚀剂层以形成第一光致抗蚀剂特征，使得第一光致抗蚀剂特征不溶于溶剂，在第一光致抗蚀剂特征上形成第二光致抗蚀剂层，第二光致抗蚀剂层以形成第二光致抗蚀剂特征，在第一和第二光致抗蚀剂特征上形成间隔层，蚀刻间隔层以形成间隔物特征并暴露第一和第二光致抗蚀剂特征，在间隔物特征之间形成第三光致抗蚀剂特征，去除间隔物特征，并且使用第一，第二和第三光致抗蚀剂特征作为掩模来图案化牺牲层以形成牺牲特征。

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