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1. 发明申请

WO2012087518A3 CHARGE PUMP SYSTEM THAT DYNAMICALLY SELECTS NUMBER OF ACTIVE STAGES 审中-公开
公开(公告)号：WO2012087518A3
公开(公告)日：2012-06-28
申请号：PCT/US2011/062662
申请日：2011-11-30
申请人： SANDISK 3D LLC , CAZZANIGA, Marco , LIU, Tz-Yi
发明人： CAZZANIGA, Marco , LIU, Tz-Yi
IPC分类号： H02M3/07 , G11C5/14
摘要： A multi-stage charge pump selects the number of active stages dynamically. In the exemplary embodiment, this is done by having a multi-stage master charge pump section (703) in which the number of active stages is settable and a slave charge pump section (723) that is of the same design as the master section. The master section (703) is used drive the external load (Vout), while the slave section drives an adjustable internal load (733). The adjustable load is set by control logic (749) by comparing the operation of the two sections. The control logic then operates the slave sections with a different number of active stages than the master stage in order to determine whether the master stage is using the optimal number of active stages. The control logic (749) can then change the number of active stages accordingly.

2. 发明申请

WO2012129083A1 CONDITIONAL PROGRAMMING OF MULTIBIT MEMORY CELLS 审中-公开
标题翻译：多位记忆细胞的条件编程
公开(公告)号：WO2012129083A1
公开(公告)日：2012-09-27
申请号：PCT/US2012/029416
申请日：2012-03-16
申请人： SANDISK 3D LLC , COSTA, Xiying , NIAN, Yibo , SCHEUERLEIN, Roy , LIU, Tz-Yi , GORLA, Chandrasekhar, Reddy
发明人： COSTA, Xiying , NIAN, Yibo , SCHEUERLEIN, Roy , LIU, Tz-Yi , GORLA, Chandrasekhar, Reddy
IPC分类号： G11C11/56 , G11C13/00
CPC分类号： G11C13/0069 , G11C11/56 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0007 , G11C13/0064 , G11C2013/0071 , G11C2013/0073 , G11C2013/0076 , G11C2013/0092 , G11C2213/32
摘要： Improved methods for programming multi-level metal oxide memory cells balance applied voltage and current to provide improved performance. Set programming, which transitions the memory cell to a lower resistance state, is accomplished by determining an appropriate programming voltage and current limit for the objective resistance state to be achieved in the programming and then applying a pulse having the determined set electrical characteristics. Reset programming, which transitions the memory cell to a higher resistance state, is accomplished by determining an appropriate programming voltage and optionally current limit for the state to be achieved in the programming and then applying a pulse having the determined electrical characteristics. The algorithm used to determine the appropriate set or reset programming voltage and current values provides for effective programming without stressing the memory element. The electrical characteristics for programming pulses may be stored in a data table used in a table look up algorithm.
摘要翻译：改进的多级金属氧化物存储单元的编程方法平衡施加的电压和电流，以提供更好的性能。通过为编程中要实现的目标电阻状态确定适当的编程电压和电流限制，然后施加具有确定的设定电气特性的脉冲来实现将存储器单元转换到较低电阻状态的设置编程。将存储器单元转换到较高电阻状态的复位编程通过确定编程中要实现的状态的适当编程电压和可选的电流限制，然后施加具有确定的电特性的脉冲来实现。用于确定适当的设置或复位编程电压和电流值的算法提供有效的编程，而不会对存储元件造成影响。编程脉冲的电气特性可以存储在表查找算法中使用的数据表中。

3. 发明申请

WO2016053533A1 APPARATUS AND METHODS FOR SENSING HARD BIT AND SOFT BITS 审中-公开
标题翻译：用于传感硬头和软件位置的装置和方法
公开(公告)号：WO2016053533A1
公开(公告)日：2016-04-07
申请号：PCT/US2015/047626
申请日：2015-08-30
申请人： SANDISK 3D LLC
发明人： SIAU, Chang , LEE, Jeffrey Koon Yee , YAN, Tianhong , CHEN, Yingchang , BALAKRISHNAN, Gopinath , LIU, Tz-Yi
IPC分类号： G11C11/16 , G11C13/00 , G11C16/28 , G11C16/32
CPC分类号： G11C13/004 , G11C13/0028 , G11C13/0061 , G11C16/28 , G11C16/32 , G11C27/02 , G11C2013/0054
摘要： A method is provided for reading a hard bit and N soft bits of a memory cell of a nonvolatile memory system in response to a single read command in a total time corresponding to a single read latency period and N + 1 data transfer times, the method comprising: generating a sense signal proportional to a current of the memory cell; generating a reference signal that comprises 2N + 1 distinct reference signal values; generating a comparison signal by comparing the sense signal and the reference signal; sampling the comparison signal to generate 2N + 1 data values; and determining the hard bit and the N soft bits based on the 2N + 1 data values.
摘要翻译：提供了一种用于在对应于单个读等待时间周期和N + 1个数据传送时间的总时间内响应于单个读取命令来读取非易失性存储器系统的存储器单元的硬比特和N个软比特的方法，该方法包括：产生与所述存储器单元的电流成比例的感测信号; 生成包括2N + 1个不同参考信号值的参考信号; 通过比较感测信号和参考信号来产生比较信号; 对比较信号进行采样以产生2N + 1个数据值; 以及基于2N + 1个数据值来确定硬比特和N个软比特。

4. 发明申请

WO2014149585A1 PROGRAM CYCLE SKIP EVALUATION BEFORE WRITE OPERATIONS IN NON-VOLATILE MEMORY 审中-公开
标题翻译：在非易失性存储器中的编写操作之前的程序循环跳转评估
公开(公告)号：WO2014149585A1
公开(公告)日：2014-09-25
申请号：PCT/US2014/019740
申请日：2014-03-01
申请人： SANDISK 3D LLC
发明人： BALAKRISHNAN, Gopinath , LIU, Tz-Yi , ZHANG, Henry
IPC分类号： G11C13/00
CPC分类号： G11C7/06 , G11C7/1006 , G11C7/1087 , G11C13/0061 , G11C13/0069 , G11C2013/0076 , G11C2013/0088 , G11C2213/71
摘要： A non-volatile memory system is disclosed that evaluates during a read before write operation whether to skip programming of portions of group of memory cells during a subsequent write operation. By evaluating skip information during a read before write operation, the write operation can be expedited. The additional overhead for evaluating skip information is consumed during the read before write operation. By performing a skip evaluation during the read before write operation, a full analysis of the availability of skipping programming for memory cells can be performed. Skip evaluations in different embodiments may be performed for entire bay address cycles, column address cycles, and/or sense amplifier address cycles. In some embodiments, some skip evaluations are performed during read before write operations while others are deferred to the write operation. In this manner, the number of data latches for storing skip information can be decreased.
摘要翻译：公开了一种非易失性存储器系统，其在写操作期间的读取期间评估是否在随后的写入操作期间跳过存储器单元组的部分的编程。通过在写入操作期间读取期间评估跳过信息，可以加速写入操作。用于评估跳过信息的额外开销在写入操作期间被读取。通过在写操作期间执行跳过评估，可以执行对存储器单元的跳过编程的可用性的全面分析。可以在整个托架地址周期，列地址周期和/或读出放大器地址周期中执行不同实施例中的跳过评估。在一些实施例中，在写入操作期间的读取期间执行一些跳过评估，而其他跳过评估被推迟到写入操作。以这种方式，可以减少用于存储跳过信息的数据锁存器的数量。

5. 发明申请

WO2014149586A1 DYNAMIC ADDRESS GROUPING FOR PARALLEL PROGRAMMING IN NON-VOLATILE MEMORY 审中-公开
标题翻译：在非易失性存储器中并行编程的动态地址分组
公开(公告)号：WO2014149586A1
公开(公告)日：2014-09-25
申请号：PCT/US2014/019741
申请日：2014-03-01
申请人： SANDISK 3D LLC
发明人： BALAKRISHNAN, Gopinath , LIU, Tz-Yi
IPC分类号： G11C7/10 , G11C13/00
CPC分类号： G06F12/0246 , G11C7/1006 , G11C13/0007 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/0076 , G11C2013/0088 , G11C2213/71
摘要： A non-volatile memory system evaluates user data before writing in order to potentially group addresses for writing within a cycle. The system can determine which sense amplifier addresses of a column address will be programmed in a column address cycle. The number of bits that will be programmed is compared with an allowable number of parallel bits. The system generates groups of sense amplifier addresses based on the comparison. The system generates groups that include a total number of bits to be programmed that is within the allowable number of parallel bits. Each group is programmed in one sense amplifier address cycle. Multiple sense amplifier addresses can be grouped for programming while still remaining within an allowable number of parallel programming bits. The system performs a read before write operation and generates bitmap data for the grouping information corresponding sense amplifier addresses.
摘要翻译：非易失性存储器系统在写入之前评估用户数据，以便在一个周期内潜在的组地址进行写入。该系统可以确定在列地址周期中将编程列地址的哪个读出放大器地址。将编程的位数与允许的并行位数进行比较。该系统基于比较产生一组读出放大器地址。系统生成组，其中包括要编程的总位数在允许的并行位数内。每组在一个读出放大器地址周期中进行编程。多个读出放大器地址可以分组编程，同时仍然保留在允许的并行编程位数中。该系统在写入操作之前进行读取，并产生对应读出放大器地址的分组信息的位图数据。

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