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11. 发明申请

WO2008058847A1 A CMOS IMAGER ARRAY WITH RECESSED DIELECTRIC LAYER 审中-公开
标题翻译：带有电介质层的CMOS图像阵列
公开(公告)号：WO2008058847A1
公开(公告)日：2008-05-22
申请号：PCT/EP2007/061705
申请日：2007-10-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , GAMBINO, Jeffrey, Peter , ADKISSON, James, William , SPROGIS, Edmund, Juris , RASSEL, Richard, John , LEIDY, Robert, Kenneth , JAFFE, Mark, David , LUCE, Stephen, Ellinwood , HE, Zhong-Xiang
发明人： GAMBINO, Jeffrey, Peter , ADKISSON, James, William , SPROGIS, Edmund, Juris , RASSEL, Richard, John , LEIDY, Robert, Kenneth , JAFFE, Mark, David , LUCE, Stephen, Ellinwood , HE, Zhong-Xiang
IPC分类号： H01L27/146
CPC分类号： H01L27/14687 , H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14632 , H01L27/14685 , H01L2224/05001 , H01L2224/05008 , H01L2224/05124 , H01L2224/05548 , H01L2224/05569 , H01L2224/05647 , H01L2224/13 , H01L2924/00014
摘要： A CMOS image sensor array and method of fabrication. The CMOS imager sensor array comprises a substrate; an array of light receiving pixel structures formed above the substrate, the array having formed therein "m" levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer; a dense logic wiring region formed adjacent to the array of light receiving pixel structures having "n" levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer, where n>m. A microlens array having microlenses and color filters formed above the interlevel dielectric material layer, a microlens and respective color filter in alignment with a respective light receiving structure formed at a surface of the substrate. A top surface of the interlevel dielectric material layer beneath the microlens array is recessed from a top surface of the interlevel dielectric material layers of the dense logic wiring region.
摘要翻译： CMOS图像传感器阵列及其制造方法。 CMOS成像器传感器阵列包括衬底; 形成在衬底上方的光接收像素结构的阵列，阵列中形成有“m”级的导电结构，每个层形成在相应的层间介电材料层中; 与具有“n”级的导电结构的光接收像素结构的阵列相邻形成的密集的逻辑布线区域，每个层级形成在相应的层间电介质材料层中，其中n> m。具有形成在层间电介质材料层上方的微透镜和滤色器的微透镜阵列，与形成在衬底表面处的各个光接收结构对准的微透镜和相应的滤色器。微透镜阵列下面的层间介电材料层的顶表面从密集逻辑布线区域的层间介电材料层的顶表面凹陷。

12. 发明申请

WO2007083432A1 弾性表面波装置及び弾性境界波装置审中-公开
标题翻译：表面声波装置和边界声波装置
公开(公告)号：WO2007083432A1
公开(公告)日：2007-07-26
申请号：PCT/JP2006/322383
申请日：2006-11-09
申请人：株式会社村田製作所 , 田中伸拓
发明人：田中伸拓
IPC分类号： H03H9/72 , H03H9/25
CPC分类号： H03H9/725 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05026 , H01L2224/05085 , H01L2224/05144 , H01L2224/05166 , H01L2224/05569 , H01L2224/0557 , H01L2224/05571 , H01L2224/11 , H01L2924/00014 , H03H9/0576 , H03H9/1092 , H01L2224/05599
摘要：　容量結合を低減することができる弾性表面波装置及び弾性境界波装置を提供する。　圧電基板１２とカバー３２とが、支持層３０を介して間隔を設けて結合されている。圧電基板１２のカバー３２に対向する主面１４には、支持層３０の内側に、送信側弾性表面波フィルタと受信側弾性表面波フィルタとが形成されている。カバー３２に関して圧電基板１２とは反対側に、送信側弾性表面波フィルタ及び受信側弾性表面波フィルタに電気的に接続されたアンテナ端子と、送信側弾性表面波フィルタに電気的に接続された送信入力端子と、受信側弾性表面波フィルタに電気的に接続された受信出力端子とを含む外部電極２８が形成されている。受信側弾性表面波フィルタとアンテナ端子とを電気的に接続する配線の一部が、カバー３２に設けられている。
摘要翻译：可以减小电容耦合的表面声波装置和弹性边界波装置。压电基板（12）和盖（32）以一定间隔通过支撑层（30）连接。在面向盖（32）的压电基板（12）的主表面（14）上，在支撑层（30）的内侧形成有透射侧声表面波滤波器和接收侧声表面波滤波器。在与压电基板（12）相对于盖（32）相对的一侧，包括与发送侧声表面波滤波器和接收侧声表面波滤波器电连接的天线端子的外部电极（28），与发送侧声表面波滤波器电连接的发送输入端子和与接收侧声表面波滤波器电连接的接收输出端子。用于电连接接收侧声表面波滤波器和天线元件的布线的一部分设置在盖（32）上。

13. 发明申请

WO2006064711A1 めっき装置、めっき方法、半導体装置、及び半導体装置の製造方法审中-公开
标题翻译：镀层器件，镀覆方法，半导体器件和半导体器件制造方法
公开(公告)号：WO2006064711A1
公开(公告)日：2006-06-22
申请号：PCT/JP2005/022539
申请日：2005-12-08
申请人：シャープ株式会社 , 岩崎良英
发明人：岩崎良英
IPC分类号： C25D17/00 , C25D5/08 , C25D7/12 , C25D17/10 , H01L21/288
CPC分类号： H01L24/11 , C25D5/02 , C25D5/08 , C25D7/123 , C25D17/001 , C25D17/002 , C25D17/02 , C25D17/10 , C25D21/06 , H01L21/2885 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05147 , H01L2224/05166 , H01L2224/05171 , H01L2224/05184 , H01L2224/05548 , H01L2224/05569 , H01L2224/05647 , H01L2224/1148 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/00014 , H01L2924/013
摘要：　フェースダウン方式の噴流めっき装置において、操作性を損なうことなく、ブラックフィルム等に起因する微小な固形異物による、めっき品質の低下を防止することを目的とし、本発明のめっき装置は、フェースダウン方式のめっき装置において、半導体ウェハ（１）と陽極電極（５）との間に、隔壁（７）が設けられており、陽極電極（５）と半導体ウェハ（１）とが隔壁（７）により隔離され、めっき処理槽（１００）が被めっき基板室と陽極電極室とに区分された構成になっている。
摘要翻译：在面朝下型喷镀装置中，可以防止由于黑色膜引起的微小固体异物而导致的电镀质量降低。在面朝下电镀装置中，在半导体晶片（1）和阳极电极（5）之间设置分隔壁（7），使得阳极电极（5）通过隔板与半导体晶片（1）分离墙（7）。电镀浴（100）被分为要被镀的基底室和阳极电极室。

14. 发明申请

WO2005048348A1 ELECTRONIC PACKAGING MATERIALS FOR USE WITH LOW-K DIELECTRIC-CONTAINING SEMICONDUCTOR DEVICES 审中-公开
标题翻译：用于低K电介质半导体器件的电子包装材料
公开(公告)号：WO2005048348A1
公开(公告)日：2005-05-26
申请号：PCT/US2004/037530
申请日：2004-11-09
申请人： HENKEL CORPORATION , TODD, Michael, G. , HUNEKE, James, T. , CRANE, Lawrence, N. , FISCHER, Gordon, C.
发明人： TODD, Michael, G. , HUNEKE, James, T. , CRANE, Lawrence, N. , FISCHER, Gordon, C.
IPC分类号： H01L23/48
CPC分类号： H01L25/50 , H01L21/563 , H01L24/73 , H01L24/81 , H01L25/0657 , H01L2224/05001 , H01L2224/05008 , H01L2224/05024 , H01L2224/05026 , H01L2224/05147 , H01L2224/05569 , H01L2224/05571 , H01L2224/05647 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/73257 , H01L2224/73265 , H01L2224/81011 , H01L2224/81801 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06575 , H01L2225/06582 , H01L2924/01004 , H01L2924/01012 , H01L2924/01019 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： Electronic packaging materials for use with Low-k dielectric-containing semiconductor devices are provided.
摘要翻译：提供了用于含低k电介质的半导体器件的电子封装材料。

15. 发明申请

WO02021587A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：WO02021587A1
公开(公告)日：2002-03-14
申请号：PCT/JP2001/005410
申请日：2001-06-25
IPC分类号： C08J7/00 , C08G77/14 , H01L21/311 , H01L21/312 , H01L21/316 , H01L21/60 , H01L21/768 , H01L23/31 , H01L23/522 , H01L23/532 , H01L23/58
CPC分类号： H01L21/02126 , H01L21/02118 , H01L21/022 , H01L21/02282 , H01L21/0234 , H01L21/31138 , H01L21/31144 , H01L21/3122 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L21/76808 , H01L21/76814 , H01L21/76819 , H01L21/76835 , H01L23/3114 , H01L23/5329 , H01L23/53295 , H01L23/585 , H01L24/11 , H01L24/45 , H01L24/48 , H01L2221/1031 , H01L2224/02166 , H01L2224/0401 , H01L2224/05147 , H01L2224/05155 , H01L2224/05569 , H01L2224/05572 , H01L2224/13099 , H01L2224/45144 , H01L2224/48091 , H01L2224/4824 , H01L2224/48247 , H01L2224/48599 , H01L2224/73215 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01093 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/12044 , H01L2924/1306 , H01L2924/13091 , H01L2924/15787 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2924/00 , H01L2224/05552 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A method of manufacturing a semiconductor device with substantially small interlayer capacity capable of being operated at a high speed, comprising the steps of patterning an organic insulation film coated as an interlayer insulation film and an insulation film formed of an organic metal polymer in the semi-thermoset state, etching, by using a plasma gas formed mainly of oxygen, the substrate organic insulation film with the organic metal polymer used as a mask, and providing a final thermosetting treatment to the insulation films.
摘要翻译：一种制造半导体器件的方法，该半导体器件具有能够高速操作的基本上较小的层间电容，包括以下步骤：将半导体层上形成的有机绝缘膜图案化为层间绝缘膜和由有机金属聚合物形成的绝缘膜，通过使用主要由氧形成的等离子体气体，使用有机金属聚合物作为掩模的基板有机绝缘膜，并对绝缘膜进行最终的热固化处理，进行蚀刻。

16. 发明申请

WO0161757B1 MODULE AND METHOD FOR INTERCONNECTING INTEGRATED CIRCUITS THAT FACILITATE HIGH SPEED SIGNAL PROPAGATION WITH REDUCED NOISE 审中-公开
标题翻译：用于将促进高速信号传播的集成电路与降低的噪声相互连接的模块和方法
公开(公告)号：WO0161757B1
公开(公告)日：2001-11-08
申请号：PCT/US0104466
申请日：2001-02-13
申请人： ALPINE MICROSYSTEMS INC
发明人： GOETZ MARTIN , ZASIO JOHN J
IPC分类号： H01L23/498 , H01L23/50 , H01L29/00 , H01L21/44 , H01L21/48 , H01L21/50 , H01L23/06
CPC分类号： H01L23/49827 , H01L23/50 , H01L24/48 , H01L2224/05569 , H01L2224/05573 , H01L2224/05599 , H01L2224/16225 , H01L2224/48091 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01039 , H01L2924/01057 , H01L2924/01322 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/19107 , H01L2924/30107 , H01L2924/3011 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2224/45099
摘要： A module and method for interconnecting integrated circuits. The module includes an insulative body that features conductive traces (23) having different resistivities associated therewith. To that end the insulative body (27), has disposed therein a conductive bond pad (22) and a plurality of spaced-apart conductive traces (23), one of which is in electrical communication with the bond pad (22), with each of the plurality of the conductive traces formed from a material having a resistivity associated therewith. The resistivity of the material from which one of the plurality of conductive traces (23) is formed being greater than the resisitivity of the material from which the remaining conductive traces (23) are formed and defines a decoupling capacitor.
摘要翻译：一种互连集成电路的模块和方法。该模块包括具有与其相关的不同电阻率的导电迹线（23）的绝缘体。为此，绝缘体（27）在其中布置有导电键合焊盘（22）和多个间隔开的导电迹线（23），其中一个导电迹线（23）与接合焊盘（22）电连通，每个导电迹线所述多个导电迹线中的一个导电迹线由具有与之相关的电阻率的材料形成。形成多个导电迹线（23）中的一个的材料的电阻率大于形成剩余导电迹线（23）的材料的电阻率，并且限定去耦电容器。

17. 发明申请

WO2016183978A1 芯片的封装结构及封装方法审中-公开
公开(公告)号：WO2016183978A1
公开(公告)日：2016-11-24
申请号：PCT/CN2015/089700
申请日：2015-09-16
申请人：苏州晶方半导体科技股份有限公司
发明人：王之奇 , 杨莹 , 喻琼 , 王蔚
IPC分类号： H01L23/31
CPC分类号： H01L23/31 , G06F3/044 , G06K9/00006 , H01L24/05 , H01L2224/02371 , H01L2224/04042 , H01L2224/05569 , H01L2224/32225 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45184 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/92247 , H01L2224/94 , H01L2924/10156 , H01L2924/10157 , H01L2924/181 , H01L2924/00012 , H01L2924/00014 , H01L2224/03
摘要：一种芯片的封装结构及封装方法，该封装结构包括：基板（300），与所述基板（300）耦合的感应芯片（301），位于所述基板（300）上的塑封层（303）。所述感应芯片（301）包括第一表面（310）、以及与第一表面（310）相对的第二表面（320），其中所述感应芯片（301）的第二表面（320）面向基板（300），所述感应芯片（301）还包括位于所述第一表面（310）的感应区（311）以及包围所述感应区（311）的外围区（312），所述外围区（312）内具有凹槽（313），所述凹槽（313）的侧壁和底部表面以及外围区（312）表面具有再布线层（314），所述感应芯片（301）的侧面暴露出所述凹槽（313）。所述塑封层（303）包围所述感应芯片（301）并填充于所述凹槽（313）内，且所述塑封层（303）暴露出所述感应区（311）的表面。

18. 发明申请

WO2016004245A1 HIGH QUALITY FACTOR FILTER IMPLEMENTED IN WAFER LEVEL PACKAGING (WLP) INTEGRATED DEVICE 审中-公开
标题翻译：高品质因子滤波器在水平包装（WLP）集成器件中实现
公开(公告)号：WO2016004245A1
公开(公告)日：2016-01-07
申请号：PCT/US2015/038895
申请日：2015-07-01
申请人： QUALCOMM INCORPORATED
发明人： LEE, Jong-Hoon , SONG, Young Kyu , YOON, Jung Ho , JOW, Uei Ming , ZHANG, Xiaonan , LANE, Ryan David
IPC分类号： H01L23/64 , H01L23/522 , H05K1/16 , H01F17/00
CPC分类号： H01L23/645 , H01F17/0013 , H01F2017/0086 , H01L23/3128 , H01L23/5223 , H01L23/5227 , H01L23/525 , H01L2224/0401 , H01L2224/05008 , H01L2224/05147 , H01L2224/05569 , H01L2224/05572 , H01L2224/131 , H01L2224/13147 , H01L2224/16145 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2225/1023 , H01L2225/1058 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/15311 , H01L2924/15331 , H01L2924/19015 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H01L2924/30107 , H05K1/111 , H05K1/165 , H05K2201/10674 , H01L2924/014
摘要： Some implementations provide an integrated device that includes a capacitor and an inductor. The inductor is electrically coupled to the capacitor. The inductor and the capacitor are configured to operate as a filter for an electrical signal in the integrated device. The inductor includes a first metal layer of a printed circuit board (PCB), a set of solder balls coupled to the PCB, and a second metal layer in a die. In some implementations, the capacitor is located in the die. In some implementations, the capacitor is a surface mounted passive device on the PCB. In some implementations, the first metal layer is a trace on the PCB. In some implementations, the inductor includes a third metal layer in the die. In some implementations, the second metal layer is an under bump metallization (UBM) layer of the die, and the third metal is a redistribution layer of the die.
摘要翻译：一些实施方案提供了包括电容器和电感器的集成器件。电感器电耦合到电容器。电感器和电容器被配置为在集成器件中用作电信号的滤波器。电感器包括印刷电路板（PCB）的第一金属层，耦合到PCB的一组焊球，以及管芯中的第二金属层。在一些实施方案中，电容器位于管芯中。在一些实现中，电容器是PCB上的表面安装无源器件。在一些实施方案中，第一金属层是PCB上的痕迹。在一些实施方案中，电感器包括管芯中的第三金属层。在一些实施方案中，第二金属层是管芯的凸块下金属化（UBM）层，第三金属是管芯的再分布层。

19. 发明申请

WO2015147785A1 THROUGH-BODY VIA FORMATION TECHNIQUES 审中-公开
标题翻译：通过形成技术的身体
公开(公告)号：WO2015147785A1
公开(公告)日：2015-10-01
申请号：PCT/US2014/031604
申请日：2014-03-24
申请人： INTEL CORPORATION , LEE, Kevin, J.
发明人： LEE, Kevin, J.
IPC分类号： H01L21/60 , H01L23/48
CPC分类号： H01L23/481 , H01L21/288 , H01L21/76829 , H01L21/76831 , H01L21/76873 , H01L21/76898 , H01L23/53209 , H01L23/53238 , H01L23/5329 , H01L24/02 , H01L24/05 , H01L25/0657 , H01L2224/02372 , H01L2224/05008 , H01L2224/05022 , H01L2224/05569 , H01L2225/06544
摘要： Techniques are disclosed for forming a through-body- via (TBV) in a semiconductor die. In accordance with some embodiments, a TBV provided using the disclosed techniques includes a polymer-based barrier layer and an electrically conductive seed layer formed by applying an electrically conductive ink directly to the barrier layer and then curing it in situ. In some embodiments, after curing, the resultant seed layer may be a thin, substantially conformal, electrically conductive metal film over which the TBV interconnect metal can be deposited. In some example cases, a polyimide, parylene, benzocyclobutene (BCB), and/or polypropylene carbonate (PPC) barrier layer and an ink containing copper (Cu) and/or silver (Ag), of nanoparticle-based or metal complex -based formulation, may be used in forming the TBV. In some instances, the disclosed techniques may be used to address poor step coverage, low run rate, and/or high cost issues associated with existing physical vapor deposition (PVD) -based far- back-end-of-line (FBEOL) processes.
摘要翻译：公开了用于在半导体管芯中形成贯穿体通孔（TBV）的技术。根据一些实施例，使用所公开的技术提供的TBV包括基于聚合物的阻挡层和通过将导电油墨直接施加到阻挡层然后在原位固化而形成的导电种子层。在一些实施方案中，固化后，所得种子层可以是薄的，基本上保形的导电金属膜，TBV互连金属可以沉积在其上。在一些示例性情况下，基于纳米颗粒或基于金属络合物的聚酰亚胺，聚对二甲苯，苯并环丁烯（BCB）和/或聚丙烯碳酸酯（PPC）阻挡层和含有铜（Cu）和/或银（Ag）配方，可用于形成TBV。在一些情况下，所公开的技术可以用于解决与现有的基于物理气相沉积（PVD）的远程后端（FBEOL）过程相关联的差的步骤覆盖率，低运行速率和/或高成本问题。

20. 发明申请

WO2014088966A3 BONDING STRUCTURE FOR A MICROELECTRONIC ASSEMBLY COMPRISING A HIGH MELTING POINT ALLOY FORMED BY BONDING TWO BOND COMPONENTS EACH COMPRISING A NON-LOW MELTING POINT MATERIAL LAYER COVERING A LOW MELTING POINT MATERIAL LAYER AND CORRESPONDING MANUFACTURING METHOD 审中-公开
标题翻译：包含通过粘结两个粘结组分形成的高熔点组成的微电子组件的结合结构，每个组合包含非低熔点点材料层覆盖低熔点点材料层和相应的制造方法
公开(公告)号：WO2014088966A3
公开(公告)日：2015-01-15
申请号：PCT/US2013072675
申请日：2013-12-02
申请人： INVENSAS CORP
发明人： UZOH CYPRIAN EMEKA
IPC分类号： H01L23/485 , H01L21/50 , H01L21/60 , H01L23/10 , H01L23/498 , H05K3/34
CPC分类号： H05K13/046 , H01L21/4853 , H01L21/50 , H01L21/76898 , H01L23/10 , H01L23/481 , H01L23/49811 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/98 , H01L2224/02372 , H01L2224/03912 , H01L2224/0401 , H01L2224/05023 , H01L2224/05025 , H01L2224/05026 , H01L2224/05027 , H01L2224/05138 , H01L2224/05155 , H01L2224/05157 , H01L2224/05164 , H01L2224/05166 , H01L2224/05171 , H01L2224/0518 , H01L2224/05181 , H01L2224/05184 , H01L2224/05187 , H01L2224/05568 , H01L2224/05569 , H01L2224/05571 , H01L2224/05647 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/13009 , H01L2224/13017 , H01L2224/13018 , H01L2224/13022 , H01L2224/13023 , H01L2224/13025 , H01L2224/13076 , H01L2224/13078 , H01L2224/1308 , H01L2224/13082 , H01L2224/13105 , H01L2224/13109 , H01L2224/13138 , H01L2224/13147 , H01L2224/13155 , H01L2224/13184 , H01L2224/1319 , H01L2224/14131 , H01L2224/16146 , H01L2224/16235 , H01L2224/16501 , H01L2224/16505 , H01L2224/2745 , H01L2224/27452 , H01L2224/27462 , H01L2224/27464 , H01L2224/29011 , H01L2224/29023 , H01L2224/2908 , H01L2224/29082 , H01L2224/29105 , H01L2224/29109 , H01L2224/29138 , H01L2224/29147 , H01L2224/32225 , H01L2224/32245 , H01L2224/32501 , H01L2224/32505 , H01L2224/73103 , H01L2224/73203 , H01L2224/81075 , H01L2224/8112 , H01L2224/81141 , H01L2224/81193 , H01L2224/81825 , H01L2224/83075 , H01L2224/8312 , H01L2224/83193 , H01L2224/83825 , H01L2924/00014 , H01L2924/381 , H01L2924/04953 , H01L2924/01071 , H01L2924/01042 , H01L2924/01015 , H01L2924/04941 , H01L2924/01074 , H01L2924/01047 , H01L2924/01031 , H01L2924/01034 , H01L2924/00012 , H01L2924/07025 , H01L2224/05552
摘要： A microelectronic assembly (10, 110, 210, 310, 410) includes a first substrate (12, 112, 212, 312, 412, 512, 612, 712, 812, 912) having a first conductive element (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022) and a second substrate (14, 114, 214, 314, 414) having a second conductive element (26, 126, 226, 326, 426). The assembly further includes an electrically conductive alloy mass (16, 116) joined to the first and second conductive elements (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022), including a first, a second and a third material. First and second materials of the alloy mass (16, 116) each have a melting point lower than a melting point of the alloy. A concentration of the first material varies in concentration from a relatively higher amount at a location disposed toward the first conductive element (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022) to a relatively lower amount toward the second conductive element (26, 126, 226, 326, 426), and a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second conductive element (26, 126, 226, 326, 426) to a relatively lower amount toward the first conductive element (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022). The microelectronic assembly (10, 110, 210, 310, 410) is formed by aligning the first substrate (12, 112, 212, 312, 412, 512, 612, 712, 812, 912), having a first bond component (30, 230, 330, 430), with the second substrate (14, 114, 214, 314, 414), having a second bond component (40, 240, 340, 440), such that the first (30, 230, 330, 430, 1030) and second (40, 240, 340, 440) bond components are in contact with each other, the first bond component (30, 230, 330, 430, 1030) including a first material layer (36, 536, 636, 736, 836, 936) adjacent the first conductive element (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022) and a first protective layer (38, 538, 638, 738, 838, 938) overlying the first material layer (36, 536, 636, 736, 836, 936), the second bond component (40, 240, 340, 440) including a second material layer (46) adjacent the second conductive element (26) and a second protective layer (48) overlying the second material layer (46), and heating the first (30, 230, 330, 430, 1030) and second (40, 240, 340, 440) bond components such that at least portions of the first (36, 536, 636, 736, 836, 936) and second (46) material layers diffuse together to form the alloy mass (16, 116) joining the first (12, 112, 212, 312, 412, 512, 612, 712, 812, 912) and second (14, 114, 214, 314, 414) substrates with one another. There may be formed a plurality of first conductive elements (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022) on the first substrate (12, 112, 212, 312, 412, 512, 612, 712, 812, 912) and a plurality of second conductive elements (26, 126, 226, 326, 426) on the second substrate (14, 114, 214, 314, 414), joined by a plurality of conductive alloy masses (16, 116). The conductive alloy mass (116) may also surround and hermetically seal an internal volume.
摘要翻译：微电子组件（10,110,210,310,410）包括具有第一导电元件（26,126,226）的第一衬底（12,112,212,312,412,512,612,712,812,912）具有第二导电元件（26,126,226,326,426）的第二基板（14,114,214,314,414），以及具有第二导电元件（26,126,226,326,426）的第二基板（14,114,214,314,414）。组件还包括接合到第一和第二导电元件（26,126,226,326,426,526,626,726,826,926,1022）的导电合金块（16,116），包括第一，第二和第三材料。合金质量（16,116）的第一和第二材料的熔点低于合金的熔点。第一材料的浓度在朝向第一导电元件（26,126,226,326,426,526,626,726,826,926,1022）设置的位置处的相对较高的量的浓度变化到相对较低的量朝向第二导电元件（26,126,226,326,426）的量，并且第二材料的浓度在朝向第二导电元件（26,126,226,326,426）设置的位置处的相对较高的量的浓度变化，426）朝向第一导电元件（26,126,226,326,426,526,626,726,826,926,1012）相对较低的量。微电子组件（10,110,210,310,410）通过使具有第一粘合组分（30,110,210,310,410）的第一粘合组分（30,110,210,310,410）具有第二接合部件（40,42,340,440）的第二基板（14,114,214,314,414），使得所述第一基板（30,230,340,440）所述第一接合部件（30,230,330,430,1030）包括第一材料层（36,536,630）和第二接合部件（40,42,340,440），所述第一接合部件邻近第一导电元件（26,126,226,326,426,526,626,726,826,926,1022）的第一保护层（38,538,638,738,838），第三保护层，覆盖在第一材料层（36,536,636,736,836,936）上的第二结合部件（40,240,340,440）包括邻近第二导电元件（26）的第二材料层（46））和覆盖在第二材料层（46）上的第二保护层（48），并且加热第一（30,230,33 0,430,1030）和第二（40,42,340,440）粘合部件，使得第一（36,536,636,736,836,936）和第二（46）材料层的至少一部分一起扩散到形成将第一（12,112,212,312,412,912）和第二（14,114,214,314,414）基板彼此接合的合金块（16,116）。可以在第一衬底（12,112,212,312,412,512,512）上形成多个第一导电元件（26,126,226,326,426,526,626,726,826,926,1022） 612,1112,812,912）以及由第二基片（14,114,214,314,414）上的多个第二导电元件（26,126,226,326,426）组成的多个导电合金块（16,116）。导电合金质量块（116）也可以围绕并气密地密封内部体积。

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