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    • 2. 发明申请
    • INSULATED TOP SIDE BUMP CONNECTION FOR A POWER DEVICE, FOR EXAMPLE FOR GATE, SOURCE AND DRAIN CONTACTS OF A POWER FIELD EFFECT TRANSISTOR
    • 用于功率器件的绝缘顶部保护连接,用于电源场效应晶体管的栅极,源极和漏极触点的示例
    • WO2014149579A1
    • 2014-09-25
    • PCT/US2014/019728
    • 2014-03-01
    • MICROCHIP TECHNOLOGY INCORPORATED
    • DIX, GregoryMELCHER, Roger
    • H01L23/485H01L23/482H01L23/495H01L23/31H01L25/065H01L21/60
    • H01L23/4952H01L23/3171H01L23/4824H01L23/4951H01L23/49562H01L23/49575H01L24/05H01L24/11H01L24/13H01L24/14H01L24/16H01L24/17H01L24/48H01L24/49H01L24/81H01L2224/0401H01L2224/05554H01L2224/05567H01L2224/05647H01L2224/1148H01L2224/13014H01L2224/13021H01L2224/13082H01L2224/131H01L2224/13147H01L2224/1329H01L2224/133H01L2224/1403H01L2224/14133H01L2224/14163H01L2224/16112H01L2224/16245H01L2224/17107H01L2224/48247H01L2224/49171H01L2224/81191H01L2224/81801H01L2224/8185H01L2924/00014H01L2924/1305H01L2924/1306H01L2924/014H01L2924/0665H01L2924/00H01L2224/05552H01L2224/45099H01L2224/05599
    • A semiconductor power chip comprises a semiconductor die (102, 140, 172, 173, 210, 220, 230, 240, 240') having a power device, for example a power field effect transistor, fabricated on a substrate (210) thereof, wherein the power device has at least one first contact element (e.g. a gate contact element) (110), a plurality of second contact elements (source contact elements) (120) and a plurality of third contact elements (drain contact elements) (130) arranged on top of the semiconductor die (102, 140, 172, 173, 210, 220, 230, 240, 240'); and an insulation layer (150) disposed on top of the semiconductor die (102, 140, 172, 173, 210, 220, 230, 240, 240') and patterned to provide openings (104, 106, 108, 154, 154', 156, 156', 158, 158') to access the plurality of second (120) and third (130) contact elements and the at least one first contact element (110). The gate (104, 154, 154') and drain (108, 158, 158') openings in the insulation layer (150) are arranged on one side of the top surface of the die (102, 140, 172, 173, 210, 220, 230, 240, 240') and the source (106, 156, 156') openings are arranged on the opposite side of the top surface of the die (102, 140, 172, 173, 210, 220, 230, 240, 240'). The openings in the insulation layer (150) are circular (104, 106, 108) or preferably elliptic (154, 154', 156, 156', 158, 158'). Solder or conductive epoxy bumps (160) are placed in the openings (104, 106, 108, 154, 154', 156, 156', 158, 158') for bonding the first (110), second (120) and third (130) contacts to lead frame fingers (204, 204', 206, 206', 208). The lead frame is optionally substantially larger than the die (220, 230) of the semiconductor power chip. The lead frame may connect together a source of a first semiconductor chip with a drain of a second semiconductor chip or sources of a first and a second semiconductor chip. A further chip (620) may be wire-bonded to the lead frame.
    • 半导体功率芯片包括具有制造在其基板(210)上的功率器件(例如功率场效应晶体管)的半导体管芯(102,140,​​172,173,210,220,230,240,240'), 其中所述功率器件具有至少一个第一接触元件(例如,栅极接触元件)(110),多个第二接触元件(源极接触元件)(120)和多个第三接触元件(漏极接触元件)(130) ),其布置在所述半导体管芯(102,140,​​172,173,210,220,230,240,240')的顶部上; 以及设置在所述半导体管芯(102,140,​​172,173,210,220,230,240,240')的顶部上并被图案化以提供开口(104,106,108,154,154')的绝缘层(150) ,156,156',158,158')以访问所述多个第二(120)和第三(130)接触元件和所述至少一个第一接触元件(110)。 绝缘层(150)中的栅极(104,154,154')和漏极(108,158,158')开口布置在管芯(102,140,​​172,173,210)的顶表面的一侧 ,220,230,240,240'),并且所述源(106,156,156')开口布置在所述管芯(102,140,​​172,23) 240,240')。 绝缘层(150)中的开口是圆形(104,106,108)或优选椭圆形(154,154',156,156',158,158')。 焊接或导电环氧树脂凸块(160)放置在开口(104,106,108,154,154',156,156',158,158')中,用于将第一(110),第二(120)和第三( 130)接触以引导框架指状物(204,204',206,206',208)。 引线框架可选地基本上大于半导体功率芯片的管芯(220,230)。 引线框架可将第一半导体芯片的源极与第二半导体芯片的漏极或第一和第二半导体芯片的源极连接在一起。 另外的芯片(620)可以引线接合到引线框架。