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1. 发明申请

WO0161757B1 MODULE AND METHOD FOR INTERCONNECTING INTEGRATED CIRCUITS THAT FACILITATE HIGH SPEED SIGNAL PROPAGATION WITH REDUCED NOISE 审中-公开
标题翻译：用于将促进高速信号传播的集成电路与降低的噪声相互连接的模块和方法
公开(公告)号：WO0161757B1
公开(公告)日：2001-11-08
申请号：PCT/US0104466
申请日：2001-02-13
申请人： ALPINE MICROSYSTEMS INC
发明人： GOETZ MARTIN , ZASIO JOHN J
IPC分类号： H01L23/498 , H01L23/50 , H01L29/00 , H01L21/44 , H01L21/48 , H01L21/50 , H01L23/06
CPC分类号： H01L23/49827 , H01L23/50 , H01L24/48 , H01L2224/05569 , H01L2224/05573 , H01L2224/05599 , H01L2224/16225 , H01L2224/48091 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01039 , H01L2924/01057 , H01L2924/01322 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/19107 , H01L2924/30107 , H01L2924/3011 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2224/45099
摘要： A module and method for interconnecting integrated circuits. The module includes an insulative body that features conductive traces (23) having different resistivities associated therewith. To that end the insulative body (27), has disposed therein a conductive bond pad (22) and a plurality of spaced-apart conductive traces (23), one of which is in electrical communication with the bond pad (22), with each of the plurality of the conductive traces formed from a material having a resistivity associated therewith. The resistivity of the material from which one of the plurality of conductive traces (23) is formed being greater than the resisitivity of the material from which the remaining conductive traces (23) are formed and defines a decoupling capacitor.
摘要翻译：一种互连集成电路的模块和方法。该模块包括具有与其相关的不同电阻率的导电迹线（23）的绝缘体。为此，绝缘体（27）在其中布置有导电键合焊盘（22）和多个间隔开的导电迹线（23），其中一个导电迹线（23）与接合焊盘（22）电连通，每个导电迹线所述多个导电迹线中的一个导电迹线由具有与之相关的电阻率的材料形成。形成多个导电迹线（23）中的一个的材料的电阻率大于形成剩余导电迹线（23）的材料的电阻率，并且限定去耦电容器。

2. 发明申请

WO0203422A3 INTEGRATED CIRCUITS PACKAGING SYSTEM AND METHOD 审中-公开
标题翻译：集成电路包装系统及方法
公开(公告)号：WO0203422A3
公开(公告)日：2007-10-18
申请号：PCT/US0120727
申请日：2001-06-29
申请人： ALPINE MICROSYSTEMS INC
发明人： BROWN SAMMY K , AVERY GEORGE E , WIGGIN ANDREW K , BEAL SAMUEL W
IPC分类号： H05K7/02 , H01L21/66 , H01L23/498 , H01L23/538 , H01L25/065 , H05K1/18
CPC分类号： H01L22/20 , H01L23/49827 , H01L23/5386 , H01L25/0655 , H01L2224/16225 , H01L2924/014 , H01L2924/3011 , H05K1/182
摘要： A plurality of integrated circuits are efficiently interconnected to improve the electrical performance of the overall system (20). This is accomplished by providing high speed, high density, system level interconnect, including interchip routing lines, on the integrated circuit devices (10), thereby reducing the routing complexity of the substrate or board (14). The devices are mounted directly on the board (14). An integrated cncuit deb vice comprises an integrated circuit region including integrated circuit elements. An interconnect layer (25) includes an insulative material, a plurality of conductive traces, and a plurality of conductive bond pads (22) arranged in first and second subsets. A first subgroup of the conductive traces (20) are connected to the integrated circuit elements in the integrated circuit region and are connected to the first subset of conductive bond pads (22). A second subgroup of the conductive traces (20) are electrically insulated from the integrated circuit elements and are electrically insulated from the first subgroup of the conductive traces to form a pass through (25). The second subgroup of the conductive traces (20) are connected to the second subset of conductive bond pads (22).
摘要翻译：多个集成电路被有效地互连以改善整个系统（20）的电气性能。这通过在集成电路器件（10）上提供高速，高密度的系统级互连（包括芯片间路由线路）来实现，从而降低了衬底或板（14）的布线复杂度。设备直接安装在板（14）上。集成电路包括集成电路元件的集成电路区域。互连层（25）包括绝缘材料，多个导电迹线以及布置在第一和第二子集中的多个导电接合焊盘（22）。导电迹线（20）的第一子组连接到集成电路区域中的集成电路元件，并连接到导电接合焊盘（22）的第一子集。导电迹线（20）的第二子组与集成电路元件电绝缘并且与导电迹线的第一子组电绝缘以形成通过（25）。导电迹线（20）的第二子组连接到导电接合焊盘（22）的第二子集。

3. 发明申请

WO2003077285A2 THIN-FILM CAPACITOR HAVING MULTI-LAYER DIELECTRIC FILM INCLUDING SILICON DIOXIDE AND TANTALUM PENTOXIDE 审中-公开
标题翻译：具有多层电介质薄膜的薄膜电容器，包括二氧化硅和三氧化二钽
公开(公告)号：WO2003077285A2
公开(公告)日：2003-09-18
申请号：PCT/US2003/006990
申请日：2003-03-07
申请人： ALPINE MICROSYSTEMS, INC.
发明人： LaFLEUR, Mike
IPC分类号： H01L
CPC分类号： H01L28/40 , H01L21/31612 , H01L21/31637 , H01L28/56
摘要： A capacitor and a method of forming the same, one embodiment of which includes depositing a multi-layer dielectric film between first and second spaced-apart electrodes. The multi-layer dielectric film includes first and second laye4rs that have differing roughness. The layer of the dielectric film having the least amount of roughness is disposed adjacent to the first electrode. After depositing the second layer of the dielectric film adjacent to the first layer, the second layer is annealed. An exemplary embodiment of the thin film capacitor forms the dielectric material from silicon dioxide (SiO 2 ) and tantalum pentoxide (Ta 2 O 5 ).
摘要翻译：一种电容器及其形成方法，其一个实施例包括在第一和第二间隔开的电极之间沉积多层电介质膜。多层电介质膜包括具有不同粗糙度的第一和第二层。具有最少粗糙度的电介质膜的层被布置成与第一电极相邻。在沉积与第一层相邻的电介质膜的第二层之后，将第二层退火。薄膜电容器的示例性实施例由二氧化硅（SiO 2）和五氧化二钽（Ta 2 O 5）形成电介质材料。

4. 发明申请

WO2003077285A3 THIN-FILM CAPACITOR HAVING MULTI-LAYER DIELECTRIC FILM INCLUDING SILICON DIOXIDE AND TANTALUM PENTOXIDE 审中-公开
公开(公告)号：WO2003077285A3
公开(公告)日：2003-09-18
申请号：PCT/US2003/006990
申请日：2003-03-07
申请人： ALPINE MICROSYSTEMS, INC.
发明人： LaFLEUR, Mike
IPC分类号： H01L21/8242
摘要： A capacitor (10) and a method of forming the same, one embodiment of which includes depositing a multi-layer dielectric film (18a, 18b,) between first and second spaced-apart electrodes (14, 16). The multi-layer dielectric film includes first and second layers that have differing roughness. The layer of the dielectric film having the least amount of roughness is disposed adjacent to the first electrode (14). After depositing the second layer (18a) of the dielectric film adjacent to the first layer (18b), the second layer is annealed. An exemplary embodiment of the thin film capacitor forms the dielectric material from silicon dioxide (SiO 2 ) and tantalum pentoxide (Ta 2 O 5 ).

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