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1. 发明公开

EP2908346A1 Pair of transistors with reduced parasitic thyristor 审中-公开
标题翻译：晶体管晶闸管
公开(公告)号：EP2908346A1
公开(公告)日：2015-08-19
申请号：EP15153075.5
申请日：2015-01-29
申请人： NXP B.V.
发明人： Ritter, Hans-Martin
IPC分类号： H01L29/735 , H01L29/78 , H01L27/082 , H01L27/092 , H01L29/06 , H01L29/10
CPC分类号： H01L29/735 , H01L21/823892 , H01L27/0823 , H01L27/0921 , H01L29/0646 , H01L29/1008 , H01L29/1079
摘要： Parasitic thyristor action may be mitigated in semiconductor devices by placement of minority carrier traps (25, 27), illustratively in the base(s) (21) of bipolar transistors or the well (403, 405) of a CMOS transistor pair (Fig. 6). The minority carrier traps include adjacent n and p regions (25, 27 / 419, 421) which may be connected by a conductor (31, 423, 427).
摘要翻译：寄生晶闸管的作用可以通过放置少量载流子阱（25,27），例如在双极晶体管的基极（21）或CMOS晶体管对的阱（403,405）中来缓解。 6）。少数载流子阱包括可由导体（31,423,427）连接的相邻的n和p区（25,27 / 419,421）。

2. 发明公开

EP0759638A3 High withstand voltage semiconductor device and manufacturing method thereof 失效
标题翻译：具有高耐受电压的半导体器件，及其制造方法
公开(公告)号：EP0759638A3
公开(公告)日：1999-05-06
申请号：EP96104778.4
申请日：1996-03-26
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Akiyama, Hajime
IPC分类号： H01L29/06 , H01L29/08
CPC分类号： H01L29/7824 , H01L29/0615 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/1008 , H01L29/102 , H01L29/1083 , H01L29/402 , H01L29/41725 , H01L29/66674 , H01L29/7302 , H01L29/7393 , H01L29/7394 , H01L29/7436 , H01L29/7455 , H01L29/7801 , H01L29/7835
摘要： An n - layer (2) is formed on a main surface of a p-type semiconductor substrate (1). A p - diffusion region (5) is formed at a surface of n - layer (2). A p diffusion region (6) is formed contiguous to one end of p - diffusion region (5). A plurality of p diffusion regions (20) containing p-type impurity the concentration of which is higher than that of p - diffusion region (5) are formed in p - diffusion region (5). A p diffusion region (3) is formed such that it is spaced apart from p - diffusion region (5). A gate electrode (9) is formed on a surface of n - layer (2) positioned between p diffusion region (3) and p - diffusion region (5) with an oxide film (10) interposed. A drain electrode (12) is formed in contact with a surface of p diffusion region (6). Furthermore, an n diffusion region (4) is formed adjacent to p diffusion region (3), and a source electrode (11) is formed in contact with both a surface of n diffusion region (4) and a surface p diffusion region (3).

3. 发明公开

EP0759638A2 High withstand voltage semiconductor device and manufacturing method thereof 失效
标题翻译： Halbleiterbauelement mit hoher Spannungsfestigkeit und dessen Herstellungsverfahren
公开(公告)号：EP0759638A2
公开(公告)日：1997-02-26
申请号：EP96104778.4
申请日：1996-03-26
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Akiyama, Hajime
IPC分类号： H01L29/06 , H01L29/08
CPC分类号： H01L29/7824 , H01L29/0615 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/1008 , H01L29/102 , H01L29/1083 , H01L29/402 , H01L29/41725 , H01L29/66674 , H01L29/7302 , H01L29/7393 , H01L29/7394 , H01L29/7436 , H01L29/7455 , H01L29/7801 , H01L29/7835
摘要： An n - layer (2) is formed on a main surface of a p-type semiconductor substrate (1). A p - diffusion region (5) is formed at a surface of n - layer (2). A p diffusion region (6) is formed contiguous to one end of p - diffusion region (5). A plurality of p diffusion regions (20) containing p-type impurity the concentration of which is higher than that of p - diffusion region (5) are formed in p - diffusion region (5). A p diffusion region (3) is formed such that it is spaced apart from p - diffusion region (5). A gate electrode (9) is formed on a surface of n - layer (2) positioned between p diffusion region (3) and p - diffusion region (5) with an oxide film (10) interposed. A drain electrode (12) is formed in contact with a surface of p diffusion region (6). Furthermore, an n diffusion region (4) is formed adjacent to p diffusion region (3), and a source electrode (11) is formed in contact with both a surface of n diffusion region (4) and a surface p diffusion region (3).
摘要翻译：在p型半导体衬底（1）的主表面上形成n +层（2）。在n层（2）的表面形成p +扩散区（5）。 p扩散区（6）形成为与p扩散区（5）的一端相邻。在p扩散区域（5）中形成多个p型扩散区（20），其中p型杂质的浓度高于p - 扩散区（5）的p型杂质。形成p扩散区域（3），使得其与p - 扩散区域（5）间隔开。在位于p扩散区域（3）和p +扩散区域（5）之间的n +层（2）的表面上形成有氧化膜（10）的栅电极（9）。漏电极（12）形成为与p扩散区域（6）的表面接触。此外，与p扩散区域（3）相邻形成n个扩散区域（4），并且形成与n扩散区域（4）的表面和表面p扩散区域（3）两者接触的源电极（11））。

4. 发明公开

EP0642171A2 Lateral bipolar transistor 失效
标题翻译：横向双极晶体管
公开(公告)号：EP0642171A2
公开(公告)日：1995-03-08
申请号：EP94203107.1
申请日：1991-02-21
申请人： CANON KABUSHIKI KAISHA
发明人： Morishita, Masakazu, c/o Canon Kabushiki Kaisha
IPC分类号： H01L29/73 , H01L29/10
CPC分类号： H01L29/1008 , H01L29/0895 , H01L29/165 , H01L29/735 , H01L29/737
摘要： A lateral bipolar transistor (fig.5) is provided with an emitter (5) and a collector (5') of a first conductivity type and a base (3,4) of a second conductivity type, arranged in a lateral structure. The transistor includes a region (4) constituting part of the base (3,4), in contact with a remainder part (3) of the base and which is positioned between the emitter (5) and collector (5'), and has a narrower energy band gap than the remainder part (3) of the base (3,4).
摘要翻译：横向双极型晶体管（图5）具有第一导电类型的发射极（5）和集电极（5'）以及第二导电类型的基极（3,4），其布置成横向结构。该晶体管包括构成基座（3,4）的一部分的区域（4），该区域与基座的其余部分（3）接触并且位于发射极（5）和集电极（5'）之间，并且具有比基部（3,4）的其余部分（3）更窄的能带隙。

5. 发明公开

EP0489262A1 Lateral bipolar transistor with edge-strapped base contact and method of fabricating same 失效
标题翻译：横向双极晶体管电容器
公开(公告)号：EP0489262A1
公开(公告)日：1992-06-10
申请号：EP91118800.1
申请日：1991-11-05
申请人： International Business Machines Corporation
发明人： Shadihi, Ghavam G. , Tang, Denny D. , Taur, Yuan
IPC分类号： H01L29/73 , H01L21/84 , H01L21/331
CPC分类号： H01L29/6625 , H01L21/84 , H01L29/1008 , H01L29/7317 , H01L29/735
摘要： A bipolar transistor is formed on a silicon-on-insulator structure comprises a substrate (102) having a layer of oxide (104) formed thereon and a layer of silicon (106) formed on said oxide layer, said layer of silicon having a substantially planar surface (108). A collector region (110) of a first conductivity type is extending from said surface (108) of said silicon layer (106), an emitter region (112) of said first conductivity type is extending from said surface of said silicon layer, and an intrinsic base region (114) of a second conductivity type is extending from said surface of said silicon layer, said intrinsic base region (114) being contiguous to said emitter region (112) and intermediate said emitter and collector regions (112, 110). A layer of insulator (116) is formed on said silicon layer (106). A polysilicon extrinsic base region (118) of said second conductivity type is formed on said insulator layer (116), and a silicon edge contact region (120) of said second conductivity type is connected to a sidewall of said extrinsic base region (118) and said surface of said intrinsic base region (114).
摘要翻译：在绝缘体上硅结构上形成双极晶体管，其包括其上形成有氧化物层（104）的衬底（102）和形成在所述氧化物层上的硅层（106），所述硅层具有基本上平面（108）。第一导电类型的集电极区域（110）从所述硅层（106）的所述表面（108）延伸，所述第一导电类型的发射极区域（112）从所述硅层的所述表面延伸，并且第二导电类型的本征基极区域（114）从所述硅层的所述表面延伸，所述本征基极区域（114）与所述发射极区域（112）邻接并且位于所述发射极和集电极区域（112,110）的中间。在所述硅层（106）上形成绝缘体层（116）。所述第二导电类型的多晶硅非本征基极区（118）形成在所述绝缘体层（116）上，并且所述第二导电类型的硅边缘接触区域（120）连接到所述外部基极区域（118）的侧壁，和所述本征基区（114）的所述表面。

6. 发明授权

EP0152116B1 Lateral bipolar transistor and method of producing the same 失效
标题翻译：侧向双极晶体管及其制造方法
公开(公告)号：EP0152116B1
公开(公告)日：1991-01-23
申请号：EP85101688.1
申请日：1985-02-15
申请人： HITACHI, LTD.
发明人： Nakazato, Kazuo , Nakamura, Tohru , Kato, Masataka , Okabe, Takahiro
IPC分类号： H01L29/73 , H01L29/10 , H01L21/225 , H01L21/316
CPC分类号： H01L21/28525 , H01L21/2257 , H01L29/1008 , H01L29/735

7. 发明公开

EP0247386A2 Lateraltransistor 有权转让
标题翻译： Lateraltransistor。
公开(公告)号：EP0247386A2
公开(公告)日：1987-12-02
申请号：EP87106346.7
申请日：1987-05-02
申请人： TELEFUNKEN electronic GmbH
发明人： Arndt, Jürgen, Dr.
IPC分类号： H01L29/72 , H01L27/06 , H01L21/82 , H01L29/10
CPC分类号： H01L29/402 , H01L21/2652 , H01L21/74 , H01L21/8249 , H01L29/1008 , H01L29/735 , Y10S148/009 , Y10S148/01
摘要： Die Erfindung betrifft einen PNP-Lateraltransistor aus zwei in die Oberfläche eines Halbleiterbereichs (12) vom n-Leitungstyp eingelassenen, Emitter (19d) und Kollektor (19c) bildenden Zonen vom p-Leitungstyp, wobei der zwischen diesen beiden Zonen liegende Teil des Halbleiterbereichs vom n-Leitungstyp die aktive Basiszone (26) bildet. Die Erfindung besteht darin, daß die aktive Basiszone (26) unterhalb der Halbleiteroberfläche und angrenzend an die Emitter- und die Kollektorzone eine vergrabene Halbleiterzone (25) enthält, die gegenüber dem übrigen umgebenden Bereich der aktiven Basiszone (26) zusätzliche kontradotierende Störstellen enthält, so daß ein Stromführungskanal für die Minoritätsladungsträger in der Basiszone entsteht. Hierdurch wird der Einfluß störender Oberflächenrekombinationen und des Substrattransistors erheblich vermindert und eine sehr hohe Gleichstromverstärkung des Lateraltransistors erzielt.
摘要翻译：本发明涉及在从n型导电型，发射器（19D）和收集器（19C）凹陷的半导体区域（12）的表面的两个横向PNP晶体管形成的p型导电型，其特征在于，所述半导体区域的这两个区域部分之间的位于的区 n导电型构成的活性基区（26）。本发明在于，半导体表面的下方的有源基区（26）和邻近所述发射极和集电极区域的掩埋半导体区（25），其（26）包含相对于围绕该有源基区的其余区域附加kontradotierende杂质，对于在基极区域的少数载流子的流动导槽形成。以这种方式，干扰在基板的表面重组的影响，并且该晶体管被显着减小，并且实现了横向的非常高的直流增益。

8. 发明公开

EP0178801A3 SEMICONDUCTOR DEVICE WITH IMAGINARY BASE REGION 失效
标题翻译：具有图像基区的半导体器件
公开(公告)号：EP0178801A3
公开(公告)日：1986-12-30
申请号：EP85306681
申请日：1985-09-19
申请人： SONY CORPORATION
发明人： KATO, YOJI C/O PATENTS DIVISION , WATANABE, SEIICHI C/O PATENTS DIVISION , WADA, MASARU C/O PATENTS DIVISION
IPC分类号： H01L29/73 , H01L21/331 , H01L29/10 , H01L29/732 , H01L29/735 , H01L29/72
CPC分类号： H01L29/735 , H01L29/1008
摘要： A semiconductor device includes a semiconductor subs trate (11) having a semi-insulating property, a first region (12) of one conductivity-type which will become an emitter region, a second region (13) of the one conductivity-type which will become a collector region, the first and second regions (12, 13) being formed on the substrate (11) with a predetermined spacing therebetween, and a third region (14) of another conductity-type formed on the substrate (11) between the first and second regions (12, 13). A forward biasing voltage is applied between the third and first regions (14, 12) thereby to form an imaginary base region (19) in the substrate (11) beneath the third region (141 by majority carriers implanted or injected from the third region (14), whereby the semiconductor device carries out a bipolar transistor operation, and at least one of the first and third regions (12, 14) consists of a plurality of regions.

9. 发明公开

EP0137992A2 Lateral bipolar transistor formed in a silicon on insulator (SOI) substrate 失效
标题翻译：双极，双极晶体管，在非晶硅隔离器（SOI）-Substrat中。
公开(公告)号：EP0137992A2
公开(公告)日：1985-04-24
申请号：EP84110211.4
申请日：1984-08-28
申请人： FUJITSU LIMITED
发明人： Nakano, Motoo
IPC分类号： H01L29/72
CPC分类号： H01L29/1008 , H01L29/7317
摘要： A lateral bipolar transistor formed on a silicon on insulator (SOI) substrate, having a base electrode of heat resistive polycrystalline silicon of first conductivity type, formed on a base region of first conductivity type, all the bottom plane of the transistor region is in contact with the insulating layer of the SOI substrate. The base electrode is extended laterally over a part of a collector region to provide a relatively large base electrode width, which allows a small width of the base region, enhancing the current amplification factor of the transistor. The base region has a vertical doping profile which has a minimum value between the base electrode and the insulator layer of the substrate, reducing the recombination of carriers in the base region. Fabricating methods utilizing self-alignment-diffusion process are provided.
摘要翻译：形成在绝缘体上硅（SOI）衬底上的横向双极晶体管，具有基极。的第一导电类型的耐热多晶硅，形成在第一导电类型的基极区上，晶体管区域的所有底面均与SOI衬底的绝缘层接触。基极在集电极区域的一部分上横向延伸以提供相对较大的基极宽度，这允许基极区域的较小宽度增强晶体管的电流放大系数。基极区域具有垂直掺杂分布，其在基极和衬底的绝缘体层之间具有最小值，从而减少了基极区域中载流子的复合。提供了利用自对准扩散过程的制造方法。

10. 发明公开

EP0100677A2 Semiconductor devices including lateral-type transistors 失效
标题翻译： Halbleiteranordnungen mit Laltaltransistoren。
公开(公告)号：EP0100677A2
公开(公告)日：1984-02-15
申请号：EP83304446.4
申请日：1983-08-01
申请人： FUJITSU LIMITED
发明人： Isogai, Hideaki , Ono, Chikai
IPC分类号： H01L29/06
CPC分类号： H01L29/402 , H01L21/76 , H01L21/761 , H01L27/1025 , H01L29/1008 , H01L29/735
摘要： A semiconductor device comprises at least one lateral-type PNP transistor (31) having a collector region (31c), an emitter region (31e), a base region (31b), and partially extended emitter wiring (37) covering the base region, to protect against channel leakage. The collector and emitter regions directly contact an isolation region (41), but the base region contacts the isolation region via a projection (42), preferably formed integrally with the isolation region. The partially extended emitter wiring may also extend over the projection, which possibility can serve to accommodate manufacturing tolerances that would otherwise reduce the degree of integration that could be achieved reliably.
摘要翻译：半导体器件包括具有集电极区域（31c），发射极区域（31e），基极区域（31b）和覆盖基极区域的部分延伸的发射极配线（37）的至少一个横向型PNP晶体管（31）以防止通道泄漏。集电极和发射极区域直接接触隔离区域（41），但是基极区域经由突起（42）接触隔离区域，优选地与隔离区域形成一体。部分延伸的发射极布线还可以在突起上延伸，这可能性可以用于适应制造公差，否则可以降低可以可靠地实现的集成度。

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