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1. 发明授权

EP0759638B1 High withstand voltage semiconductor device and manufacturing method thereof 失效
标题翻译：具有高耐受电压的半导体器件，及其制造方法
公开(公告)号：EP0759638B1
公开(公告)日：2011-07-13
申请号：EP96104778.4
申请日：1996-03-26
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Akiyama, Hajime
IPC分类号： H01L29/06 , H01L29/08 , H01L29/78 , H01L29/739 , H01L29/10 , H01L29/745 , H01L29/73 , H01L29/74
CPC分类号： H01L29/7824 , H01L29/0615 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/1008 , H01L29/102 , H01L29/1083 , H01L29/402 , H01L29/41725 , H01L29/66674 , H01L29/7302 , H01L29/7393 , H01L29/7394 , H01L29/7436 , H01L29/7455 , H01L29/7801 , H01L29/7835

2. 发明公开

EP1868234A3 High withstand voltage semiconductor device and manufacturing method thereof 失效
标题翻译：耐高电压半导体器件及其制造方法
公开(公告)号：EP1868234A3
公开(公告)日：2009-04-15
申请号：EP07018406.4
申请日：1996-03-26
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Akiyama, Hajime
IPC分类号： H01L29/739 , H01L29/78 , H01L29/06 , H01L29/08 , H01L29/10
CPC分类号： H01L29/7824 , H01L29/0615 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/1008 , H01L29/102 , H01L29/1083 , H01L29/402 , H01L29/41725 , H01L29/66674 , H01L29/7302 , H01L29/7393 , H01L29/7394 , H01L29/7436 , H01L29/7455 , H01L29/7801 , H01L29/7835
摘要： An n - layer (2) is formed on a main surface of a p-type semiconductor substrate (1). A p - diffusion region (5) is formed at a surface of n - layer (2). A p diffusion region (6) is formed contiguous to one end of p - diffusion region (5). A plurality of p diffusion regions (20) containing p-type impurity the concentration of which is higher than that of p - diffusion region (5) are formed in p - diffusion region (5). A p diffusion region (3) is formed such that it is spaced apart from p - diffusion region (5). A gate electrode (9) is formed on a surface of n - layer (2) positioned between p diffusion region (3) and p - diffusion region (5) with an oxide film (10) interposed. A drain electrode (12) is formed in contact with a surface of p diffusion region (6). Furthermore, an n diffusion region (4) is formed adjacent to p diffusion region (3), and a source electrode (11) is formed in contact with both a surface of n diffusion region (4) and a surface p diffusion region (3).

3. 发明授权

EP1158582B1 Pin diode with insulated gate. 失效
标题翻译： PIN二极管的绝缘栅。
公开(公告)号：EP1158582B1
公开(公告)日：2004-09-01
申请号：EP01117369.7
申请日：1996-06-12
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Takahashi, Tetsuo , Nakamura, Katsumi , Minato, Tadaharu , Harada, Masana
IPC分类号： H01L29/739
CPC分类号： H01L29/66348 , H01L29/0692 , H01L29/0696 , H01L29/66356 , H01L29/66378 , H01L29/7391 , H01L29/7397 , H01L29/7455 , H01L29/749 , H01L29/868 , H01L2924/0002 , H01L2924/00

4. 发明公开

EP1202352A3 High breakdown voltage semiconductor device 失效
标题翻译：具有高击穿电压的半导体器件
公开(公告)号：EP1202352A3
公开(公告)日：2003-08-06
申请号：EP01128222.5
申请日：1992-01-29
申请人： Kabushiki Kaisha Toshiba
发明人： Matsudai, Tomoko, Kabushiki Kaisha Toshiba , Nakagawa, Akio, Kabushiki Kaisha Toshiba , Yasuhara, Norio, Kabushiki Kaisha Toshiba
IPC分类号： H01L29/06 , H01L29/745 , H01L29/78 , H01L29/786 , H01L27/092 , H01L21/336 , H01L29/861 , H01L27/06 , H01L27/12 , H01L29/74 , H01L29/749 , H01L29/739
CPC分类号： H01L29/7824 , H01L21/76264 , H01L27/0623 , H01L27/0922 , H01L27/1203 , H01L29/0878 , H01L29/1083 , H01L29/404 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/42368 , H01L29/66772 , H01L29/7394 , H01L29/7436 , H01L29/7455 , H01L29/749 , H01L29/7835 , H01L29/78624 , H01L29/8611
摘要： A semiconductor device which comprises a substrate (1); an insulating layer (2) formed on said substrate (1); a high resistance semiconductor layer (4) formed on said insulating layer (2); a dielectric isolation region (3) formed in said high resistance semiconductor layer (4); an element region formed in said high resistance semiconductor layer (4) isolated by said dielectric isolation region (3) in a lateral direction; a first low resistance region (6) of a first conductivity type formed in a surface portion of said element region; a second low resistance region (7) of a second conductivity type formed in said element region between said first low resistance region (6) and said dielectric isolation region (3) to be separated from said first low resistance region (6); and a third low resistance region (27) of a first conductivity type formed contiguous with the isolation region (3).

5. 发明授权

EP1030372B1 Method of manufacturing a semiconductor device 失效
公开(公告)号：EP1030372B1
公开(公告)日：2003-04-02
申请号：EP00107885.6
申请日：1996-06-12
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Takahashi, Tetsuo , Nakamura, Katsumi , Minato, Tadaharu , Harada, Masana
IPC分类号： H01L29/739 , H01L29/745 , H01L29/749 , H01L21/332 , H01L21/331
CPC分类号： H01L29/66348 , H01L29/0692 , H01L29/0696 , H01L29/66356 , H01L29/66378 , H01L29/7391 , H01L29/7397 , H01L29/7455 , H01L29/749 , H01L29/868 , H01L2924/0002 , H01L2924/00

6. 发明公开

EP1269546A1 BIPOLAR MOSFET DEVICE 有权
标题翻译：双极MOSFET安排
公开(公告)号：EP1269546A1
公开(公告)日：2003-01-02
申请号：EP00958828.6
申请日：2000-09-07
申请人： Demontfort University
发明人： MADATHIL, Sankara, Narayanan, Ekkanath
IPC分类号： H01L29/74 , H01L29/745 , H01L29/749
CPC分类号： H01L29/7455 , H01L29/747 , H01L29/749
摘要： There is disclosed a semiconductor device comprising: at least one cell comprising a base region (32) of a first conductivity type having disposed therein at least one emitter region (36a, 36b) of a second conductivity type; a first well region (22) of a second conductivity type; a second well region (2a) of a first conductivity type; a drift region (24) of a second conductivity type; a collector region (14) of a first conductivity type; a collector contact (16) in which each cell is disposed within the first well region (22) and the first well region (22) is disposed within the second well region (20); the device further comprising: a first gate (61) disposed over a base region (32) so that a MOSFET channel can be formed between an emitter region (36a, 36b) and the first well region (22); the device further comprising: a second gate disposed over the second well region (20) so that a MOSFET channel can be formed between the first well region (22) and the drift region (24).

7. 发明公开

EP1202352A2 High breakdown voltage semiconductor device 失效
标题翻译： Halbleiterbauelement mit hoher Durchbruchspannung
公开(公告)号：EP1202352A2
公开(公告)日：2002-05-02
申请号：EP01128222.5
申请日：1992-01-29
申请人： Kabushiki Kaisha Toshiba
发明人： Matsudai, Tomoko, Kabushiki Kaisha Toshiba , Nakagawa, Akio, Kabushiki Kaisha Toshiba , Yasuhara, Norio, Kabushiki Kaisha Toshiba
IPC分类号： H01L27/06 , H01L27/092 , H01L27/12 , H01L29/06 , H01L29/739 , H01L29/74 , H01L29/744 , H01L29/749 , H01L29/861 , H01L29/78 , H01L21/336
CPC分类号： H01L29/7824 , H01L21/76264 , H01L27/0623 , H01L27/0922 , H01L27/1203 , H01L29/0878 , H01L29/1083 , H01L29/404 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/42368 , H01L29/66772 , H01L29/7394 , H01L29/7436 , H01L29/7455 , H01L29/749 , H01L29/7835 , H01L29/78624 , H01L29/8611
摘要： A semiconductor device which comprises a substrate (1); an insulating layer (2) formed on said substrate (1); a high resistance semiconductor layer (4) formed on said insulating layer (2); a dielectric isolation region (3) formed in said high resistance semiconductor layer (4); an element region formed in said high resistance semiconductor layer (4) isolated by said dielectric isolation region (3) in a lateral direction; a first low resistance region (6) of a first conductivity type formed in a surface portion of said element region; a second low resistance region (7) of a second conductivity type formed in said element region between said first low resistance region (6) and said dielectric isolation region (3) to be separated from said first low resistance region (6); and a third low resistance region (27) of a first conductivity type formed contiguous with the isolation region (3).
摘要翻译：一种半导体器件，包括衬底（1）; 形成在所述基板（1）上的绝缘层（2）; 形成在所述绝缘层（2）上的高电阻半导体层（4）; 形成在所述高电阻半导体层（4）中的介质隔离区（3）; 形成在所述高电阻半导体层（4）中的元件区域，所述高电阻半导体层（4）在横向方向上由所述介电隔离区域（3）隔离; 形成在所述元件区域的表面部分中的第一导电类型的第一低电阻区域（6）形成在所述第一低电阻区域（6）和所述电介质隔离区域（3）之间的所述元件区域中的与所述第一低电阻区域（6）分离的第二导电类型的第二低电阻区域（7）。以及与隔离区域（3）相邻形成的第一导电类型的第三低电阻区域（27）。

8. 发明公开

EP1176643A2 MOS power semiconductor device having a trench gate and method of making the same 审中-公开
标题翻译：具有它们的制备沟槽栅电极和过程MOS功率半导体器件
公开(公告)号：EP1176643A2
公开(公告)日：2002-01-30
申请号：EP01116709.5
申请日：2001-07-17
申请人： Fairchild Semiconductor Corporation
发明人： Zeng, Jun , Dolny, Gary M. , Kocon, Christopher B. , Brush, Linda S.
IPC分类号： H01L29/78 , H01L29/417 , H01L29/423 , H01L29/739 , H01L29/745 , H01L21/336 , H01L21/331 , H01L21/332
CPC分类号： H01L29/7802 , H01L29/41766 , H01L29/66348 , H01L29/66363 , H01L29/7397 , H01L29/7455 , H01L29/7813
摘要： An MOS power device a substrate comprises an upper layer having an upper surface and an underlying drain region, a well region of a first conductance type disposed in the upper layer over the drain region, and a plurality of spaced apart buried gates, each of which comprises a trench that extends from the upper surface of the upper layer through the well region into the drain region. Each trench comprises an insulating material lining its surface, a conductive material filling its lower portion to a selected level substantially below the upper surface of the upper layer, and an insulating material substantially filling the remainder of the trench. A plurality of highly doped source regions of a second conductance type are disposed in the upper layer adjacent the upper portion of each trench, each source region extending from the upper surface to a depth in the upper layer selected to provide overlap between the source regions and the conductive material in the trenches. A groove in each of the highly doped source regions extends through the source regions into the well region and terminates in a nadir. A highly doped body region of a first conductance type is disposed in the well region adjacent both to the nadir of one or more of the grooves and to adjacent source regions penetrated by the grooves. A conductive layer is disposed over the substrate and electrically contacts the body and source regions. A process for fabricating a device produces an MOS power device that avoids the loss of channel width and provides reduced channel resistance without sacrificing device ruggedness and dynamic characteristics.
摘要翻译：的MOS功率器件上的上表面和在底层的漏极区域具有上层的包括基材，在漏极区域中的上层设置的第一电导类型的阱区域中，和间隔开的埋入式栅极的复数，其中的每一个包括沟槽的确从通过所述阱区的上部层向漏区的上表面上延伸。绝缘材料衬里其表面的每个沟槽包括，导电材料填充其下部，以大大低于上层的上表面上选定的水平，和绝缘材料基本上填充所述沟槽的剩余部分。一个第二电导类型的高度掺杂的源极区的多个上层邻近每个沟槽的上部设置，在上层从上表面延伸至一深度各源极区选择为所述源极区域之间提供重叠导电材料在沟槽中。在每个重掺杂源极区的凹槽通过源极区域到阱区延伸，并且在最低点终止。第一电导类型的高度掺杂的体区在相邻的两个的一个或多个槽的最低点和由槽穿入的相邻源极区的阱区被设置。导电层设置在基片和电接触所述主体区和源区。 MOS功率器件的一种制造设备过程中产生确实避免了信道宽度的损失和信道提供降低的电阻而不牺牲设备的耐用性和动态特性。

9. 发明公开

EP1158582A1 Pin diode with insulated gate and manufacturing method thereof 失效
标题翻译： PIN二极管隔离门。
公开(公告)号：EP1158582A1
公开(公告)日：2001-11-28
申请号：EP01117369.7
申请日：1996-06-12
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Takahashi, Tetsuo , Nakamura, Katsumi , Minato, Tadaharu , Harada, Masana
IPC分类号： H01L29/739
CPC分类号： H01L29/66348 , H01L29/0692 , H01L29/0696 , H01L29/66356 , H01L29/66378 , H01L29/7391 , H01L29/7397 , H01L29/7455 , H01L29/749 , H01L29/868 , H01L2924/0002 , H01L2924/00
摘要： A pin diode is formed by a p + collector region (1), an n type buffer region (3), an n - region (5) and an n + cathode region (7). A trench (9) is formed from the surface of n + cathode region (7) through n + cathode region (7) to reach n - region (5). An insulating film (11) is formed along an inner wall surface of trench (9). A gate electrode layer (13) is formed to oppose to the sidewall of n + cathode region (7) with insulating film (11) interposed. A cathode electrode (17) is formed to be electrically connected to n + cathode region (7). An anode electrode (19) is formed to be electrically connected to p + collector region (1). The n + cathode region (7) is formed entirely over the surface between trenches (9) extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.
摘要翻译：一种制造具有在半导体衬底（105）中包括第一，第二和第三沟槽（113a，113b，113c，113d）的多个沟槽（113）的IGBT器件的方法，由此在夹在沟槽113a和113b之间的区域中并且在夹在沟槽113c和113d之间的区域中，形成p型基极区域107，n +发射极区域109和p +接触区域111。在夹在沟槽113b和113c之间的区域中，没有形成p型基极区域107等，只有n +区域105被定位。填充沟槽113b的栅极电极层117和填充沟槽113c的栅极电极层117由导电部分117a一体地形成，并且它们彼此电连接。导电部分117a形成在夹在沟槽113b和113c之间的区域上，绝缘膜129被插入。

10. 发明公开

EP1131848A1 VERFAHREN ZUR HERSTELLUNG EINES LEISTUNGSHALBLEITERS MIT EINER STOPPZONE 有权
标题翻译：一种用于生产功率半目止损ZONE
公开(公告)号：EP1131848A1
公开(公告)日：2001-09-12
申请号：EP99968325.3
申请日：1999-10-15
申请人： EUPECEuropäische Gesellschaft fürLeistungshalbleiter mbH & Co. KG
发明人： SCHULZE, Hans-Joachim , BARTHELMESS, Reiner
IPC分类号： H01L21/322 , H01L21/324 , H01L29/10
CPC分类号： H01L29/7395 , H01L29/1016 , H01L29/7455 , H01L29/749 , Y10S438/92
摘要： The invention relates to a method for producing a silicon power semiconductor device with a stop zone. According to the invention, this stop zone is produced by introducing oxygen and subsequently heating in order to form thermal donors with the oxygen.

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