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1. 发明公开

EP3336846A1 MEMORY WITH SINGLE-EVENT LATCHUP PREVENTION CIRCUITRY 有权
公开(公告)号：EP3336846A1
公开(公告)日：2018-06-20
申请号：EP17201976.2
申请日：2017-11-15
申请人： INTEL Corporation
发明人： ZHANG, Weimin , XU, Yanzhong
IPC分类号： G11C11/412
CPC分类号： H01L27/0921 , G11C5/14 , G11C11/4125 , G11C11/417
摘要： An integrated circuit that includes an array of random-access memory cells is provided. Each memory cell may include inverting circuits formed from pull-up transistors and pull-down transistors and also access transistors coupled to the inverting circuits. The pull-up transistors may be formed in an n-well. The memory cells may also be coupled to single event latch-up (SEL) prevention circuitry. The SEL prevention circuitry may include a clamping circuit, a voltage sensing circuit, and a driver circuit. In response to a single event alpha particle strike at one of the memory cells, a temporary voltage rise may be presented at the clamping circuit. The voltage sensing circuit may detect the voltage rise and direct the driver circuit to bias the n-well into deep reverse bias region. Operated in this way, the SEL prevention circuitry can mitigate SEL while minimizing memory cell leakage.

2. 发明公开

EP3036767A1 LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION 有权
标题翻译： LAYOUT-KONSTRUKTION ZUR ADRESSIERUNG VON ELEKTROMIGRATION
公开(公告)号：EP3036767A1
公开(公告)日：2016-06-29
申请号：EP14758471.8
申请日：2014-08-21
申请人： Qualcomm Incorporated
发明人： RASOULI, Seid Hadi , BRUNOLLI, Michael Joseph , HAU-RIEGE, Christine Sung-An , MALABRY, Mickael , HARISH, Sucheta Kumar , BALASUBRAMANIAN, Prathiba , MEDISETTI, Kamesh , BOMSHTEIN, Nikolay , DATTA, Animesh , KWON, Ohsang
IPC分类号： H01L27/02 , H01L23/528 , H01L27/092 , H01L23/482
CPC分类号： H01L27/0921 , H01L21/823871 , H01L23/4824 , H01L23/522 , H01L27/0207 , H01L27/092 , H01L2924/0002 , H03K17/168 , H03K17/6872 , H01L2924/00
摘要： A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together. A second interconnect on the interconnect level extends in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level couple the first interconnect and the second interconnect together. A third interconnect on the interconnect level extends perpendicular to the length direction and is offset from the set of interconnects to connect the first interconnect and the second interconnect together.
摘要翻译：具有多个PMOS晶体管的CMOS器件，每个具有PMOS漏极和多个NMOS晶体管，每个具有NMOS漏极包括在长度方向上延伸的互连级上的第一互连，以将PMOS漏极连接在一起。互连级上的第二互连在长度方向上延伸以将NMOS漏极连接在一起。在至少一个附加互连级上的一组互连将第一互连和第二互连耦合在一起。互连级上的第三互连件垂直于长度方向延伸，并且从该组互连件偏移以将第一互连和第二互连连接在一起。

3. 发明授权

EP1873831B1 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：EP1873831B1
公开(公告)日：2015-10-21
申请号：EP06122692.4
申请日：2006-10-20
申请人： Fujitsu Semiconductor Limited
发明人： Ema, Taiji c/o FUJITSU LIMITED, , Asano, Masayoshi c/o FUJITSU LIMITED, , Anezaki, Toru c/o FUJITSU LIMITED, , Ariyoshi, Junichi c/o FUJITSU LIMITED,
IPC分类号： H01L27/092 , H01L21/762
CPC分类号： H01L21/823892 , H01L27/0921 , H01L27/11803

4. 发明公开

EP2909860A4 SEMICONDUCTOR DEVICE AND METHOD OF PREVENTING LATCH-UP IN A CHARGE PUMP CIRCUIT 有权转让
标题翻译： VERFAHREN ZUR VERHINDERUNG VON LATCH-UP IN EINER LADEPUMPENSUNGHALBLEITERBAUEMENT
公开(公告)号：EP2909860A4
公开(公告)日：2015-10-14
申请号：EP13848087
申请日：2013-10-02
申请人： SEMTECH CORP
发明人： AEBISCHER DANIEL , CHEVROULET MICHEL
IPC分类号： H01L27/092 , H01L21/8238 , H02M3/07
CPC分类号： H01L27/0629 , H01L21/823892 , H01L27/0921 , H02M3/073 , H02M2003/078
摘要： A charge pump circuit includes a substrate and first well region formed in the substrate. A first transistor includes first and second conduction regions disposed in the first well region. A second well region is formed in the substrate. A third well region is formed within the second well region. A second transistor includes first and second conduction regions disposed in the third well region. The second well region and third well region are coupled to a common terminal. The common terminal receives a local potential and the first well region and second well region are commonly maintained at the local potential. The first transistor and second transistor operate within the charge pump cell. A plurality of charge pump cells can be cascaded together with an output of a first charge pump cell coupled to an input of a second charge pump cell.
摘要翻译：电荷泵电路包括基板和形成在基板中的第一阱区域。第一晶体管包括设置在第一阱区中的第一和第二导电区。在衬底中形成第二阱区。在第二阱区域内形成第三阱区域。第二晶体管包括设置在第三阱区中的第一和第二导电区域。第二阱区域和第三阱区域耦合到公共端子。公共端子接收局部电位，并且第一阱区域和第二阱区域通常保持在局部电位。第一晶体管和第二晶体管在电荷泵单元内工作。多个电荷泵单元可以与耦合到第二电荷泵单元的输入的第一电荷泵单元的输出级联在一起。

5. 发明公开

EP2581938A4 HIGH-VOLTAGE INTEGRATED CIRCUIT DEVICE 有权
标题翻译：带集成电路的高压设备
公开(公告)号：EP2581938A4
公开(公告)日：2014-12-31
申请号：EP12757637
申请日：2012-03-13
申请人： FUJI ELECTRIC CO LTD
发明人： YAMAJI MASAHARU
IPC分类号： H01L21/761 , G05F3/02 , H01L27/092
CPC分类号： G05F3/02 , H01L21/761 , H01L27/0921 , H01L27/0922
摘要： A high-voltage integrated circuit device (100) comprises, in a surface layer of a p semiconductor substrate (1), an n region (3) which is a high-side floating-potential region, an n - region (4) which becomes a high-voltage junction terminating region (93), and an n - region (2) which is an L-VDD potential region. A low-side circuit portion (91) is disposed in an n - region (2). Below a pickup electrode (59) disposed in the high-voltage junction terminating region (93), a universal contact region (58) in Ohmic contact with the pickup electrode is disposed. The universal contact region (58) has a p + region (56) and an n + region (57) that are disposed in alternating contact along a surface of the p semiconductor substrate (1). By disposing the universal contact region (58) in this way, the quantity of carriers flowing into the low-side circuit portion (91) can be reduced when a negative surge voltage is input. Consequently, erroneous operation and destruction due to latchup of a logic portion of the low-side circuit portion (91) can be prevented.
摘要翻译：高电压集成电路器件（100）在p型半导体衬底（1）的表面层中包括作为高侧浮动电位区域的n区域（3），成为高压结端接区域（93）和作为L-VDD电势区域的n区域（2）。低侧电路部分（91）设置在n区（2）中。在设置在高压结终止区域（93）中的拾取电极（59）的下方设置有与拾取电极欧姆接触的通用接触区域（58）。通用接触区域（58）具有沿着p半导体衬底（1）的表面交替接触地设置的p +区域（56）和n +区域（57）。通过以这种方式设置通用接触区域（58），当输入负浪涌电压时，流入低侧电路部分（91）的载流子的数量可以减少。因此，可以防止由于低侧电路部分（91）的逻辑部分的闭锁而导致的错误操作和破坏。

6. 发明授权

EP2535932B1 Puce de circuit intégré comprenant un dispositif de protection contre des attaques 有权
标题翻译：芯片集成电路对攻击保护装置
公开(公告)号：EP2535932B1
公开(公告)日：2014-03-19
申请号：EP12168455.9
申请日：2012-05-18
申请人： STMicroelectronics (Rousset) SAS
发明人： Lisart, Mathieu , Sarafianos, Alexandre
IPC分类号： H01L23/58 , H01L21/763
CPC分类号： H01L23/576 , H01L21/763 , H01L23/585 , H01L27/0921 , H01L2924/0002 , H01L2924/00

7. 发明授权

EP1840965B1 Adjustable transistor body bias generation circuitry with latch-up prevention 有权转让
标题翻译：可调晶体管基片电压产生电路与抗闩锁保护
公开(公告)号：EP1840965B1
公开(公告)日：2013-09-18
申请号：EP07003008.5
申请日：2007-02-13
申请人： Altera Corporation
发明人： Srinivas, Perisetty
IPC分类号： H01L27/092 , H03K19/003 , G05F3/20
CPC分类号： H01L27/0921 , H03K19/00315 , H03K2217/0018

8. 发明授权

EP1436846B1 MOS DEVICES AND CORRESPONDING MANUFACTURING METHODS AND CIRCUITS 有权
标题翻译： MOS安排及相关方法和电路
公开(公告)号：EP1436846B1
公开(公告)日：2011-07-27
申请号：EP02778470.1
申请日：2002-10-08
申请人： Intersil Americas Inc.
发明人： BEASOM, James, D.
IPC分类号： H01L29/78 , H01L29/165 , H01L21/336 , H01L21/84 , H01L21/762 , H03K17/691 , H03K17/082 , H03K17/785
CPC分类号： H01L29/7813 , H01L27/0921 , H01L29/1095 , H01L29/165 , H01L29/7801 , H01L29/7809 , H01L29/7835
摘要： MOS devices such a DMOS transistors (100) with reduced parasitic bipolar transistor action comprising a substrate (102) having a working surface, at least one body region (114) and for each body region a source region (118) and a layer of narrow band gap material (132). Each body region is formed in the substrate proximate the working surface of the substrate. Each layer of narrow band gap material is positioned in a portion of its associated body region and proximate the working surface of the substrate. The narrow band gap material may be SiGe. A switching power supply control circuit and a solid state relay integrated circuit comprising the MOS device are also disclosed.

9. 发明授权

EP1443564B1 Semiconductor device in which punchthrough is prevented 有权
标题翻译：半导体器件防止“穿通”的突破
公开(公告)号：EP1443564B1
公开(公告)日：2008-12-24
申请号：EP04001612.3
申请日：2004-01-26
申请人： NEC Electronics Corporation
发明人： Kawaguchi, Hiroshi , Mizuno, Riki
IPC分类号： H01L27/092
CPC分类号： H01L21/823892 , H01L27/0921

10. 发明授权

EP1751800B1 VERFAHREN ZUM LÖSCHEN VON IN EINER SCHALTUNG AUFTRETENDEN LATCH-UPS SOWIE ANORDNUNGEN ZUM DURCHFÜHREN DES VERFAHRENS 有权
标题翻译：方法清除电路中发生的LATCH-UPS和安排执行该方法
公开(公告)号：EP1751800B1
公开(公告)日：2008-03-26
申请号：EP05754592.3
申请日：2005-06-01
申请人： Deutsches Zentrum für Luft- und Raumfahrt e.V.
发明人： GRUBER, Robin , SCHOTT, Jörg , TEGTMEIER, Bernd
IPC分类号： H01L27/092
CPC分类号： H01L27/0921 , H01L23/62 , H01L2924/0002 , H03K17/0822 , H01L2924/00
摘要： According to the invention, in order to suppress a latch-up, the supply voltage is switched off following the detection of a latch-up, charge located in the circuit is reduced with the aid of a short-circuiting switch, and the detection of a low voltage is temporarily canceled when the supply voltage is gradually increased again. A protective circuit is assigned to an electronic circuit in order to protect the radiation-sensitive components thereof, said electronic circuit being subdivided into groups of active circuit components accepting a similar amount of current in a predefined area and a protective circuit being assigned to at least one of said groups of active circuit components accepting approximately the same amount of current in a predefined area. In order to prevent the output current from influencing the output voltage, a current-detecting unit is mounted upstream of a voltage-regulating unit.

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