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1. 发明授权

EP2656391B1 COLUMN IV TRANSISTORS FOR PMOS INTEGRATION 有权转让
公开(公告)号：EP2656391B1
公开(公告)日：2018-08-22
申请号：EP11850350.7
申请日：2011-12-20
申请人： Intel Corporation
发明人： GLASS, Glenn A. , MURTHY, Anand S.
IPC分类号： H01L29/78 , H01L21/336 , H01L21/285 , H01L29/45 , H01L29/49 , H01L29/66 , H01L29/167 , H01L29/165
CPC分类号： H01L29/0676 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3215 , H01L21/76831 , H01L23/535 , H01L27/092 , H01L27/0924 , H01L29/0615 , H01L29/0847 , H01L29/086 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/456 , H01L29/4966 , H01L29/66477 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66681 , H01L29/66931 , H01L29/7785 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in Sight of this disclosure, including both planar and non-planar transistor structures {e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type de vices, but can be used for n-type de vices if so desired.

2. 发明公开

EP3312886A1 SELECTIVE GERMANIUM P-CONTACT METALIZATION THROUGH TRENCH 审中-公开
标题翻译：选择性锗P-接触金属化通过沟槽
公开(公告)号：EP3312886A1
公开(公告)日：2018-04-25
申请号：EP17193291.6
申请日：2011-09-30
申请人： INTEL Corporation
发明人： Glass, Glenn A. , Murthy, Anand, S. , Ghani, Tahir
IPC分类号： H01L29/78 , H01L21/336 , H01L21/285 , H01L29/45 , H01L29/49 , H01L29/66 , H01L29/167 , H01L29/165
CPC分类号： H01L29/0676 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3215 , H01L21/76831 , H01L23/535 , H01L27/092 , H01L27/0924 , H01L29/0615 , H01L29/0847 , H01L29/086 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/456 , H01L29/4966 , H01L29/66477 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66681 , H01L29/66931 , H01L29/7785 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in Sight of this disclosure, including both planar and non-planar transistor structures {e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type de vices, but can be used for n-type de vices if so desired.
摘要翻译：公开了用于形成相对于常规器件具有降低的寄生接触电阻的晶体管器件的技术。例如，可以使用标准接触堆叠，例如在硅或硅锗（SiGe）源极/漏极区域上的一系列金属来实施所述技术。根据这种实施例的一个示例，在源极/漏极和接触金属之间提供中间硼掺杂锗层，以显着降低接触电阻。鉴于本公开，包括平面和非平面晶体管结构（例如，FinFET）以及应变和非应变沟道结构，许多晶体管配置和合适的制造工艺将是显而易见的。分级缓冲可以用来减少失配错位。这些技术特别适用于实现p型设备，但如果需要的话，可用于n型设备。

3. 发明公开

EP2544238A2 Solid-state image pick-up device and imaging system using the same 审中-公开
标题翻译：固体摄像装置及使用其的成像系统
公开(公告)号：EP2544238A2
公开(公告)日：2013-01-09
申请号：EP12182192.0
申请日：2005-02-15
申请人： Canon Kabushiki Kaisha
发明人： Inoue, Shunsuke
IPC分类号： H01L27/146
CPC分类号： H01L27/14601 , H01L21/28525 , H01L23/53271 , H01L27/14612 , H01L27/14623 , H01L27/1463 , H01L27/14636 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a solid-state image pick-up device without shading in the dark state, and capable of making a dynamic range and a S/N high. Reference numeral 505 denotes an N-type cathode of a photodiode, 506 denoting a surface P-type region for forming the photodiode into an embedded structure, 508a denoting an N-type high concentration region which forms a floating diffusion and which is also a drain region of a transfer MOS transistor. Reference character 508b denotes a polysilicon lead-out electrode brought into direct contact with the N-type high concentration region. Light incident from the surface passes through an aperture without a metal third layer 525 to enter into the photodiode. Among incident lights, light reflected by the top surface of a gate electrode 504 of the transfer MOS transistor is reflected by a first layer metal 521 right above the polysilicon, so as to repeats reflection a plurality of times to attenuate sufficienly before entering into the floating diffusion section, thereby making the aliasing extremely small.
摘要翻译：本发明提供一种在黑暗状态下没有阴影的固态图像拾取装置，并且能够使动态范围和S / N较高。附图标记505表示光电二极管的N型阴极，506表示用于将光电二极管形成为嵌入结构的表面P型区域，508a表示形成浮动扩散的N型高浓度区域，并且其也是漏极传输MOS晶体管的区域。附图标记508b表示与N型高浓度区域直接接触的多晶硅引出电极。从表面入射的光穿过没有金属第三层525的孔进入光电二极管。在入射光中，由传输MOS晶体管的栅电极504的顶表面反射的光被多晶硅正上方的第一层金属521反射，从而多次重复反射以在进入浮动之前充分衰减扩散部分，从而使混叠非常小。

4. 发明公开

EP2461352A1 Method of manufacturing low resistivity contacts on n-type germanium 有权
标题翻译： Verfahren zur Herstellung von Kontakten mit geringem Widerstand au-n-Germanium
公开(公告)号：EP2461352A1
公开(公告)日：2012-06-06
申请号：EP11191678.9
申请日：2011-12-02
申请人： IMEC , Katholieke Universiteit Leuven K.U. Leuven R&D
发明人： Martens, Koen , Loo, Roger , Kittl, Jorge
IPC分类号： H01L21/285
CPC分类号： H01L21/28525
摘要： A method for manufacturing an electrical contact between n-type germanium (10) and a layer (12, 13) of material with electrical resistivity smaller than 1x10 -2 Ωcm, the electrical contact having a specific contact resistivity below 10 -4 Ωcm 2 , the method comprising
obtaining a semiconductor substrate having atop a germanium region (10) doped with n-type dopants at a first doping level,
forming an interfacial silicon layer (11) overlying the n-type doped germanium region (10), the interfacial silicon layer (11) being doped with n-type dopants at a second doping level and having a thickness higher than the critical thickness, such that the interfacial layer (11) is at least partially relaxed, and
forming a layer (12, 13) of material with electrical resistivity smaller than 1x10 -2 Ωcm overlying the interfacial silicon layer (11).
The invention also provides corresponding semiconductor devices.
摘要翻译：一种用于制造n型锗（10）和电阻率小于1×10 -2 cm的材料层（12,13）之间的电接触的方法，所述电接触具有低于10 -4 cm的特定接触电阻如图2所示，该方法包括获得在第一掺杂水平上掺杂有n型掺杂剂的锗区（10）顶部的半导体衬底，形成覆盖在n型掺杂锗区（10）上的界面硅层（11），界面硅层（11）以第二掺杂水平掺杂n型掺杂剂并且具有高于临界厚度的厚度，使得界面层（11）至少部分松弛，并形成层（12,13 ）的电阻率小于界面硅层（11）上的1×10 -2 cm的材料。本发明还提供相应的半导体器件。

5. 发明授权

EP1374290B1 IMPROVED PROCESS FOR DEPOSITION OF SEMICONDUCTOR FILMS 有权
标题翻译：半导体层的改进分离过程
公开(公告)号：EP1374290B1
公开(公告)日：2008-07-02
申请号：EP02706308.0
申请日：2002-02-12
申请人： ASM America, Inc.
发明人： TODD, Michael, A.
IPC分类号： H01L21/205
CPC分类号： C23C16/0272 , B82Y10/00 , B82Y30/00 , C23C16/22 , C23C16/24 , C23C16/30 , C23C16/308 , C23C16/325 , C23C16/345 , C23C16/36 , C23C16/56 , C30B25/02 , C30B29/06 , H01L21/02422 , H01L21/0243 , H01L21/0245 , H01L21/0251 , H01L21/02529 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/02592 , H01L21/02595 , H01L21/02598 , H01L21/0262 , H01L21/02667 , H01L21/2257 , H01L21/28035 , H01L21/28044 , H01L21/28194 , H01L21/28525 , H01L21/28556 , H01L21/3185 , H01L21/32055 , H01L28/84 , H01L29/127 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66181 , H01L29/66242 , H01L31/1804 , H01L31/182 , H01L31/202 , Y02E10/546 , Y02E10/547 , Y02P70/521 , Y10S438/933
摘要： Chemical vapor deposition processes utilize higher order silanes and germanium precursors as chemical precursors. The processes have high deposition rates yet produce more uniform films, both compositionally and in thickness, than films prepared using conventional chemical precursors. In preferred embodiments, trisilane is employed to deposit SiGe-containing films that are useful in the semiconductor industry in various applications such as transistor gate electrodes.

6. 发明公开

EP1866956A2 SINGLE WAFER THERMAL CVD PROCESSES FOR HEMISPHERICAL GRAINED SILICON AND NANO-CRYSTALLINE GRAIN-SIZED POLYSILICON 审中-公开
标题翻译：与单晶片热CVD工艺FOR半球形颗粒状硅和纳米晶粒定形多晶硅
公开(公告)号：EP1866956A2
公开(公告)日：2007-12-19
申请号：EP06738202.8
申请日：2006-03-14
申请人： Applied Materials, Inc.
发明人： LI, Ming , CUNNINGHAM, Kevin , PANAYIL, Sheeba , XING, Guangcai , IYER, R. Suryanarayanan
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： C23C16/24 , C23C16/56 , H01L21/28035 , H01L21/28525 , H01L28/84 , H01L29/4925
摘要： Methods for depositing hemispherical grained silicon layers and nanocrystalline grain-sized polysilicon layers are provided. The hemispherical grained silicon layers and nanocrystalline grain-sized polysilicon layers are deposited in single substrate chemical vapor deposition chambers. The hemispherical grained silicon layers and nanocrystalline grain-sized polysilicon layers may be used as electrode layers in semiconductor devices. In one aspect, a two step deposition process is provided to form a nanocrystalline grain-sized polysilicon layer with a reduced roughness.

7. 发明授权

EP0684632B1 Method of forming a film at low temperature for a semiconductor device 失效
标题翻译：一种用于在低温下的半导体装置的制造薄膜的方法
公开(公告)号：EP0684632B1
公开(公告)日：2007-12-12
申请号：EP95107485.5
申请日：1995-05-16
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD
发明人： Mizuno, Bunji , Okada, Kenji , Nakayama, Ichirou
IPC分类号： H01L21/205 , H01L21/285 , H01L21/316 , H01L21/318 , H01L21/336
CPC分类号： H01L21/02238 , C23C16/48 , C23C16/482 , C23C16/484 , C23C16/485 , C23C16/486 , C23C16/487 , H01L21/02167 , H01L21/0217 , H01L21/02211 , H01L21/02227 , H01L21/02247 , H01L21/02252 , H01L21/02277 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/28512 , H01L21/28525 , H01L21/28556 , H01L21/31608

8. 发明公开

EP1295346A4 LOW AREA METAL CONTACTS FOR PHOTOVOLTAIC DEVICES 审中-公开
标题翻译：光伏器件小的界面的金属触点
公开(公告)号：EP1295346A4
公开(公告)日：2006-12-13
申请号：EP01929101
申请日：2001-05-04
申请人： UNISEARCH LTD
发明人： WENHAM STUART ROSS , KOSCHIER LINDA MARY
IPC分类号： H01L21/205 , H01L21/285 , H01L31/0224 , H01L31/04 , H01L31/18 , H01L21/20 , H01L21/28
CPC分类号： H01L31/1804 , H01L21/28525 , H01L31/022425 , H01L31/022441 , Y02E10/547 , Y02P70/521
摘要： In a method for forming a contact on semiconductor surface, a crystalline silicon surface is first oxidized, following which an aluminium layer is deposited onto the oxide layer. A layer of amorphous silicon is then deposited onto the aluminium layer. The structure is then heated to a temperature below the aluminium/silicon eutectic temperature to locally reduce the oxide layer in regions where the quality/density of the oxide layer is lower. Simultaneously, the amorphous silicon penetrates into the aluminium layer, in which it has a high mobility. With continued heating, the aluminium penetrates completely through the oxide layer in localized regions, exposing the crystalline silicon surface. The exposed silicon surface provides a sight for nucleating epitaxial growth, which occurs rapidly as silicon within the aluminium continuously feeds the solid phase epitaxial growth process. The rapid epitaxial growth facilitates the formation of a new crystalline silicon layer that occupies the original space where the oxide layer was grown. The epitaxially grown silicon provides a bridge between the original p-type silicon surface and the metal layer and is itself doped p-type such that the metal is in electrical contact with the original silicon surface via the epitaxially grown silicon in the localized regions where the oxide layer was reduced.

9. 发明授权

EP1464077B1 VERFAHREN ZUM HERSTELLEN EINES KONDENSATORS 有权
标题翻译：方法制造电容器
公开(公告)号：EP1464077B1
公开(公告)日：2006-11-08
申请号：EP03706355.9
申请日：2003-01-10
申请人： Infineon Technologies AG
发明人： DAHL, Claus , STAHRENBERG, Knut , WILBERTZ, Christoph
IPC分类号： H01L21/02
CPC分类号： H01L28/60 , H01L21/28525 , H01L27/0805 , H01L29/94
摘要： A method for producing a capacitor involves preparing a rough structure provided with a substrate (210) and with at least one dielectric layer (224, 226), whereby a first region and a second region of the substrate (210) are separated by a non-conductive layer (212, 214, 216). Above the first and second region, an electrically conductive layer (228) is applied to the at least one dielectric layer (224, 226). In addition, a mask layer (230) is applied to the electrically conductive layer, whereby this layer is structured in order to produce a first mask (230) above the first region. The inventive method also involves an etching away of the electrically conductive layer (230) and of at least one of the dielectric layers (226) in the second region by using the first mask and involves a finishing processing of an active element in the second region.

10. 发明公开

EP1374291A2 DEPOSITION METHOD OVER MIXED SUBSTRATES USING TRISILANE 有权
标题翻译：分离工艺对混合作基质BY丙
公开(公告)号：EP1374291A2
公开(公告)日：2004-01-02
申请号：EP02721028.5
申请日：2002-02-12
申请人： ASM America, Inc.
发明人： TODD, Michael, A.
IPC分类号： H01L21/205
CPC分类号： C23C16/0272 , B82Y10/00 , B82Y30/00 , C23C16/22 , C23C16/24 , C23C16/30 , C23C16/308 , C23C16/325 , C23C16/345 , C23C16/36 , C23C16/56 , C30B25/02 , C30B29/06 , H01L21/02422 , H01L21/0243 , H01L21/0245 , H01L21/0251 , H01L21/02529 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/02592 , H01L21/02595 , H01L21/02598 , H01L21/0262 , H01L21/02667 , H01L21/2257 , H01L21/28035 , H01L21/28044 , H01L21/28194 , H01L21/28525 , H01L21/28556 , H01L21/3185 , H01L21/32055 , H01L28/84 , H01L29/127 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66181 , H01L29/66242 , H01L31/1804 , H01L31/182 , H01L31/202 , Y02E10/546 , Y02E10/547 , Y02P70/521 , Y10S438/933
摘要： Trisilane is used in chemical vapor deposition methods to deposit silicon-containing films over mixed substrates. Such methods are useful in semiconductor manufacturing to provide a variety of advantages, including uniform deposition over heterogeneous surfaces, high deposition rates, and higher manufacturing productivity. An example is in forming the base region of a heterojunction bipolar transistor, including simultaneous deposition over both single crystal semiconductor surfaces and amorphous insulating regions.

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