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1. 发明授权

EP0018739B1 A decoder circuit for a semiconductor memory device 失效
标题翻译：半导体存储器件的解码器电路
公开(公告)号：EP0018739B1
公开(公告)日：1989-11-02
申请号：EP80301175.8
申请日：1980-04-11
申请人： FUJITSU LIMITED
发明人： Isogai, Hideaki
IPC分类号： H03M7/00 , G11C8/00
CPC分类号： G11C11/415 , G11C11/4087 , H03M7/005

2. 发明公开

EP0100677A2 Semiconductor devices including lateral-type transistors 失效
标题翻译： Halbleiteranordnungen mit Laltaltransistoren。
公开(公告)号：EP0100677A2
公开(公告)日：1984-02-15
申请号：EP83304446.4
申请日：1983-08-01
申请人： FUJITSU LIMITED
发明人： Isogai, Hideaki , Ono, Chikai
IPC分类号： H01L29/06
CPC分类号： H01L29/402 , H01L21/76 , H01L21/761 , H01L27/1025 , H01L29/1008 , H01L29/735
摘要： A semiconductor device comprises at least one lateral-type PNP transistor (31) having a collector region (31c), an emitter region (31e), a base region (31b), and partially extended emitter wiring (37) covering the base region, to protect against channel leakage. The collector and emitter regions directly contact an isolation region (41), but the base region contacts the isolation region via a projection (42), preferably formed integrally with the isolation region. The partially extended emitter wiring may also extend over the projection, which possibility can serve to accommodate manufacturing tolerances that would otherwise reduce the degree of integration that could be achieved reliably.
摘要翻译：半导体器件包括具有集电极区域（31c），发射极区域（31e），基极区域（31b）和覆盖基极区域的部分延伸的发射极配线（37）的至少一个横向型PNP晶体管（31）以防止通道泄漏。集电极和发射极区域直接接触隔离区域（41），但是基极区域经由突起（42）接触隔离区域，优选地与隔离区域形成一体。部分延伸的发射极布线还可以在突起上延伸，这可能性可以用于适应制造公差，否则可以降低可以可靠地实现的集成度。

3. 发明授权

EP0018172B1 High speed electronic switching circuit 失效
标题翻译：高速电子切换电路
公开(公告)号：EP0018172B1
公开(公告)日：1983-08-03
申请号：EP80301153.5
申请日：1980-04-10
申请人： FUJITSU LIMITED
发明人： Isogai, Hideaki
IPC分类号： H03K17/04 , H03K17/60 , G11C7/06
CPC分类号： G11C11/415 , H01L27/0783 , H03K17/04166

4. 发明公开

EP0031681A3 Decoder circuit 失效
标题翻译：解码器电路
公开(公告)号：EP0031681A3
公开(公告)日：1982-02-17
申请号：EP80304586
申请日：1980-12-18
申请人： FUJITSU LIMITED
发明人： Tanaka, Miki , Isogai, Hideaki
IPC分类号： G11C11/40
CPC分类号： H03K17/62 , G11C11/415 , G11C11/416 , H03M7/005
摘要： A decoder circuit comprises:
a differential amplifier circuit 41 which receives one or a plurality of line selection signals B which are to be decoded; switching circuits 31a-1, 31a-2, for switching predetermined line systems 50a, 51a in high or low level states according to the output signal B, B supplied from the differential amplifier circuit 41, and constant current supply circuits 21, 22 for supplying constant current to predetermined lines 13a, 14a of the above line systems 50a, 51a according to the signal supplied from the switching circuits 31a-1, 31a-2. The switching circuits 31a-1, 31a-2 are connected in parallel with respect to the constant current supply circuits 21, 22.

5. 发明公开

EP0031681A2 Decoder circuit 失效
标题翻译：解码器电路
公开(公告)号：EP0031681A2
公开(公告)日：1981-07-08
申请号：EP80304586.3
申请日：1980-12-18
申请人： FUJITSU LIMITED
发明人： Tanaka, Miki , Isogai, Hideaki
IPC分类号： G11C11/40
CPC分类号： H03K17/62 , G11C11/415 , G11C11/416 , H03M7/005
摘要： A decoder circuit comprises:

a differential amplifier circuit 41 which receives one or a plurality of line selection signals B which are to be decoded; switching circuits 31a-1, 31a-2, for switching predetermined line systems 50a, 51a in high or low level states according to the output signal B, B supplied from the differential amplifier circuit 41, and constant current supply circuits 21, 22 for supplying constant current to predetermined lines 13a, 14a of the above line systems 50a, 51a according to the signal supplied from the switching circuits 31a-1, 31a-2. The switching circuits 31a-1, 31a-2 are connected in parallel with respect to the constant current supply circuits 21, 22.
摘要翻译：解码器电路包括：差分放大器电路41，其接收要被解码的一个或多个行选择信号B; 用于根据从差分放大器电路41提供的输出信号B，B将预定线路系统50a，51a切换为高电平或低电平状态的开关电路31a-1,31a-2以及用于供应电流的恒定电流供应电路21,22 根据从开关电路31a-1,31a-2提供的信号将恒定电流提供给上述线路系统50a，51a的预定线路13a，14a。开关电路31a-1,31a-2相对于恒流源电路21,22并联连接。

6. 发明公开

EP0024894A1 Decoder circuit 失效
标题翻译：译码电路。
公开(公告)号：EP0024894A1
公开(公告)日：1981-03-11
申请号：EP80302907.3
申请日：1980-08-21
申请人： FUJITSU LIMITED
发明人： Isogai, Hideaki
IPC分类号： H03K13/25 , G11C8/00
CPC分类号： H03M7/005 , G11C8/10 , G11C11/415
摘要： A decoder circuit for a semiconductor memory device includes input terminal gates (G 00 -G 03 ) which receive address signal bits; first decoder lines (DL1) for decoding output signals of some of the inputterminal gates, and multi-emitter transistors (Ga-Gd, 0 7 ) each having emitter terminals connected to the first decoder lines and a collector terminal connected to a power source and to the base of a transistor (Ga-Gd,Q 7 ) which drives one of a plurality of groups of output terminal gates (G 10 -G 25 ), the multi-emitter transistors turning the driving transistor on or off depending upon the potential of the first decoder lines. Second decoder lines (DLll) are provided for decoding output signals from the remainder (G 02 ,G 03 ) of the input terminal gates. Further multi-emitter transistors (G 10 -G 25 ,Q 7 ) have their emitter terminals connected to the second decoder lines, and each has a collector terminal connected via a resistor to the emitter of the associated transistor (Ga-Gd,Q 7 ) for driving the group of output terminal gates and to the base of an output transistor (G io -G 25 ,Q 7 ), the multi-emitter transistors turning the output transistor on or off depending upon the potential of the second decoder lines and upon the emitter potential of the transistor (Ga-Gd,Q 7 ) which drives the group of the output terminal gates. Diode matrices can be used in place of multi-emitter transistors. In the present invention, constant current sources (I 1 ) are connected to the second decoder lines and emitter-follower transistors (Q 8 -Q 9 ) are inserted between the power source and the second decoder lines and are turned on or off by the output signals of the said remainder of the input terminal gates.

7. 发明公开

EP0018739A3 A decoder circuit for a semiconductor memory device 失效
标题翻译：半导体存储器件的解码器电路
公开(公告)号：EP0018739A3
公开(公告)日：1981-01-07
申请号：EP80301175
申请日：1980-04-11
申请人： FUJITSU LIMITED
发明人： Isogai, Hideaki
IPC分类号： H03K13/25 , G11C08/00
CPC分类号： G11C11/415 , G11C11/4087 , H03M7/005
摘要： A decoder circuit for a semiconductor memory device having a short build-up time for the potential on the decoder lines whilst using only a limited number of constant current sources in the decoder comprises a sequence of address signal input terminals (A o , A 1 , ...) a number of address buffers (21,22, ...) a number of pairs of decoder lines do, d 0 , d 1 , d 1 , ...) connected to the address buffers with each pair of the decoder lines being connected between its address buffer and a constant currentsource (S 2 ), a major part of the current from each constant current source (S 2 ) passing through only one decoder line of each pair at any instant, a sequence of word lines (W o , W 1 . W 2 , ...) and a number of word drivers (41, 42) each having a matrix of diodes (D 1 , D 2 , ...) of a multi-emitter transistor (Q m ). This arrangement halves the number of current sources used with the decoder lines and eliminates those used in the word drivers whilst not increasing the build-up time of potentials applied to the decoder lines.

8. 发明授权

EP0100677B1 Semiconductor devices including lateral-type transistors 失效
标题翻译：包括横向晶体管的半导体器件
公开(公告)号：EP0100677B1
公开(公告)日：1989-03-22
申请号：EP83304446.4
申请日：1983-08-01
申请人： FUJITSU LIMITED
发明人： Isogai, Hideaki , Ono, Chikai
IPC分类号： H01L29/06
CPC分类号： H01L29/402 , H01L21/76 , H01L21/761 , H01L27/1025 , H01L29/1008 , H01L29/735

9. 发明授权

EP0031226B1 A decoder circuit 失效
标题翻译：解码器电路
公开(公告)号：EP0031226B1
公开(公告)日：1986-12-10
申请号：EP80304497.3
申请日：1980-12-12
申请人： FUJITSU LIMITED
发明人： Isogai, Hideaki , Takahashi, Yukio
IPC分类号： G11C8/00 , G11C11/40 , H03K19/08
CPC分类号： G11C8/10 , G11C8/00 , G11C8/06 , G11C11/4116 , G11C11/415 , H03K5/15 , H03K19/086

10. 发明公开

EP0031226A3 A decoder circuit 失效
标题翻译：解码器电路
公开(公告)号：EP0031226A3
公开(公告)日：1983-07-20
申请号：EP80304497
申请日：1980-12-12
申请人： FUJITSU LIMITED
发明人： Isogai, Hideaki , Takahashi, Yukio
IPC分类号： G11C08/00 , G11C11/40 , H03K19/08
CPC分类号： G11C8/10 , G11C8/00 , G11C8/06 , G11C11/4116 , G11C11/415 , H03K5/15 , H03K19/086
摘要： The decoder circuit has output gates 11 a to 11 d. Each output gate (11a) has an output driver transistor TW3 for driving an output line (WO). The transistor TW3 is turned ON and OFF in dependence upon the output from a multi-emitter transistor TW1 and TW2 providing a logic AND circuit, which receives address signals AO and A1. A current switching circuit comprising transistor TW5, inverter transistor TW6 and constant current source 15 is connected to a voltage source line Vcc. Current from the voltage source line Vcc is supplied to the base of transistor TW3 from the current switching circuit when the AND circuit provides a "1" output to inverter transistor TW6. In this way resistor RX is not involved in supply of current to line W0 so that a rise characteristic for that line can be sharpened.

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