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1. 发明公开

EP2685504A1 Transistor à effet tunnel 审中-公开
标题翻译： Tunneleffekttransistor
公开(公告)号：EP2685504A1
公开(公告)日：2014-01-15
申请号：EP13174928.5
申请日：2013-07-03
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives , CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
发明人： Le Royer, Cyrille , Cristoloveanu, Sorin , Wan, Jing , Zaslavsky, Alexander
IPC分类号： H01L29/739 , H01L21/331 , H01L29/165
CPC分类号： H01L29/78 , H01L29/165 , H01L29/66227 , H01L29/66356 , H01L29/66477 , H01L29/7302 , H01L29/739 , H01L29/7391
摘要： L'invention concerne un transistor à effet tunnel (TFET) dont la région de drain (140, 440, 540) comporte une première zone dopée (111, 411, 511) selon un dopage d'un premier type (N+), et une deuxième zone dopée (112, 412, 512) selon un dopage d'un deuxième type (P) formant avec la première zone une jonction (PN+). On obtient ainsi un fort courant à l'état passant (I ON ) par amplification bipolaire.
摘要翻译：晶体管具有源极区（160），漏极区（140）和栅电极。源极区域和漏极区域中的给定区域包括掺杂掺杂型的半导体区域（111）。给定区域包括掺杂有另一掺杂类型的另一半导体区（112）。用前掺杂区形成结。源极区域和漏极区域中的另一给定区域包括掺杂有前掺杂型的第三半导体区域（113）。对于晶体管的制造方法，还包括独立权利要求。

2. 发明公开

EP2261990A3 High withstand voltage semiconductor device and manufacturing method thereof 失效
标题翻译：耐高电压半导体器件及其制造方法
公开(公告)号：EP2261990A3
公开(公告)日：2012-02-22
申请号：EP10182259.1
申请日：1996-03-26
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Akiyama, Hajime
IPC分类号： H01L29/739 , H01L29/78 , H01L29/06 , H01L29/08 , H01L21/332 , H01L29/73 , H01L29/745 , H01L29/10
CPC分类号： H01L29/7824 , H01L29/0615 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/1008 , H01L29/102 , H01L29/1083 , H01L29/402 , H01L29/41725 , H01L29/66674 , H01L29/7302 , H01L29/7393 , H01L29/7394 , H01L29/7436 , H01L29/7455 , H01L29/7801 , H01L29/7835
摘要： An n - layer (2) is formed on a main surface of a p-type semiconductor substrate (1). A p - diffusion region (5) is formed at a surface of n - layer (2). A p diffusion region (6) is formed contiguous to one end of p - diffusion region (5). A plurality of p diffusion regions (20) containing p-type impurity the concentration of which is higher than that of p - diffusion region (5) are formed in p - diffusion region (5). A p diffusion region (3) is formed such that it is spaced apart from p - diffusion region (5). A gate electrode (9) is formed on a surface of n - layer (2) positioned between p diffusion region (3) and p - diffusion region (5) with an oxide film (10) interposed. A drain electrode (12) is formed in contact with a surface of p diffusion region (6). Furthermore, an n diffusion region (4) is formed adjacent to p diffusion region (3), and a source electrode (11) is formed in contact with both a surface of n diffusion region (4) and a surface p diffusion region (3).

3. 发明公开

EP2346077A1 DRAM memory cell having a vertical bipolar injector and method of operating the same 审中-公开
标题翻译： DRAM-Speicherzelle mit einem vertikalen bipolaren Injektor und entsprechendes Betriebsverfahren
公开(公告)号：EP2346077A1
公开(公告)日：2011-07-20
申请号：EP10187682.9
申请日：2010-10-15
申请人： S.O.I. Tec Silicon on Insulator Technologies
发明人： Mazure, Carlos , Ferrant, Richard
IPC分类号： H01L27/07 , H01L27/108 , H01L29/78 , G11C11/404 , H01L29/786 , H01L29/08 , H01L29/73
CPC分类号： H01L29/7841 , G11C11/404 , G11C2211/4016 , H01L27/0711 , H01L27/10802 , H01L29/086 , H01L29/7302
摘要： According to a first aspect, the invention relates to a memory cell comprising:
- an FET transistor having a source (S), a drain (D) and a floating body (FB) between the source and the drain,
- an injector that can be controlled to inject a charge into the floating body of the FET transistor, the injector consisting of a bipolar transistor having an emitter (15), a base and a collector formed by the body of the FET transistor,
the cell being characterized in that the emitter of the bipolar transistor is arranged so that the source of the FET transistor serves as the base for the bipolar transistor.
The invention also extends to a memory array comprising a plurality of memory cells according to the first aspect of the invention, and to a method of controlling such a memory cell.
摘要翻译：根据第一方面，本发明涉及一种存储单元，其包括： - FET源晶体管，其在源极和漏极之间具有源极（S），漏极（D）和浮体（FB）， - 可以被控制以将电荷注入到FET晶体管的浮动体中，该注入器由具有发射极（15）的双极晶体管，由FET晶体管的本体形成的基极和集电极组成，该电池的特征在于，双极晶体管的发射极被配置为使得FET晶体管的源极用作双极晶体管的基极。本发明还扩展到包括根据本发明的第一方面的多个存储单元的存储器阵列，以及一种控制这种存储单元的方法。

4. 发明授权

EP0250086B2 Electrical circuit utilizing a concentric collector PNP transistor 失效
标题翻译：电电路包括具有同心集电极PNP晶体管
公开(公告)号：EP0250086B2
公开(公告)日：1996-09-11
申请号：EP87304272.5
申请日：1987-05-14
申请人： GENERAL MOTORS CORPORATION
发明人： Shreve, John R. , Kearney, Mark B.
IPC分类号： H03K17/08 , G05F1/573 , H01L29/72 , H01L29/41
CPC分类号： H01L29/7302 , G05F1/573 , H03K17/0826

5. 发明公开

EP0657944A3 Gate controlled lateral bipolar junction transistor and method of fabrication thereof 失效
标题翻译： Gartesteuerter横向双相变压器和Verfahren zur Herstellung。
公开(公告)号：EP0657944A3
公开(公告)日：1995-08-02
申请号：EP94308956.5
申请日：1994-12-02
申请人： NORTHERN TELECOM LIMITED
发明人： Mahli, Duljit S. , Kung, William , Deen, M. Jamal , Ilowski, John , Kovacic, Stephen J.
IPC分类号： H01L29/739 , H01L27/07 , H01L29/735
CPC分类号： H03G1/007 , H01L27/0722 , H01L29/7302 , H01L29/735 , H01L29/7393
摘要： A gate controlled lateral bipolar junction transistor (GCLBJT) device for an integrated circuit and a method of fabrication thereof are provided. The GCLBJT resembles a merged field effect transistor and lateral bipolar transistor, i.e. a lateral bipolar transistor having base, emitter and collector terminals and a fourth terminal for controlling a gate electrode overlying an active base region. The device is operable as an electronically configurable lateral transistor. Advantageously a heavily doped buried layer provides a base electrode having a base contact which surrounds and encloses the collector. The surface region between emitter and collector is characterised by lightly doped regions adjacent and contiguous with the heavily doped emitter and collector, which effectively reduce the base width of the bipolar transistor and improve operation for analogue applications. A threshold adjust implant in the surface of the base region under the gate electrode allows for control of threshold voltage of the surface MOS channel. Performance parameters of the bipolar transistor may be adjusted via a signal to the fourth i.e., gate, terminal, to control inversion under the gate, thereby controlling the path of carriers between the emitter and collector. Transistor performance characteristics such as common-emitter current gain, unity-gain frequency, and the low frequency noise properties are all variable quantities which can be specified electronically, i.e. they are programmable by a signal applied to the gate. Concurrent use of field effect and bipolar injection phenomenon within the same device yield the salient device characteristics. Applications include mixer and modulation circuits.
摘要翻译：提供了一种用于集成电路的栅极控制横向双极结型晶体管（GCLBJT）器件及其制造方法。 GCLBJT类似于合并的场效应晶体管和横向双极晶体管，即具有基极，发射极和集电极端子的横向双极晶体管，以及用于控制覆盖有源基极区域的栅电极的第四端子。该器件可操作为电子可配置的横向晶体管。有利地，重掺杂掩埋层提供具有包围和封闭收集器的基极接触的基极。发射极和集电极之间的表面区域的特征在于与重掺杂的发射极和集电极相邻并邻近的轻掺杂区域，这有效地降低了双极晶体管的基极宽度并改善了模拟应用的操作。在栅电极下方的基极区域的表面中的阈值调整植入允许控制表面MOS沟道的阈值电压。双极晶体管的性能参数可以通过信号调整到第四个即栅极，以控制栅极下的反相，从而控制发射极和集电极之间的载流子路径。诸如共发射极电流增益，单位增益频率和低频噪声特性的晶体管性能都是可以电子指定的可变量，即它们可以通过施加到栅极的信号来编程。同时使用场效应和双极注入现象产生显着的器件特性。应用包括混频器和调制电路。

6. 发明公开

EP0603737A2 Hybrid bipolar/field-effect power transistor in group III-V material system 失效
标题翻译：混合双极/ Feldeffekt-Leistung晶体管材料呕吐III-V型。
公开(公告)号：EP0603737A2
公开(公告)日：1994-06-29
申请号：EP93120248.5
申请日：1993-12-16
申请人： Hughes Aircraft Company
发明人： Larson, Lawrence E. , Asbeck, Peter , Brown, Julia J.
IPC分类号： H01L29/72
CPC分类号： H01L29/7392 , H01L29/7302 , H01L29/7391 , H01L29/8083
摘要： A hybrid power transistor (40) includes a vertical PNP bipolar transistor (42) having a floating base (46). A junction-gate type field-effect transistor (FET) (62) has a lateral N-type channel (64, 66) and a vertical electron injection path (54) from the channel (64, 66) into the base (46) of the bipolar transistor (42). The FET channel current and thereby the electron injection current are controlled by the FET gate voltage. The injection current conductivity modulates the base (46) and thereby controls the collector current of the bipolar transistor (42). The FET (62) does not require a gate insulating layer, enabling fabrication of the hybrid transistor (40) in the group III-V material system.
摘要翻译：混合功率晶体管（40）包括具有浮动基极（46）的垂直PNP双极晶体管（42）。结栅型场效应晶体管（FET）（62）具有从沟道（64,66）到基底（46）的横向N型沟道（64,66）和垂直电子注入路径（54）的双极晶体管（42）。 FET沟道电流，从而电子注入电流由FET栅极电压控制。注入电流电导率调制基极（46），从而控制双极晶体管（42）的集电极电流。 FET（62）不需要栅极绝缘层，能够在III-V族材料体系中制造混合晶体管（40）。

7. 发明授权

EP0316988B1 Lateral high-voltage transistor 失效
标题翻译：横向高压晶体管
公开(公告)号：EP0316988B1
公开(公告)日：1992-06-10
申请号：EP88202470.6
申请日：1988-11-04
申请人： Philips Electronics N.V.
发明人： Ludikhuize, Adrianus Willem
IPC分类号： H01L29/72 , H01L29/08
CPC分类号： H01L29/7302

8. 发明公开

EP2757580A1 Bipolar cmos dmos (bcd) processes 审中-公开
标题翻译：双极-CMOS-DMOS-Prozesse
公开(公告)号：EP2757580A1
公开(公告)日：2014-07-23
申请号：EP13152160.1
申请日：2013-01-22
申请人： NXP B.V.
发明人： Boos, Priscilla , Van Dalen, Rob , Spaan, Erick
IPC分类号： H01L21/84 , H01L27/12 , H01L21/762
CPC分类号： H01L27/0623 , H01L21/76221 , H01L21/76281 , H01L21/8249 , H01L21/84 , H01L27/1203 , H01L29/7302
摘要： There is disclosed a method of manufacturing a high voltage, HV, device with a BCD process. The method comprises undertaking a Local Oxidation of Silicon, LOCOS, fabrication process to form a recessed insulating structure prior to undertaking a Bipolar CMOS DMOS, BCD, fabrication process to form a plurality of device layers on the recessed insulating structure.
摘要翻译：公开了一种制造具有BCD工艺的高压HV装置的方法。该方法包括进行硅局部氧化，LOCOS制造工艺，以在进行双极CMOS DMOS，BCD制造工艺之前形成凹陷绝缘结构，以在凹陷绝缘结构上形成多个器件层。

9. 发明公开

EP2725615A1 Semiconductor device comprising a diode and method for producing such a device 有权转让
标题翻译：一种半导体器件，包括制造该装置的一个二极管和方法
公开(公告)号：EP2725615A1
公开(公告)日：2014-04-30
申请号：EP12190455.1
申请日：2012-10-29
申请人： IMEC
发明人： Hellings, Geert , Scholz, Mirko , Linten, Dimitri
IPC分类号： H01L27/02 , H01L29/866 , H01L21/329 , H01L29/06 , H01L29/36
CPC分类号： H01L23/60 , H01L27/0255 , H01L29/0649 , H01L29/0688 , H01L29/36 , H01L29/6609 , H01L29/66098 , H01L29/66106 , H01L29/66234 , H01L29/7302 , H01L29/735 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： The present invention is related to a semiconductor device comprising a diode junction between two semiconductor regions of different doping types, in particular between an upper portion of an active area and the remainder of said area, said active area being defined in a substrate surface between two field dielectric regions. The upper portion is a portion of the active area that is lower in width than the active area itself. In a preferred embodiment, the device of the invention is an ESD comprising such a diode. In addition, the active area is provided with a doping profile, exhibiting a maximum value at the surface of said active area, and changing to a minimum value at a higher depth, said depth preferably being higher than half the depth of the upper portion. The diode does not require an ESD implant for lowering the holding voltage. As such the device and method according to the invention allow to reduce the number of processing steps in the production of ESD and other devices comprising a diode junction.
摘要翻译：本发明，特别地之间的有源区域和所述区域的剩余部分的上部涉及到半导体器件，包括不同的掺杂类型的两个半导体区域之间的二极管结，所述的基底表面限定二者之间的活性区场电介质区域。上部是有源区域的一部分所做的是在宽度上比所述有源区本身低。在优选实施方案中，本发明的装置是包括寻求二极管的ESD。此外，有源区设置有掺杂分布，参展在所述有源区的表面上的最大值，并且在较高的深度变化到最小值，所述深度优选为比上部的深度的一半更高。二极管不要求ESD植入物用于降低保持电压。作为检查的装置和方法雅丁发明允许以减少的生产ESD的包括二极管结的处理步骤和其它设备的数量。

10. 发明公开

EP1868234A2 High withstand voltage semiconductor device and manufacturing method thereof 失效
标题翻译：耐高电压半导体器件及其制造方法
公开(公告)号：EP1868234A2
公开(公告)日：2007-12-19
申请号：EP07018406.4
申请日：1996-03-26
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Akiyama, Hajime
IPC分类号： H01L21/336 , H01L29/06 , H01L29/78
CPC分类号： H01L29/7824 , H01L29/0615 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/1008 , H01L29/102 , H01L29/1083 , H01L29/402 , H01L29/41725 , H01L29/66674 , H01L29/7302 , H01L29/7393 , H01L29/7394 , H01L29/7436 , H01L29/7455 , H01L29/7801 , H01L29/7835
摘要： An n - layer (2) is formed on a main surface of a p-type semiconductor substrate (1). A p - diffusion region (5) is formed at a surface of n - layer (2). A p diffusion region (6) is formed contiguous to one end of p - diffusion region (5). A plurality of p diffusion regions (20) containing p-type impurity the concentration of which is higher than that of p - diffusion region (5) are formed in p - diffusion region (5). A p diffusion region (3) is formed such that it is spaced apart from p - diffusion region (5). A gate electrode (9) is formed on a surface of n - layer (2) positioned between p diffusion region (3) and p - diffusion region (5) with an oxide film (10) interposed. A drain electrode (12) is formed in contact with a surface of p diffusion region (6). Furthermore, an n diffusion region (4) is formed adjacent to p diffusion region (3), and a source electrode (11) is formed in contact with both a surface of n diffusion region (4) and a surface p diffusion region (3).

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