专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP4379806A1 HIGH POWER DENSITY RECTIFIER DEVICE 审中-公开
公开(公告)号：EP4379806A1
公开(公告)日：2024-06-05
申请号：EP23213791.9
申请日：2023-12-01
申请人： Littelfuse Semiconductor (Wuxi) Co., Ltd.
发明人： Zhou, Jifeng , Zhang, Glenda , He, Lei
IPC分类号： H01L29/06 , H01L21/329 , H01L29/861
CPC分类号： H01L29/861 , H01L29/0661 , H01L29/0619 , H01L29/66136
摘要： A high power density rectifier diode apparatus, structure and associated methods thereof. The apparatus includes a substrate silicon layer, a middle silicon layer coupled to the substrate layer, an upper silicon layer coupled to the middle silicon layer, a cathode terminal coupled to the substrate silicon layer, an anode terminal coupled to the upper silicon layer, and one or more trench termination layers formed in the substrate silicon layer and at least a portion of the middle silicon layer. The trench termination layers are configured to be formed on at least one side of the substrate silicon layer and at least a portion of the middle silicon layer. The substrate silicon layer is at least one of the following: an n-type layer, a p-type layer, and any combination thereof.

2. 发明公开

EP4376089A1 SILICON CARBIDE INTEGRATED DEVICE AND METHOD FOR MANUFACTURING AN INTEGRATED DEVICE 审中-公开
公开(公告)号：EP4376089A1
公开(公告)日：2024-05-29
申请号：EP23209667.7
申请日：2023-11-14
申请人： STMicroelectronics S.r.l.
发明人： FRAGAPANE, Leonardo
IPC分类号： H01L29/06 , H01L29/12 , H01L29/78
CPC分类号： H01L29/1608 , H01L29/66068 , H01L29/7811 , H01L29/0619 , H01L29/0692
摘要： An integrated device (11) includes: a semiconductor structural layer (5), including silicon carbide and having a first conductivity type; a power device (2) integrated in the structural layer (5); and an edge termination structure (3), extending in a ring around the power device (2) and having a second conductivity type. The edge termination structure (3) includes a plurality of ring structures (10, 11, 12) each arranged around the power device (2) and in contiguous pairs. At least a first one (10, 11) of the ring structures (10, 11, 12) comprises a transition region (10b, 11b) contiguous to a second one (11, 12) of the ring structures (10, 11, 12). The transition region (10b, 11b) includes connection regions (10c, 11c), having the second conductivity type, connected to the second one (11, 12) of the ring structures (10, 11, 12) and alternating with charge control regions (10d, 11d) having the first conductivity type.

3. 发明授权

EP4080582B1 GALLIUM NITRIDE DEVICE, SWITCHING POWER TRANSISTOR, DRIVE CIRCUIT, AND GALLIUM NITRIDE DEVICE PRODUCTION METHOD 审中-实审
公开(公告)号：EP4080582B1
公开(公告)日：2024-04-24
申请号：EP22169177.7
申请日：2022-04-21
IPC分类号： H01L29/778 , H01L29/417 , H01L29/06 , H01L29/20
CPC分类号： H01L29/7786 , H01L29/2003 , H01L29/0619 , H01L29/41725 , H01L29/41758 , H01L29/0653

4. 发明授权

EP2613356B1 IE type trench gate IGBT 有权
公开(公告)号：EP2613356B1
公开(公告)日：2018-07-04
申请号：EP13150257.7
申请日：2013-01-04
申请人： Renesas Electronics Corporation
发明人： Matsuura, Hitoshi
IPC分类号： H01L29/739 , H01L29/40
CPC分类号： H01L29/7397 , H01L29/0619 , H01L29/0696 , H01L29/0804 , H01L29/0821 , H01L29/0865 , H01L29/0882 , H01L29/1095 , H01L29/404 , H01L29/407 , H01L29/41708 , H01L29/4236 , H01L29/66348 , H01L29/7395 , H01L2924/0002 , H01L2924/00
摘要： In a method of further enhancing the performance of a narrow active cell IE type trench gate IGBT having the width of active cells narrower than that of inactive cells, it is effective to shrink the cells so that the IE effects are enhanced. However, when the cells are shrunk simply, the switching speed is reduced due to increased gate capacitance. A cell formation area (10) of the IE type trench gate IGBT is basically composed of first linear unit cell areas (40f) having linear active cell areas (40a), second linear unit cell areas (40s) having linear hole collector areas (40c) and linear inactive cell areas (40i) disposed therebetween.

5. 发明公开

EP3336880A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD 有权
公开(公告)号：EP3336880A1
公开(公告)日：2018-06-20
申请号：EP17200145.5
申请日：2017-11-06
申请人： Renesas Electronics Corporation
发明人： HISADA, Kenichi , ARAI, Koichi
IPC分类号： H01L21/336 , H01L29/78 , H01L29/06
CPC分类号： H01L29/66068 , H01L21/02236 , H01L21/02255 , H01L21/02271 , H01L21/045 , H01L21/049 , H01L23/291 , H01L23/3171 , H01L29/0615 , H01L29/0619 , H01L29/063 , H01L29/0634 , H01L29/0692 , H01L29/0696 , H01L29/1608 , H01L29/511 , H01L29/518 , H01L29/7395 , H01L29/7811
摘要： A semiconductor device includes: a first conductivity type semiconductor substrate made of silicon carbide; a second conductivity type body region in a device region of the semiconductor substrate; a first conductivity type source region formed in the body region; and a gate electrode formed on the body region through gate insulating films. The semiconductor device further includes, in a termination region of the semiconductor substrate, second conductivity type RESURF layers, and an edge termination region formed in the RESURF layers. Then, the RESURF layers and a front surface of the semiconductor substrate adjacent to the RESURF layers are covered by an oxidation-resistant insulating film.

6. 发明公开

EP3324444A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：EP3324444A1
公开(公告)日：2018-05-23
申请号：EP17201514.1
申请日：2017-11-14
申请人： Renesas Electronics Corporation
发明人： Mori, Takahiro
IPC分类号： H01L29/78 , H01L29/06 , H01L21/336
CPC分类号： H01L29/0649 , H01L21/76224 , H01L29/0619 , H01L29/0653 , H01L29/0692 , H01L29/402 , H01L29/4238 , H01L29/66659 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要： A semiconductor device according to one embodiment includes a semiconductor substrate (SUB) having a first surface (FS), an insulating isolation structure (ISL) having a first depth (D1), and a gate electrode (GE). The semiconductor substrate has source and drain regions (SR, DRA), a reverse conductivity region (RCR) having a second depth (D2), a body region (BR), and a drift region (DRI). The source region, the drift region, and the drain region are of a first conductivity type, and the body region and the reverse conductivity region are of a second conductivity type which is opposite to the first conductivity type. The insulating isolation structure is disposed between the drain region and the reverse conductivity region. The first depth is larger than the second depth.

7. 发明公开

EP3200236A4 SILICON CARBIDE SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE, AND METHOD FOR DESIGNING SILICON CARBIDE SEMICONDUCTOR DEVICE 有权
公开(公告)号：EP3200236A4
公开(公告)日：2018-05-23
申请号：EP14880381
申请日：2014-09-24
申请人： SHINDENGEN ELECTRIC MFG
发明人： INOUE TETSUTO , SUGAI AKIHIKO , NAKAMURA SHUNICHI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12
CPC分类号： H01L29/1608 , G06F17/5068 , H01L21/02529 , H01L21/76895 , H01L23/535 , H01L29/0619 , H01L29/0623 , H01L29/0642 , H01L29/0661 , H01L29/0696 , H01L29/407 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/66068 , H01L29/66666 , H01L29/66734 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L29/7827
摘要： A silicon carbide semiconductor device includes a silicon carbide layer 32 of a first conductivity type, a silicon carbide layer 36 of a second conductivity type, a gate trench 20, a gate electrode 79 provided in the gate trench 20, and a protection trench 10 formed to a greater depth than the gate trench 20. A region in the horizontal direction that includes both the gate trench 20 and a protection trench 10 that surrounds only a part of the gate trench 20 in the horizontal direction is a cell region, and a region in the horizontal direction that includes a protection trench 10 and in which a gate pad 89 or a lead electrode connected to the gate pad 89 is disposed is a gate region. A second conductive member 81 is provided above the gate trench 20 in the cell region and in the gate region, and the second conductive member 81 is disposed to extend from above the gate trench 20 in the cell region to the gate region through above a part of the cell region in which the protection trench 10 is not provided.

8. 发明公开

EP3238260A1 REVERSE-CONDUCTING SEMICONDUCTOR DEVICE 有权转让
标题翻译：反向导电半导体器件
公开(公告)号：EP3238260A1
公开(公告)日：2017-11-01
申请号：EP15819822.6
申请日：2015-12-22
申请人： ABB Technology AG
发明人： STORASTA, Liutauras , CORVASCE, Chiara , LE GALLO, Manuel , RAHIMO, Munaf , KOPTA, Arnost
IPC分类号： H01L29/739 , H01L29/78 , H01L29/06
CPC分类号： H01L29/7395 , H01L29/0615 , H01L29/0619 , H01L29/063 , H01L29/0692 , H01L29/0696 , H01L29/0834 , H01L29/0865 , H01L29/1004 , H01L29/1095 , H01L29/36 , H01L29/402 , H01L29/7396 , H01L29/7811 , H01L29/7819 , H01L29/7823
摘要： A reverse-conducting MOS device is provided having an active cell region and a termination region. Between a first and second main side. The active cell region comprises a plurality of MOS cells with a base layer of a second conductivity type. On the first main side a bar of the second conductivity type, which has a higher maximum doping concentration than the base layer, is arranged between the active cell region and the termination region, wherein the bar is electrically connected to the first main electrode. On the first main side in the termination region a variable-lateral-doping layer of the second conductivity type is arranged. A protection layer of the second conductivity type is arranged in the variable-lateral-doping layer, which protection layer has a higher maximum doping concentration than the maximum doping concentration of the variable-lateral-doping layer in a region attached to the protection layer.
摘要翻译：提供具有有源单元区域（10）和终端区域（12）的反向导通MOS器件（1）。在第一和第二主侧（20,25）之间。有源单元区域（10）包括具有第二导电类型的基极层（4）的多个MOS单元（11）。在第一主侧（20）上，具有比基极层（4）更高的最大掺杂浓度的第二导电类型的条（8）被布置在有源单元区（10）与终端区（12）之间），其中杆（8）电连接到第一主电极（2）。在终端区（12）的第一主侧（20）上布置第二导电类型的可变横向掺杂层（7）。第二导电类型的保护层（9）被布置在可变横向掺杂层（7）中，该保护层（9）具有比可变横向掺杂层（8）的最大掺杂浓度更高的最大掺杂浓度在附着到保护层（9）的区域中。

9. 发明授权

EP3164890B1 METHOD FOR MANUFACTURING A POWER SEMICONDUCTOR DEVICE WITH THICK TOP-METAL-DESIGN 有权转让
标题翻译：用顶部金属设计制造功率半导体器件的方法
公开(公告)号：EP3164890B1
公开(公告)日：2017-11-01
申请号：EP16717322.8
申请日：2016-04-13
申请人： ABB Schweiz AG
发明人： MATTHIAS, Sven , PAPADOPOULOS, Charalampos , CORVASCE, Chiara , KOPTA, Arnost
IPC分类号： H01L21/331 , H01L29/739 , H01L29/417 , H01L29/06
CPC分类号： H01L21/32131 , H01L21/304 , H01L29/0619 , H01L29/0661 , H01L29/402 , H01L29/41708 , H01L29/41741 , H01L29/41766 , H01L29/66348 , H01L29/7397
摘要： The present application contemplates a method for manufacturing a power semiconductor device. The method comprises: providing a wafer of a first conductivity type, the wafer having a first main side and a second main side opposite to the first main side, and the wafer including an active cell area, which extends from the first main side to the second main side, in a central part of the wafer and a termination area surrounding the active cell area in an orthogonal projection onto a plane parallel to the first main side; forming a metallization layer on the first main side to electrically contact the wafer in the active cell area, wherein the surface of the metallization layer, which faces away from the wafer, defines a first plane parallel to the first main side; forming an isolation layer on the first main side in the termination area, wherein the surface of the isolation layer facing away from the wafer defines a second plane parallel to the first main side; after the step of forming the metallization layer and after the step of forming the isolation layer, mounting the wafer with its first main side to a flat surface of a chuck; and thereafter thinning the wafer from its second main side by grinding while pressing the second main side of the wafer onto a grinding wheel by applying a pressure between the chuck and the grinding wheel, wherein the first plane is further away from the wafer than a third plane, which is parallel to the second plane and arranged at a distance of 1 μm from the second plane in a direction towards the wafer.

10. 发明公开

EP3231008A1 METHOD FOR MANUFACTURING A WIDE BANDGAP JUNCTION BARRIER SCHOTTKY DIODE 有权转让
标题翻译：制造宽带结电阻肖特基二极管的方法
公开(公告)号：EP3231008A1
公开(公告)日：2017-10-18
申请号：EP15794507.2
申请日：2015-11-04
申请人： ABB Schweiz AG
发明人： MINAMISAWA, Renato , RAHIMO, Munaf
IPC分类号： H01L21/329 , H01L29/872 , H01L21/28 , H01L29/06 , H01L29/40 , H01L29/45 , H01L29/47 , H01L29/24 , H01L29/20
CPC分类号： H01L21/0485 , H01L21/048 , H01L21/0495 , H01L29/0619 , H01L29/1608 , H01L29/2003 , H01L29/401 , H01L29/45 , H01L29/47 , H01L29/6606 , H01L29/66212 , H01L29/872
摘要： A method for manufacturing a wide bandgap junction barrier Schottky diode having an anode side and a cathode side is provided, wherein an (n+) doped cathode layer is arranged on the cathode side, at least on p doped anode layer is arranged on the anode side, an (n−) doped drift layer is arranged between the cathode layer and the at least one anode layer, which drift layer extends to the anode side, wherein the following manufacturing steps are performed: a) providing an (n+) doped wide bandgap substrate, b) creating the drift layer on the cathode layer, c) creating the at least one anode layer on the drift layer, d) applying a first metal layer on the anode side on top of the drift layer for forming a Schottky contact, characterized in, that e) creating a second metal layer on top of at least one anode layer, wherein after having created the first and the second metal layer, a metal layer on top of the at least one anode layer has a second thickness and a metal layer on top of the drift layer has a first thickness, wherein the second thickness is smaller than the first thickness, f) then performing a first heating step at a first temperature, by which due the second thickness being smaller than the first thickness an ohmic contact is formed at the interface between the second metal layer and the at least one anode layer, wherein performing the first heating step such that a temperature below the first metal layer is kept below a temperature for forming an ohmic contact.
摘要翻译：提供了一种制造具有阳极侧（10）和阴极侧（15）的宽带隙结型势垒肖特基二极管（1）的方法，其中在阴极侧（15）上布置（n +）掺杂阴极层（2），在阳极侧（10）上布置至少一个p掺杂阳极层（3），在阴极层（2）和至少一个阳极层（3）之间布置（n-）掺杂漂移层（4）），所述漂移层（4）延伸到阳极侧（10），其中执行以下制造步骤：a）提供（n +）掺杂的宽带隙衬底（100），b）（2），c）在漂移层（4）上形成至少一个阳极层（3），d）在漂移层（4），用于形成肖特基接触（55），其特征在于，e）在至少一个阳极层（3）的顶部上形成第二金属层（6），其中在形成第一和第二金属层 5，6），一个见面在所述至少一个阳极层（3）的顶部上具有第二厚度（64）并且在所述漂移层（4）的顶部上的金属层具有第一厚度（54），其中所述第二厚度（64）是 f）然后在第一温度下执行第一加热步骤（63），由此第二厚度（64）小于第一厚度（54），因此欧姆接触（65）是小于第一厚度形成在所述第二金属层（6）和所述至少一个阳极层（3）之间的界面处，其中执行所述第一加热步骤（63），使得所述第一金属层（5）下方的温度保持低于形成欧姆接触。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式