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1. 发明公开

EP4407668A1 SEMICONDUCTOR ARRANGEMENT WITH GUARD STRUCTURE 审中-公开
公开(公告)号：EP4407668A1
公开(公告)日：2024-07-31
申请号：EP23153758.0
申请日：2023-01-27
申请人： Infineon Technologies Dresden GmbH & Co . KG
发明人： HIRLER, Franz , WEIS, Rolf
IPC分类号： H01L21/761 , H01L21/225 , H01L21/762
CPC分类号： H01L21/761 , H01L21/76237 , H01L21/2254
摘要： A semiconductor arrangement and an electronic circuit with a semiconductor arrangement are disclosed. The semiconductor arrangement includes: a semiconductor body (100) having a first region (1) of a first doping type, a second region (2) of the first doping type, and a third region (3) of a second doping type complementary to the first doping type; and a guard structure (4) arranged in the third region (3) between the first and second regions (1, 2). The first region (1) and the second region (2) are spaced apart from each other in a lateral direction (x) of the semiconductor body (100), and the third region (3) is arranged between the first and second regions (1, 2). The guard structure (4) includes a first guard region (5) and a second guard region (6) arranged next to each other in the first lateral direction (x), wherein the first guard region (5) includes a doped region (51) of the second doping type, and wherein the second guard region (6) includes a doped region (61) of the first doping type.

2. 发明公开

EP3327790A1 LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTING DEVICES WITH LIGHTLY-DOPED ISOLATION LAYERS 审中-公开
公开(公告)号：EP3327790A1
公开(公告)日：2018-05-30
申请号：EP17203915.8
申请日：2017-11-27
申请人： NXP USA, Inc.
发明人： Grote, Bernhard , Lin, Xin , Mehrotra, Saumitra Raj , Radic, Ljubo , Zhu, Ronghua
IPC分类号： H01L29/78 , H01L21/761 , H01L29/06 , H01L29/10
CPC分类号： H01L29/7823 , H01L21/26513 , H01L21/761 , H01L29/063 , H01L29/0634 , H01L29/0646 , H01L29/0653 , H01L29/0696 , H01L29/0869 , H01L29/0886 , H01L29/1083 , H01L29/36 , H01L29/402 , H01L29/4916 , H01L29/66681 , H01L29/7835
摘要： An example laterally diffused metal oxide semiconducting (LDMOS) device includes a semiconductor substrate of a first conductivity type, active MOS regions, and a lightly-doped isolation layer (LDIL) of a second conductivity type. The active MOS regions include source and drain regions and a plurality of PN junctions. The LDIL is formed above and laterally along the semiconductor substrate, and located between the semiconductor substrate and at least a part of the active MOS regions. The LDIL is doped with dopant of the second conductivity type to cause, in response to selected voltages applied to the LDMOS device, the plurality of PN junctions to deplete each other and to support a voltage drop between the source and drain regions along the LDIL.

3. 发明公开

EP3273483A1 PROCÉDÉ DE FABRICATION D'UN TRANSISTOR BIPOLAIRE DE TYPE PNP EN PARALLÈLE DE LA FABRICATION D'UN TRANSISTOR BIPOLAIRE DE TYPE NPN ET DE TRANSISTORS MOS À CANAL N ET À CANAL P 有权
标题翻译：方法制造制造的双极晶体管NPN型和MOS晶体管CHANNEL N和P沟道的双极晶体管PNP型的并行
公开(公告)号：EP3273483A1
公开(公告)日：2018-01-24
申请号：EP17156146.7
申请日：2017-02-14
申请人： STMicroelectronics (Crolles 2) SAS
发明人： CHEVALIER, Pascal , AVENIER, Grégory
IPC分类号： H01L29/66 , H01L29/732 , H01L27/06 , H01L27/07 , H01L29/08 , H01L29/423 , H01L29/06
CPC分类号： H01L21/82285 , H01L21/02532 , H01L21/02639 , H01L21/26513 , H01L21/28518 , H01L21/31111 , H01L21/761 , H01L21/8249 , H01L27/0623 , H01L27/0826 , H01L27/1022 , H01L29/0646 , H01L29/0649 , H01L29/0804 , H01L29/0821 , H01L29/42304 , H01L29/66272 , H01L29/732
摘要： L'invention concerne un procédé de fabrication d'un transistor PNP en parallèle de la fabrication de transistors NPN, NMOS et PMOS, ce procédé de fabrication du transistor bipolaire PNP comprenant les étapes successives : dépôt, sur un substrat (1) semiconducteur dopé P, d'une première couche (5) semiconductrice divisée en des première, deuxième et troisième régions (15, 17, 19) ; implantation profonde dans le substrat (1) d'un caisson isolant (21) ; implantation de premier, deuxième et troisième caissons (25, 27, 35, 37) respectivement dopés N, P et P entre lesdites première, deuxième et troisième régions (19, 17, 15) et le caisson isolant (21) ; dépôt d'une première couche isolante et d'une deuxième couche isolante sélectivement gravables par rapport à la première sur la troisième région (15) et création d'un masque ; épitaxie sélective d'une deuxième couche semiconductrice dopée P dans ledit masque.
摘要翻译：本发明涉及一种方法，用于并行地制造PNP晶体管用于生产NPN晶体管，PMOS和NMOS，所述方法包括连续步骤的PNP双极型晶体管的制造方法的：沉积，基板（1）掺杂的半导体P于被分成第一，第二和第三区域（15,17,19）的第一半导体层（5）; 在绝缘盒（21）的基板（1）中深植入; 注入第一，第二和第三腔室（25，27，35，37）分别掺杂的N，P和P之间的所述第一，第二和第三区域（19，17，15）和所述绝缘壳体（21）; 在第三区域（15）上沉积相对于第一绝缘层和第二绝缘层可选择性蚀刻的第一绝缘层和第二绝缘层，并形成掩模; 在所述掩模中的第二P掺杂半导体层的选择性外延。

4. 发明公开

EP3136426A1 METHOD FOR PRODUCING A JUNCTION FIELD EFFECT TRANSISTOR ON A SEMICONDUCTOR SUBSTRATE 有权
标题翻译：用于生产TRANSITION场效应晶体管在半导体基板
公开(公告)号：EP3136426A1
公开(公告)日：2017-03-01
申请号：EP15182155.0
申请日：2015-08-24
申请人： IMEC VZW
发明人： Hellings, Geert , Van der Plas, Geert , Scholz, Mirko
IPC分类号： H01L21/337 , H01L29/808 , H01L29/10 , H01L21/265 , H01L29/861 , H01L21/329 , H01L21/761
CPC分类号： H01L27/0928 , H01L21/0332 , H01L21/265 , H01L21/266 , H01L21/761 , H01L27/0629 , H01L27/098 , H01L29/1058 , H01L29/456 , H01L29/66128 , H01L29/66893 , H01L29/66901 , H01L29/808 , H01L29/8611
摘要： The invention is related to a method for producing a junction field effect transistor on a semiconductor substrate, wherein the steps of depositing a pre-metal dielectric layer and producing contact openings in said PMD layer precede the step of implanting a well with dopants of a first and second type and wherein the thickness of the PMD layer is configured so that a channel is created by implanting dopants through the PMD layer. The method of the invention allows to produce the JFET on an interposer substrate using a limited number of lithographic masks.
摘要翻译：本发明涉及一种方法，用于在半导体基板制造结型场效应晶体管，worin在说PMD层上沉积预金属电介质层和制造接触开口的步骤先于植入的阱与第一类型的掺杂剂的步骤和第二类型和worin PMD层的厚度，做了一个信道是通过PMD层注入掺杂剂在已配置。本发明的方法允许生产到使用光刻掩膜有限数量内插基板的JFET。

5. 发明公开

EP3127154A1 MONOLITHIC ALLY INTEGRATED TRANSISTORS FOR A BUCK CONVERTER 审中-公开
标题翻译：单相整流晶体振荡器EINENABWÄRTSWANDLER
公开(公告)号：EP3127154A1
公开(公告)日：2017-02-08
申请号：EP15742923.4
申请日：2015-01-30
申请人： Texas Instruments Incorporated , Texas Instruments Japan Limited
发明人： WANG, Jun , BAIOCCHI, Frank , LIN, Haian
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/088 , H01L21/26533 , H01L21/761 , H01L21/823493 , H01L27/1207 , H01L29/0649 , H01L29/1045 , H01L29/1087 , H01L29/402 , H01L29/4175 , H01L29/7816 , H01L29/7835 , H02M3/1588 , Y02B70/1466
摘要： An integrated semiconductor transistor chip for use in a buck converter includes a high side transistor formed on the chip and comprising a laterally diffused metal oxide semiconductor (LDMOS) transistor and a low side transistor formed on the chip and comprising a source down metal oxide semiconductor field effect transistor (MOSFET). The chip also includes a substrate of the chip for use as a source for the low side transistor and an n-doped well for isolation of the high side transistor from the source of the low side transistor.
摘要翻译：用于降压转换器的集成半导体晶体管芯片包括形成在芯片上并包括横向扩散的金属氧化物半导体（LDMOS）晶体管的高侧晶体管和形成在芯片上的低侧晶体管，并且包括源极下行金属氧化物半导体场效应晶体管（MOSFET）。该芯片还包括用作低侧晶体管的源极的芯片的衬底和用于从低侧晶体管的源极隔离高侧晶体管的n掺杂阱。

6. 发明公开

EP3010042A4 SEMICONDUCTOR DEVICE 有权
标题翻译： HALBLEITERBAUELEMENT
公开(公告)号：EP3010042A4
公开(公告)日：2017-01-18
申请号：EP14811117
申请日：2014-06-06
申请人： FUJI ELECTRIC CO LTD
发明人： YAMAJI MASAHARU
IPC分类号： H01L27/08 , H01L21/336 , H01L21/764 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L27/07 , H01L27/12 , H01L29/06 , H01L29/739 , H01L29/78 , H01L29/861 , H01L29/868
CPC分类号： H01L29/7818 , H01L21/761 , H01L21/764 , H01L27/0629 , H01L27/0727 , H01L27/1207 , H01L29/0619 , H01L29/0649 , H01L29/1095 , H01L29/7393 , H01L29/78 , H01L29/8611 , H03K17/002
摘要： In a semiconductor device (100) including a bootstrap diode (Db) and a high voltage electric field transistor (62) on a p-type semiconductor substrate (1), a cavity (3) is formed in an n - -type buried layer (50) of the semiconductor substrate (1) to use the buried layer (50) beneath the cavity as a drain drift region of the high voltage n-channel MOSFET (62), whereby a leakage current by holes (92) that flows to the semiconductor substrate (1) side in forward biasing of the bootstrap diode (Db) can be suppressed, and charging current for a bootstrap capacitor C1 can be increased, as well as increase in chip area can be suppressed.
摘要翻译：在p型半导体衬底（1）上包括自举二极管（Db）和高电压电场晶体管（62）的半导体器件（100）中，在n型掩埋层（50）的半导体衬底（1）的半导体衬底（50），以使用所述腔下面的掩埋层（50）作为所述高电压n沟道MOSFET（62）的漏极漂移区域，由此漏电流（92）流到可以抑制自举二极管（Db）的正向偏置的半导体衬底（1）侧，并且可以增加自举电容器C1的充电电流，并且可以抑制芯片面积的增加。

7. 发明授权

EP2243158B1 A process for forming an isolation structure 有权
标题翻译：用于隔离结构的制造方法
公开(公告)号：EP2243158B1
公开(公告)日：2016-10-19
申请号：EP09711355.9
申请日：2009-02-17
申请人： Advanced Analogic Technologies, Inc.
发明人： DISNEY, Donald, R. , WILLIAMS, Richard, K.
IPC分类号： H01L21/762 , H01L21/761
CPC分类号： H01L21/761 , H01L21/76243 , H01L21/76267 , H01L21/763 , H01L21/8222 , H01L21/82285 , H01L21/823878 , H01L21/823892 , H01L27/0825 , H01L27/0826 , H01L29/41708 , H01L29/732

8. 发明公开

EP3043387A1 INSULATED GATE BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREFOR 有权转让
标题翻译：绝缘栅双极型晶体管及其制造方法
公开(公告)号：EP3043387A1
公开(公告)日：2016-07-13
申请号：EP14840868.5
申请日：2014-08-25
申请人： CSMC Technologies Fab1 Co., Ltd.
发明人： ZHONG, Shengrong , ZHOU, Dongfei , DENG, Xiaoshe , WANG, Genyi
IPC分类号： H01L29/739 , H01L21/331
CPC分类号： H01L29/0623 , H01L21/761 , H01L29/045 , H01L29/0619 , H01L29/1095 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/20 , H01L29/66333 , H01L29/6634 , H01L29/7395 , H01L29/7396
摘要： An insulated gate bipolar transistor (100) is provided. A substrate (10) of the insulated gate bipolar transistor (100) is of an N type. A P-type region (16) is disposed on a back of the N-type substrate. A back metal structure (18) is disposed on a back of the P-type region (16). A terminal protection ring is disposed in a terminal structure. A polysilicon gate (31) is disposed on a front surface of the substrate (10) in an active region. Sidewalls (72) are disposed at two sides of the polysilicon gate (31) on the substrate (10). An interlayer medium (81) covered with the polysilicon gate (31) and the sidewalls (72) are disposed on the substrate (10). The interlayer medium (81) is covered with a metal lead wire layer (91). An N-type carrier enhancement region (41) is disposed in the substrate (10) in the active region. A P-type body region (51) is disposed in the carrier enhancement region (41). An N-type heavily doped region (61) is disposed in the P-type body region (51). A P-type heavily doped region (71) is disposed in the N-type heavily doped region (61). An inward recessed shallow pit (62) with a depth of 0.15 to 0.3 micrometers is formed on a surface of the P-type heavily doped region (71). By disposing the carrier enhancement region (41), the carrier concentration of a channel can be increased and a forward voltage drop can be reduced; in addition, the shallow pit (62) can make a device obtain good impurity distribution and a large metal contact area, thereby improving the performance of the device.
摘要翻译：提供绝缘栅双极晶体管（100）。绝缘栅双极型晶体管（100）的衬底（10）是N型的。 P型区域（16）设置在N型衬底的背面。背面金属结构（18）设置在P型区域（16）的背面。终端保护环设置在终端结构中。多晶硅栅极（31）设置在衬底（10）的有源区中的前表面上。侧壁（72）设置在衬底（10）上的多晶硅栅极（31）的两侧。在衬底（10）上设置覆盖有多晶硅栅极（31）和侧壁（72）的层间介质（81）。层间介质（81）被金属引线层（91）覆盖。 N型载流子增强区（41）设置在有源区中的衬底（10）中。载波增强区（41）中设置有P型体区（51）。 N型重掺杂区（61）设置在P型体区（51）中。 P型重掺杂区（71）设置在N型重掺杂区（61）中。在P型重掺杂区（71）的表面上形成深度为0.15至0.3微米的向内凹陷的浅坑（62）。通过设置载流子增强区域（41），可以增加沟道的载流子浓度，并且可以降低正向压降; 此外，浅槽（62）可以使器件获得良好的杂质分布和大的金属接触面积，从而提高器件的性能。

9. 发明公开

EP3010042A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：EP3010042A1
公开(公告)日：2016-04-20
申请号：EP14811117.2
申请日：2014-06-06
申请人： Fuji Electric Co., Ltd.
发明人： YAMAJI, Masaharu
IPC分类号： H01L27/08 , H01L21/336 , H01L21/764 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/06 , H01L29/78 , H01L29/861 , H01L29/868
CPC分类号： H01L29/7818 , H01L21/761 , H01L21/764 , H01L27/0629 , H01L27/0727 , H01L27/1207 , H01L29/0619 , H01L29/0649 , H01L29/1095 , H01L29/7393 , H01L29/78 , H01L29/8611 , H03K17/002
摘要： In a semiconductor device (100) including a bootstrap diode (Db) and a high voltage electric field transistor (62) on a p-type semiconductor substrate (1), a cavity (3) is formed in an n - -type buried layer (50) of the semiconductor substrate (1) to use the buried layer (50) beneath the cavity as a drain drift region of the high voltage n-channel MOSFET (62), whereby a leakage current by holes (92) that flows to the semiconductor substrate (1) side in forward biasing of the bootstrap diode (Db) can be suppressed, and charging current for a bootstrap capacitor C1 can be increased, as well as increase in chip area can be suppressed.
摘要翻译：在包括p型半导体衬底（1）上的自举二极管（Db）和高压电场晶体管（62）的半导体器件（100）中，空腔（3）形成在n型掩埋层（50），以使用所述空腔下方的所述掩埋层（50）作为所述高电压n沟道MOSFET（62）的漏极漂移区，由此漏电流通过空穴（92）流到所述半导体衬底可以抑制自举二极管（Db）正向偏置时的半导体衬底（1）侧，并且可以增加自举电容器C1的充电电流，并且可以抑制芯片面积的增加。

10. 发明授权

EP2849218B1 Integrated circuit of CMOS type comprising first and second circuit parts 有权
标题翻译： Integrierte Schaltung vom CMOS-Typ mit ersten und zweiten Schaltungsteilen
公开(公告)号：EP2849218B1
公开(公告)日：2016-02-03
申请号：EP13368032.2
申请日：2013-09-16
申请人： ST-Ericsson SA
发明人： Talayssat, Jacques
IPC分类号： H01L21/8238 , H01L21/761 , H01L27/092 , H01L27/108 , H01L27/11 , G11C8/10 , G11C11/419
CPC分类号： G11C11/419 , G11C8/10 , H01L21/761 , H01L21/823892 , H01L27/0928 , H01L27/10894 , H01L27/10897 , H01L27/1104
摘要： An integrated circuit (100) of CMOS type comprises first (10) and second (20) circuit parts arranged close to one another in a single semiconducting substrate. The circuit combines using a deep doping well (2) for reducing digital noise and implementing a sleep mode for reducing power consumption. Such circuit may contain a random access memory and be a radio communication system-on-chip device. It may advantageously be used within a mobile communication apparatus such as a mobile phone.
摘要翻译： CMOS型集成电路（100）包括在单个半导体衬底中彼此靠近布置的第一（10）和第二（20）电路部分。该电路结合使用深掺杂阱（2），以减少数字噪声并实现睡眠模式以降低功耗。这种电路可以包含随机存取存储器，并且是无线电通信片上系统装置。它可以有利地用于诸如移动电话的移动通信装置中。

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