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1. 发明申请

WO2017160468A1 SYSTEMS AND METHODS FOR ELOECTROMAGNETIC INTERFERENCE SHIELDING 审中-公开
标题翻译：用于电磁干扰屏蔽的系统和方法
公开(公告)号：WO2017160468A1
公开(公告)日：2017-09-21
申请号：PCT/US2017/018408
申请日：2017-02-17
申请人： INTEL CORPORATION
发明人： DIAS, Rajendra C. , PRAKASH, Anna M. , HEPPNER, Joshua D. , LI, Eric J. , RARAVIKAR, Nachiket R.
IPC分类号： H01L23/552 , H01L23/60 , H01L25/065 , H01L23/538
摘要： Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.
摘要翻译：这里通常讨论的是包括或提供电磁干扰（EMI）屏蔽的方法和设备。器件可以包括其中包括电连接电路的衬底，在衬底上或至少部分在衬底中的接地电路，至少部分地从衬底的表面暴露的接地电路，电连接到连接电路和接地电路的管芯，衬底上的管芯以及围绕管芯的导电箔或导电膜，导电箔或导电膜电连接到接地电路。

2. 发明申请

WO2017172200A1 HELICALLY INSULATED TWINAX CABLE SYSTEMS AND METHODS 审中-公开
标题翻译：螺旋形绝缘TWINAX电缆系统和方法
公开(公告)号：WO2017172200A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/020126
申请日：2017-03-01
申请人： INTEL CORPORATION
发明人： ZHANG, Zhichao , OUYANG, Gong , XIAO, Kai , LI, Eric J. , AYGUN, Kemal
IPC分类号： H01B9/00 , H01B3/30 , H01B7/00 , H01B13/06
CPC分类号： H01B7/0241 , H01B11/1856 , H01B11/20 , H01B13/08 , H01B13/22 , H05K9/0098
摘要： A helically wound insulated twinax cable improves performance by reducing cable dielectric loss while reducing manufacturing cost and complexity. The helical winding reduces the dielectric loss by increasing the percentage of air in the dielectric filler surrounding the signal conductors. The helical insulator wire winding further provides mechanical support and reduces the risk of creating an electrical short-circuit. This will improve differential signaling capability of the two-conductor cable, improve the overall channel margin performance, relieve the electrical loss budgets for other channel components, and enable longer cable range.
摘要翻译：一种螺旋缠绕绝缘双轴电缆通过减少电缆介质损耗，同时降低制造成本和复杂性来提高性能。螺旋绕组通过增加信号导体周围的介电填充物中的空气百分比来降低介电损耗。螺旋形绝缘线绕组进一步提供机械支撑并降低产生电短路的风险。这将改善双导线电缆的差分信号传输能力，改善整体信道裕度性能，减轻其他信道组件的电损耗预算，并延长电缆的使用范围。

3. 发明申请

WO2017160435A1 MODULAR SQUEEGEE HEAD APPARATUS FOR PRINTING MATERIALS 审中-公开
标题翻译：用于印刷材料的模块化头部装置
公开(公告)号：WO2017160435A1
公开(公告)日：2017-09-21
申请号：PCT/US2017/017519
申请日：2017-02-10
申请人： INTEL CORPORATION
发明人： HEPPNER, Joshua D. , LIFF, Shawna M. , LI, Eric J. , PRAKASH, Anna M.
IPC分类号： B41J25/00 , B41J27/00
CPC分类号： B41F15/18 , B41F15/12 , B41F15/44 , B41L13/02 , B41L13/12 , B41L13/14 , H05K3/1233
摘要： Described is an apparatus which comprises: a squeegee head which is operable to drop a material; and a vacuum manifold attachable to the squeegee head, wherein the vacuum manifold is operable to create a vacuum in a space prior to the squeegee head is to drop the material.
摘要翻译：描述了一种设备，其包括：刮刀头，其可操作以落下材料; 以及可连接到刮刀头的真空歧管，其中真空歧管可操作以在刮刀头掉落材料之前在空间中产生真空。

4. 发明申请

WO2017172135A1 VARIABLE BALL HEIGHT ON BALL GRID ARRAY PACKAGES BY SOLDER PASTE TRANSFER 审中-公开
标题翻译：球栅阵列上的可变球高度通过焊锡膏转移
公开(公告)号：WO2017172135A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/019129
申请日：2017-02-23
申请人： INTEL CORPORATION
发明人： LI, Eric J. , YAO, Jimin , LIFF, Shawna M.
IPC分类号： H01L23/498 , H01L23/495 , H01L23/00 , H01L21/48
摘要： BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold.
摘要翻译：具有空间变化的球高度的BGA封装，用于形成这种封装的模具和技术。具有空腔的模板或模具可以被预制造以保持施加到模具的焊膏材料，例如通过焊膏印刷工艺。空腔的深度和/或直径可以根据模具工作表面区域内的空间位置预先确定。模腔尺寸可以对应于封装位置来指定以解决封装中的一个或多个预先存在或预期的空间变化，诸如封装级翘曲测量。可以提供任何数量的不同的球高度。模具可以用于标准化工艺中，不需要在模具每次更换时进行修改。

5. 发明申请

WO2017112252A1 SEMICONDUCTOR PACKAGE WITH TRENCHED MOLDING-BASED ELECTROMAGNETIC INTERFERENCE SHIELDING 审中-公开
标题翻译：半导体封装基于模压成型的电磁干扰屏蔽
公开(公告)号：WO2017112252A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/063318
申请日：2016-11-22
申请人： INTEL CORPORATION
发明人： DIAS, Rajendra C. , LI, Eric J. , HEPPNER, Joshua D.
IPC分类号： H01L23/552 , H01L23/29 , H01L23/31 , H01L23/498 , H01L25/075 , H01L25/11
CPC分类号： H01L23/552 , H01L21/3105 , H01L21/31111 , H01L21/31116 , H01L21/4867 , H01L21/561 , H01L21/565 , H01L21/76877 , H01L21/78 , H01L23/3121 , H01L23/3128 , H01L23/3135 , H01L23/5283 , H01L23/5328 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/92 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L2224/131 , H01L2224/13111 , H01L2224/13147 , H01L2224/16227 , H01L2224/2919 , H01L2224/2929 , H01L2224/29388 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/81207 , H01L2224/92125 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06568 , H01L2924/14 , H01L2924/1461 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/01029 , H01L2924/014 , H01L2924/00014 , H01L2924/00012 , H01L2224/81 , H01L2224/83 , H01L2224/85 , H01L2924/00
摘要： Semiconductor packages with electromagnetic interference (EMI) shielding and a method of manufacture therefor is disclosed. The semiconductor packages may house single electronic component or may be a system in a package (SiP) implementation. The EMI shielding may be provided on top of and along the periphery of the semiconductor package. The EMI shielding on the periphery may be formed of cured conductive ink or cured conductive paste disposed on sidewalls of molding that encapsulates the electronic component(s) provided on the semiconductor package. The vertical portions of the EMI shielding, including EMI shielding on the periphery may be formed by filling conductive ink in trenches formed in-situ with curing the molding. The top portion of the EMI shielding may additionally be cured conductive ink.
摘要翻译：公开了具有电磁干扰（EMI）屏蔽的半导体封装及其制造方法。半导体封装可以容纳单个电子组件或者可以是封装（SiP）实现中的系统。 EMI屏蔽可以设置在半导体封装的顶部并沿着其周边。周边上的EMI屏蔽可以由固化的导电油墨或固化的导电膏形成，固化的导电膏设置在封装设置在半导体封装上的电子组件的模制件的侧壁上。包括外围EMI屏蔽的EMI屏蔽的垂直部分可以通过在原位形成的沟槽中填充导电墨水并固化模制品来形成。 EMI屏蔽的顶部可以另外固化导电油墨。

6. 发明申请

WO2018126258A1 ELECTRONIC PACKAGE ASSEMBLY WITH COMPACT DIE PLACEMENT 审中-公开
公开(公告)号：WO2018126258A1
公开(公告)日：2018-07-05
申请号：PCT/US2018/012028
申请日：2018-01-02
申请人： INTEL CORPORATION
发明人： LI, Eric J. , MEHTA, Vipul V. , RAORANE, Digvijay A.
IPC分类号： H01L21/56 , H01L25/065
摘要： An electronic package assembly is disclosed. A substrate can have an upper surface area. A first active die can have an upper surface area and a bottom surface, the bottom surface operably coupled to the substrate. A second active die can have an upper surface area and a bottom surface, the bottom surface operably coupled to the substrate. A capillary underfill material can at least partially encapsulate the bottom surface of the first active die and the second active die and extend upwardly upon inside side surfaces of the first and second active dies. A combined area of the upper surface area of the first active die and an upper surface area of the second active die is at least about 90% of the upper surface area of the substrate.

7. 发明申请

WO2017112056A1 ELECTROMAGNETIC INTERFERENCE SHIELDING FOR SYSTEM-IN-PACKAGE TECHNOLOGY 审中-公开
标题翻译：系统级封装技术的电磁干扰屏蔽
公开(公告)号：WO2017112056A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/057541
申请日：2016-10-18
申请人： INTEL CORPORATION
发明人： LI, Eric J. , TOMITA, Yoshihiro , RARAVIKAR, Nachiket R. , SANKMAN, Robert L.
IPC分类号： H01L23/552 , H01L23/31 , H01L21/56 , H01L23/00 , H01L25/065
CPC分类号： H01L23/552 , H01L21/31105 , H01L21/6835 , H01L21/78 , H01L23/3128 , H01L23/5386 , H01L24/97 , H01L25/0655 , H01L25/50 , H01L2924/15311 , H01L2924/1815
摘要： Embodiments are generally directed to electromagnetic interference shielding for system-in-package technology. An embodiment of a system-in-package includes a substrate; chips and components attached to the substrate; dielectric molding over the chips and components; and an electromagnetic interference (EMI) shield. The EMI shield formed from a conductive paste, and the EMI shield provides a combined internal EMI shield between chips and components of the system in package and external EMI shield for the system-in-package.
摘要翻译：实施例通常针对系统级封装技术的电磁干扰屏蔽。系统级封装的实施例包括衬底; 芯片和附着在衬底上的组件; 在芯片和组件上进行电介质模制; 和电磁干扰（EMI）屏蔽。由导电膏形成的EMI屏蔽以及EMI屏蔽提供了封装内系统的芯片和组件之间的组合内部EMI屏蔽，以及用于封装内系统的外部EMI屏蔽。

8. 发明申请

WO2018125050A1 STACKED DIE CAVITY PACKAGE 审中-公开
公开(公告)号：WO2018125050A1
公开(公告)日：2018-07-05
申请号：PCT/US2016/068722
申请日：2016-12-27
申请人： INTEL CORPORATION
发明人： MODI, Mitul , SANKMAN, Robert L. , MALLIK, Debendra , MAHAJAN, Ravindranath V. , ALUR, Amruthavalli P. , DENG, Yikang , LI, Eric J.
IPC分类号： H01L25/065 , H01L23/498 , H01L23/31
摘要： An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.

9. 发明申请

WO2017160468A8 SYSTEMS AND METHODS FOR ELECTROMAGNETIC INTERFERENCE SHIELDING 审中-公开
公开(公告)号：WO2017160468A8
公开(公告)日：2017-09-21
申请号：PCT/US2017/018408
申请日：2017-02-17
申请人： INTEL CORPORATION
发明人： DIAS, Rajendra C. , PRAKASH, Anna M. , HEPPNER, Joshua D. , LI, Eric J. , RARAVIKAR, Nachiket R.
IPC分类号： H01L23/552 , H01L23/60 , H01L25/065 , H01L23/538
摘要： Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.

10. 发明申请

WO2017111952A1 ULTRA SMALL MOLDED MODULE INTEGRATED WITH DIE BY MODULE-ON-WAFER ASSEMBLY 审中-公开
标题翻译：超小型模块与模块在晶圆组件模块集成
公开(公告)号：WO2017111952A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/067422
申请日：2015-12-22
申请人： INTEL CORPORATION
发明人： YOSHIHIRO, Tomita , LI, Eric J. , LIFF, Shawna M. , FALCON, Javier A. , HEPPNER, Joshua D.
IPC分类号： H01L25/065 , H01L23/28 , H01L23/48
CPC分类号： H01L21/561 , H01L21/568 , H01L23/48 , H01L24/19 , H01L24/96 , H01L25/065 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/48091 , H01L2224/73204 , H01L2924/00014 , H01L2924/181 , H01L2924/1815 , H01L2924/00012 , H01L2224/45099
摘要： Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.
摘要翻译：本发明的实施例包括用于形成模制模块的模制模块和方法。根据一个实施例，模制模块可以被集成到电气封装中。根据本发明的实施例的电封装可以包括具有在至少一个表面上形成的再分布层的管芯。模制模块可以安装到模具上。根据一个实施例，模制模块可以包括模制层和封装在模制层内的多个部件。来自每个组件的端子可以基本上与模制层的表面共面以便允许端子电耦合到管芯上的再分布层。本发明的另外的实施例可以包括在模具层中形成的一个或多个模具通孔，以在部件周围提供动力输送和/或一个或多个法拉第笼。

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