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1. 发明申请

WO2007050420A2 SEMICONDUCTOR DEVICE WITH REDUCED PACKAGE CROSS-TALK AND LOSS 审中-公开
标题翻译：具有减少包装的半导体器件交叉和损失
公开(公告)号：WO2007050420A2
公开(公告)日：2007-05-03
申请号：PCT/US2006040869
申请日：2006-10-18
申请人： FREESCALE SEMICONDUCTOR INC , CONDIE BRIAN W , MAHALINGAM MALI , SHAH MAHESH K
发明人： CONDIE BRIAN W , MAHALINGAM MALI , SHAH MAHESH K
IPC分类号： H01L23/28
CPC分类号： H01L23/3135 , H01L23/295 , H01L23/4334 , H01L24/48 , H01L2224/05553 , H01L2224/48247 , H01L2224/97 , H01L2924/00014 , H01L2924/01021 , H01L2924/09701 , H01L2924/10161 , H01L2924/14 , H01L2924/181 , H01L2924/3025 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Structure and method are provided for plastic encapsulated semiconductor devices having reduced package cross-talk and loss. Semiconductor die (42) are first coated with a buffer region (51) having a lower dielectric constant and/or lower loss tangent than the plastic encapsulation. The encapsulation (47) surrounds the buffer region providing a solid structure. The lower buffer region reduces the stray capacitance and therefore the cross-talk between electrodes on or coupled to the die. The lower buffer region reduces the parasitic loss in the encapsulation. Low and/or buffer regions can be achieved using low density organic and/or inorganic materials. Another way is to disperse hollow microspheres or other fillers (52) in the buffer region. An optional sealing layer formed between the buffer region and the encapsulation can mitigate any buffer layer porosity. The buffer region desirably has less than about 3.0 and/or less than about 0.005.
摘要翻译：提供了具有降低的封装串扰和损耗的塑料封装半导体器件的结构和方法。半导体管芯（42）首先被涂覆有比塑料封装具有更低介电常数和/或更低损耗角正切的缓冲区（51）。封装（47）围绕提供固体结构的缓冲区域。下部缓冲区域减小了杂散电容，并因此降低了在电极上或耦合到管芯上的电极之间的串扰。较低的缓冲区减少了封装中的寄生损耗。可以使用低密度有机和/或无机材料实现低和/或缓冲区。另一种方法是将中空微球或其它填料（52）分散在缓冲区中。形成在缓冲区和封装之间的可选密封层可以缓解任何缓冲层的孔隙度。缓冲区理想地具有小于约3.0和/或小于约0.005。

2. 发明申请

WO2007050421A3 SEMICONDUCTOR DEVICE WITH IMPROVED ENCAPSULATION 审中-公开
标题翻译：具有改进封装的半导体器件
公开(公告)号：WO2007050421A3
公开(公告)日：2007-08-02
申请号：PCT/US2006040870
申请日：2006-10-18
申请人： FREESCALE SEMICONDUCTOR INC , CONDIE BRIAN W , SHAH MAHESH K
发明人： CONDIE BRIAN W , SHAH MAHESH K
IPC分类号： H01L23/29
CPC分类号： H01L23/295 , H01L23/4334 , H01L24/48 , H01L2224/48247 , H01L2924/00014 , H01L2924/01021 , H01L2924/09701 , H01L2924/14 , H01L2924/181 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Structure and method are provided for plastic encapsulated semiconductor devices. The encapsulation (47) comprises a plastic binder having a dielectric constant e b and loss tangent db and a filler (52) mixed therewith having lower e f and/or df so that e m and/or d m of the mix is less than e b , d b , respectively. Hollow microspheres of varied sizes are preferred fillers, desirably in the size range of about 0.3 to 300 micrometers. These should comprise at least about 50%, more preferably 60 to 70% or more of the mixture by volume so that the resulting mix has e m m
摘要翻译：为塑料封装半导体器件提供了结构和方法。封装（47）包括具有介电常数εb和损耗正切db的塑料粘合剂和与其混合的填料（52）具有较低的e和/或df 混合物的e m和/或d m m分别小于e b b和b b。不同尺寸的中空微球体是优选的填料，理想地在约0.3至300微米的尺寸范围内。这些应该包含至少约50％，更优选60至70％或更多的体积混合物，使得所得混合物具有ε3，优选<2.5和D < / SUB> <0.005。将密封剂混合物放置在模具附近或模具上，使得模具，模具布线和/或模具连接的边缘电场暴露于不具有填料的塑料封装的较低的e和/或d。

3. 发明申请

WO2007050422A3 PLASTIC PACKAGED DEVICE WITH DIE INTERFACE LAYER 审中-公开
标题翻译：具有DIE接口层的塑料包装设备
公开(公告)号：WO2007050422A3
公开(公告)日：2009-05-14
申请号：PCT/US2006040871
申请日：2006-10-18
申请人： FREESCALE SEMICONDUCTOR INC , CONDIE BRIAN W , SHAH MAHESH K
发明人： CONDIE BRIAN W , SHAH MAHESH K
IPC分类号： H01L21/48 , H01L21/50 , H01L23/28 , H01L23/29
CPC分类号： H01L23/3192 , H01L23/3164 , H01L23/3171 , H01L23/4334 , H01L24/97 , H01L2224/48091 , H01L2924/01004 , H01L2924/01005 , H01L2924/01021 , H01L2924/01033 , H01L2924/01057 , H01L2924/01074 , H01L2924/01082 , H01L2924/09701 , H01L2924/14 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： Structure and method are provided for plastic encapsulated semiconductor devices having a buffer layer of low dielectric constant and/or low loss tangent material separating the die surface from the plastic encapsulation. Semiconductor wafers with substantially completed SC die (42) are coated with the buffer layer (52). The buffer layer is patterned to expose the die bonding pads (44) but leave the buffer layer over some or all of the other die metallization. The die are then separated, mounted on a lead-frame or other support, wire bonded or otherwise coupled to external leads, and encapsulated. The plastic encapsulation (47) surrounds the die and the buffer layer, providing a solid structure. The buffer layer reduces the parasitic capacitance, cross-talk and loss between metallization regions on the die. An optional sealing layer may also be provided at the wafer stage between the buffer layer and the plastic encapsulation to mitigate any buffer layer porosity.
摘要翻译：提供了具有低介电常数和/或低损耗正切材料的缓冲层的塑料封装的半导体器件的结构和方法，其将管芯表面与塑料封装分开。具有基本上完成的SC管芯（42）的半导体晶片被缓冲层（52）涂覆。对缓冲层进行图案化以使裸片接合焊盘（44）露出，但是将缓冲层留在其它管芯金属化部分或全部上。然后将管芯分离，安装在引线框架或其他支撑件上，引线键合或以其他方式耦合到外部引线，并封装。塑料封装（47）围绕裸片和缓冲层，提供坚实的结构。缓冲层减少了裸片上的金属化区域之间的寄生电容，串扰和损耗。也可以在缓冲层和塑料封装之间的晶片台处提供可选的密封层，以减轻任何缓冲层孔隙率。

4. 发明申请

WO2007001854A3 CHEMICAL DIE SINGULATION TECHNIQUE 审中-公开
标题翻译：化学成型技术
公开(公告)号：WO2007001854A3
公开(公告)日：2007-12-06
申请号：PCT/US2006023120
申请日：2006-06-13
申请人： FREESCALE SEMICONDUCTOR INC , CONDIE BRIAN W , DOUGHERTY DAVID J , SHAH MAHESH K
发明人： CONDIE BRIAN W , DOUGHERTY DAVID J , SHAH MAHESH K
IPC分类号： H01L21/00
CPC分类号： H01L21/78
摘要： A method is provided for manufacturing a semiconductor device from a substrate (200) having an active surface (204) and a non-active surface (206). The method comprises depositing a backing material (104) onto the non-active surface of the substrate (206) in a pattern (500), the pattern (500) having at least a first die section (210), a second die section (212) adjacent the first die section (210), and a strip (216) connecting the first die section (210) and the second die section (212), removing material from portions of the non-active surface of the substrate (206) on which the backing material (104) is not deposited to thereby partially separate the substrate (200) into a first die (236) and a second die (238) connected to one another by the strip (254) of the deposited backing material, and breaking the strip connector (254) to separate the first die (236) from the second die (238).
摘要翻译：提供了一种从具有有源表面（204）和非有效表面（206）的衬底（200）制造半导体器件的方法。该方法包括以图案（500）将背衬材料（104）沉积到基底（206）的非活性表面上，图案（500）具有至少第一模具部分（210），第二模具部分 212），以及连接第一模具部分（210）和第二模具部分（212）的条带（216），从衬底（206）的非活性表面的部分去除材料，其上不沉积背衬材料（104），从而通过沉积的背衬材料的带（254）将衬底（200）部分地分离成第一模具（236）和第二模具（238），所述第一模具（238）彼此连接，以及断开带状连接器（254）以将第一管芯（236）与第二管芯（238）分离。

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