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1. 发明申请

WO2014089814A1 一种半导体器件及其制备方法审中-公开
公开(公告)号：WO2014089814A1
公开(公告)日：2014-06-19
申请号：PCT/CN2012/086614
申请日：2012-12-14
申请人：复旦大学
发明人：吴东平 , 皮朝阳 , 赵娜 , 张卫 , 张世理
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/486 , H01L21/76843 , H01L21/76855 , H01L21/76883 , H01L21/76889 , H01L23/485 , H01L23/53271 , H01L29/458 , H01L2924/0002 , H01L2924/00
摘要：一种半导体器件及其制备方法，在晶体管的源极（302）和漏极（303）上形成金属半导体化合物接触区（304），同时在绝缘介质层（306）中的对应于源极和漏极位置的通孔（307）内，形成金属半导体化合物（312），将源极和漏极引出。由于通孔内的填充材料与源极和漏极接触区的材料都为金属半导体化合物，可以使通孔内的填充材料与源极和漏极接触区之间的接触电阻较小；可以使得通孔内的物质本身的电阻较小；可以使通孔内的导电材料与绝缘介质层之间具有良好的界面和粘附性，既不破坏介质层材料的结构、又不需要在通孔内的填充材料和绝缘介质层间形成阻挡层。

2. 发明申请

WO2008107419A1 FORMATION OF A RELIABLE DIFFUSION-BARRIER CAP ON A CU-CONTAINING INTERCONNECT ELEMENT HAVING GRAINS WITH DIFFERENT CRYSTAL ORIENTATIONS 审中-公开
标题翻译：在具有不同晶体取向的颗粒的含CU连接元件上形成可靠的扩散阻挡层
公开(公告)号：WO2008107419A1
公开(公告)日：2008-09-12
申请号：PCT/EP2008/052565
申请日：2008-03-03
申请人： NXP B.V. , ST MICROELECTRONICS (CROLLES 2) SAS , TORRES, Joaquin , GOSSET, Laurent , CHHUN, Sonarith , ARNAL, Vincent
发明人： TORRES, Joaquin , GOSSET, Laurent , CHHUN, Sonarith , ARNAL, Vincent
IPC分类号： H01L21/768 , H01L21/321
CPC分类号： H01L21/76849 , H01L21/76834 , H01L21/76867 , H01L21/76889
摘要： The present invention relates to a method for fabricating a diffusion-barrier cap on a Cu-containing interconnect element that has crystallites of at least two different crystalorientations, comprisesselectively incorporating Si into only a first set of crystallites withat least one first crystalorientation, employing first process conditions, and subsequently selectively forming a first adhesion-layer portion comprising CuSi and a first diffusion-barrier-layer portion only on the first set of crystallites, thus forming a first barrier- cap portion, and subsequently selectively incorporating Si into only the second set of crystallites, employing second process conditions that differ from the first process conditions, and forming a second barrier-cap portion comprising a Si-containing second diffusion-barrier layer portion on the second set of crystallites of the interconnect element. The processing improves the properties of the diffusion-barrier cap and secures a continuous formation of a diffusion-barrier layer on the interconnect element.
摘要翻译：本发明涉及一种在含Cu互连元件上制造扩散阻挡帽的方法，该方法具有至少两种不同晶体取向的晶体，其包括仅将第一组晶体中的Si并入至少一种第一晶体取向中，条件，并且随后选择性地形成包含CuSi和第一扩散阻挡层部分的第一粘附层部分，仅在第一组微晶上形成第一屏蔽帽部分，随后选择性地将Si并入仅第二组的微晶，使用与第一工艺条件不同的第二工艺条件，以及在互连元件的第二组微晶上形成包含含Si的第二扩散阻挡层部分的第二阻挡帽部分。该处理改善了扩散阻挡帽的性质，并确保了互连元件上的扩散阻挡层的连续形成。

3. 发明申请

WO2003103046A1 BURIED DIGIT LINE STACK AND PROCESS FOR MAKING SAME 审中-公开
标题翻译： BURIED数字线路堆栈和制造过程
公开(公告)号：WO2003103046A1
公开(公告)日：2003-12-11
申请号：PCT/US2003/017579
申请日：2003-06-04
申请人： MICRON TECHNOLOGY, INC.
发明人： HU, Y., Jeff
IPC分类号： H01L23/532
CPC分类号： H01L23/53266 , H01L21/2855 , H01L21/32051 , H01L21/32053 , H01L21/76849 , H01L21/7685 , H01L21/76855 , H01L21/76867 , H01L21/76889 , H01L27/10885 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： A process of making a buried digit line stack is disclosed. The process includes forming a silicon-lean metal silicide first film (226) over a polysilicon plug (224), followed by a silicide compound barrier second film (228). The silicide compound barrier second film is covered with a refractory metal third film (232). A salicidation process causes the first film to salicide (236) with the polysilicon plug. In one embodiment, all the aforementioned deposition processes are carried out by physical vapor deposition ("PVD").
摘要翻译：公开了一种制作掩埋式数字线叠层的工艺。该方法包括在多晶硅插塞（224）上形成贫硅金属硅化物第一膜（226），然后形成硅化合物屏障第二膜（228）。硅化物阻挡层第二膜被难熔金属第三膜（232）覆盖。水解过程使得第一膜与多晶硅插塞自杀（236）。在一个实施方案中，所有上述沉积工艺都是通过物理气相沉积（“PVD”）进行的。

4. 发明申请

WO1995024731A1 MASKING METHOD USED IN SALICIDE PROCESS 审中-公开
标题翻译：在浸渍过程中使用的掩蔽方法
公开(公告)号：WO1995024731A1
公开(公告)日：1995-09-14
申请号：PCT/US1995000798
申请日：1995-01-20
申请人： NATIONAL SEMICONDUCTOR CORPORATION
发明人： NATIONAL SEMICONDUCTOR CORPORATION , GRUBISICH, Michael , BLAIR, Christopher, S.
IPC分类号： H01L21/768
CPC分类号： H01L21/768 , H01L21/76889
摘要： A mask opening (52) used to etch exposed oxide spacer portions (37, 40) is made to not expose any parasitic oxide spacers (44) formed along an edge of the isolated silicon island (12). The desired oxide spacers (38, 39) will thus be intact to properly isolate silicide portions formed over exposed silicon and polysilicon surfaces. This process may be used during the formation of a bipolar or MOS transistor formed in an isolated silicon island (12).
摘要翻译：用于蚀刻暴露的氧化物间隔物部分（37,40）的掩模开口（52）不会暴露沿隔离的硅岛（12）的边缘形成的任何寄生氧化物间隔物（44）。因此，期望的氧化物间隔物（38,39）将是完整的，以适当地隔离在暴露的硅和多晶硅表面上形成的硅化物部分。在形成在隔离硅岛（12）中形成的双极或MOS晶体管时，可以使用该工艺。

5. 发明申请

WO1991006120A1 SELF-ALIGNING METAL INTERCONNECT FABRICATION 审中-公开
标题翻译：自对准金属互连制造
公开(公告)号：WO1991006120A1
公开(公告)日：1991-05-02
申请号：PCT/EP1990001717
申请日：1990-10-08
申请人： VLSI TECHNOLOGY INC
发明人： VLSI TECHNOLOGY INC , TSOU, Morris, Hsimeng
IPC分类号： H01L21/90
CPC分类号： H01L21/31683 , H01L21/28525 , H01L21/76889
摘要： In a method for fabricating a semiconductor device such as a MOS device, a nitride cap (204) is formed over a remote interconnect (104) of gate material. In a subsequent oxide growth step, oxide (140) is formed over another remote interconnect (106) and transistor gates, while the nitride cap prevents oxide growth over the first remote interconnect. Thinner oxide over source and drain regions is removed, leaving oxide formations over the gates and the second interconnect; the nitride cap is also removed. Silicide (134, 136, 138) is then formed over the source and drain regions and over portions of the first remote interconnect. A conducting layer (132) is deposited and a local interconnect is then patterned therefrom which electrically connects the first remote interconnect to at least one source/drain region without using via holes. This local interconnect crosses over the second remote interconnect, while being insulated from it by the oxide formation. The result of the method is an integrated circuit device with this bridging interconnect and compact dimensions, the latter due to the relaxed tolerances afforded by the self-aligning features of the method.

6. 发明申请

WO2017058279A1 SOURCE-GATE REGION ARCHITECTURE IN A VERTICAL POWER SEMICONDUCTOR DEVICE 审中-公开
标题翻译：垂直功率半导体器件中的源极区域结构
公开(公告)号：WO2017058279A1
公开(公告)日：2017-04-06
申请号：PCT/US2016/015394
申请日：2016-01-28
申请人： D3 SEMICONDUCTOR LLC
发明人： HARRINGTON, Thomas, E.
IPC分类号： H01L21/82 , H01L21/32 , H01L21/70 , H01L21/77 , H01L21/822
CPC分类号： H01L23/535 , H01L21/28518 , H01L21/76805 , H01L21/76843 , H01L21/76889 , H01L21/76895 , H01L23/53266 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/41775 , H01L29/456 , H01L29/4933 , H01L29/66333 , H01L29/66712 , H01L29/7395 , H01L29/7802 , H01L29/7811
摘要： A vertical drift metal-oxide-semiconductor (VDMOS) transistor with improved contact to source and body regions, and a method of fabricating the same. A masked ion implant of the source regions into opposite-type body regions defines the locations of body contact regions, which are implanted subsequently with a blanket implant. The surface of the source regions and body contact regions are silicide clad, and an overlying insulator layer deposited and planarized. Contact openings are formed through the planarized insulator layer, within which conductive plugs are formed to contact the metal silicide, and thus the source and body regions of the device. A metal conductor is formed overall to the desired thickness, and contacts the conductive plugs to provide bias to the source and body regions.
摘要翻译：具有改善与源极和体区的接触的垂直漂移金属氧化物半导体（VDMOS）晶体管及其制造方法。源极区域的掩模离子注入到相对体区域中限定了身体接触区域的位置，其随后用橡皮布植入物植入。源极区域和体接触区域的表面是硅化物包层的，并且上覆的绝缘体层沉积并平坦化。通过平坦化的绝缘体层形成接触开口，其中形成导电插塞以接触金属硅化物，从而与器件的源极和体区接触。金属导体整体形成所需的厚度，并且与导电塞接触以向源区和身体区提供偏压。

7. 发明申请

WO2013190759A1 固体撮像素子及びその製造方法审中-公开
标题翻译：固态成像元件及其制造方法
公开(公告)号：WO2013190759A1
公开(公告)日：2013-12-27
申请号：PCT/JP2013/002750
申请日：2013-04-23
申请人：パナソニック株式会社
发明人：境田　良太 , 高橋　信義 , 佐伯　幸作
IPC分类号： H01L27/146 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/768 , H01L23/522 , H01L23/532 , H01L29/78 , H04N5/357 , H04N5/374
CPC分类号： H01L27/307 , H01L21/28525 , H01L21/76889 , H01L21/76895 , H01L21/76897 , H01L23/485 , H01L27/14612 , H01L27/14643 , H01L51/441 , H01L2924/0002 , H01L2924/00
摘要：　固体撮像素子が備える撮像画素は、基板（１００）に形成された拡散領域である電荷蓄積部（１０２）と、基板上における電荷蓄積部の側方に形成されたゲート電極（１０３）と、電荷蓄積部の上に形成された絶縁膜（３００）と、該絶縁膜を貫通して電荷蓄積部と接続された、半導体からなるコンタクトプラグ（２００）とを有している。コンタクトプラグは、その下部が絶縁膜に埋め込まれ、且つその上部が絶縁膜から露出している。コンタクトプラグの上部の表面には、シリサイド（２１０）が形成されており、電荷蓄積部及びゲート電極には、シリサイドが形成されていない。
摘要翻译：该固态成像元件的成像像素包括：形成在基板（100）中的扩散区域的电荷存储部（102）。栅极电极，其形成在所述基板的所述电荷存储部的一侧; 绝缘膜（300），其形成在所述电荷存储部上; 以及由半导体形成并穿过绝缘膜以连接到电荷存储部分的接触插塞（200）。接触插塞的下部嵌入在绝缘膜中，而接触插塞的上部从绝缘膜露出。在接触插塞的上部的表面上形成硅化物（210），而在电荷存储部分和栅电极上不形成硅化物。

8. 发明申请

WO2010002718A2 METHOD OF FORMING STACKED TRENCH CONTACTS AND STRUCTURES FORMED THEREBY 审中-公开
标题翻译：形成堆叠的TRENCH联系人及其形成的结构的方法
公开(公告)号：WO2010002718A2
公开(公告)日：2010-01-07
申请号：PCT/US2009048764
申请日：2009-06-26
申请人： INTEL CORP , SELL BERNHARD , GOLONZKA OLEG
发明人： SELL BERNHARD , GOLONZKA OLEG
IPC分类号： H01L21/28
CPC分类号： H01L23/535 , H01L21/28052 , H01L21/28123 , H01L21/76805 , H01L21/76889 , H01L21/76895 , H01L21/76897 , H01L21/823425 , H01L21/823468 , H01L21/823475 , H01L23/485 , H01L23/5226 , H01L23/528 , H01L23/53257 , H01L23/53266 , H01L27/088 , H01L29/0847 , H01L29/4175 , H01L29/4925 , H01L29/66666 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IlD disposed on a top surface of a metal gate disposed on the substrate.
摘要翻译：描述形成微电子器件的方法和相关结构。这些方法可以包括形成包括设置在基板的源极/漏极接触件上的第一接触金属和设置在第一接触金属的顶表面上的第二接触金属的结构，其中第二接触金属设置在设置的IID内在设置在基板上的金属栅极的顶面上。

9. 发明申请

WO2007057796A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED WITH SUCH A METHOD 审中-公开
标题翻译：制造半导体器件的方法和采用这种方法获得的半导体器件
公开(公告)号：WO2007057796A1
公开(公告)日：2007-05-24
申请号：PCT/IB2006/053956
申请日：2006-10-27
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MADAKASIRA, Vijayaraghavan , AGARWAL, Prabhat , DONKERS, Johannes, J., T., M. , VAN DAL, Mark
发明人： MADAKASIRA, Vijayaraghavan , AGARWAL, Prabhat , DONKERS, Johannes, J., T., M. , VAN DAL, Mark
IPC分类号： H01L21/768
CPC分类号： H01L21/76877 , H01L21/28525 , H01L21/76889 , H01L2221/1094
摘要： The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (12) which is provided with at least one semiconductor element (E) and comprising a monocrystalline silicon (1) region on top of which an epitaxial silicon region (2) is formed by providing a metal silicide region (3) on the monocrystalline silicon region (1) and a low-crystallinity silicon region (4) on top of the metal silicide region (3), after which the low-crystallinity silicon region (4) is transformed by heating into the epitaxial silicon region (2) having a high-crystallinity, during which process the metal silicide region (3) is moved from the bottom of the low-crystallinity silicon region (4) to the top of the epitaxial silicon region (2). According to the invention above the level of the metal silicide region (3) an insulating layer (5) is formed which is provided with an opening (6), the low-crystallinity silicon region (4) is deposited in the opening (6) and on top of the insulating layer (5), the part (4A, 4B) of the low-crystallinity silicon region (4) on top of the insulating layer (5) is removed by a planarization process after which the epitaxial silicon region (2) is formed. In this way an epitaxial silicon region (2), preferably a nano wire (2), is simply obtained that is provided with a metal silicide contact (region) in a self-aligned manner and that can form a part of semiconductor element (E) like a transistor.
摘要翻译：本发明涉及一种制造具有衬底（11）和半导体本体（12）的半导体器件（10）的方法，该半导体器件（12）设置有至少一个半导体元件（E）并且包括顶部的单晶硅（1）区域其中通过在单晶硅区域（1）上提供金属硅化物区域（3）和在金属硅化物区域（3）的顶部上的低结晶度硅区域（4）形成外延硅区域（2），之后其中低结晶度硅区域（4）通过加热转变成具有高结晶度的外延硅区域（2），在该过程中，金属硅化物区域（3）从低结晶度硅区域的底部移动（4）到外延硅区域（2）的顶部。根据上述本发明，金属硅化物区域（3）的水平形成有设置有开口（6）的绝缘层（5），低结晶度硅区域（4）沉积在开口（6）中，并且在绝缘层（5）的顶部，通过平坦化工艺除去绝缘层（5）顶部上的低结晶性硅区域（4）的部分（4A，4B），之后将外延硅区域 2）。以这种方式，简单地获得外延硅区域（2），优选纳米线（2），其以自对准方式设置有金属硅化物接触（区域），并且可以形成半导体元件（E ）像晶体管。

10. 发明申请

WO2006102318A2 ELECTROLESS DEPOSITION PROCESS ON A CONTACT CONTAINING SILICON OR SILICIDE 审中-公开
标题翻译：在含硅或硅的接触处的电沉积工艺
公开(公告)号：WO2006102318A2
公开(公告)日：2006-09-28
申请号：PCT/US2006/010220
申请日：2006-03-20
申请人： APPLIED MATERIALS, INC. , STEWART, Michael P. , WEIDMAN, Timothy W. , SHANMUGASUNDRAM, Arulkumar , ZHU, Zhize , GANDIKOTA, Srinivas , GELATOS, Avgerinos V. (Jerry) , ROSATO, John J. , EAGLESHAM, David J.
发明人： STEWART, Michael P. , WEIDMAN, Timothy W. , SHANMUGASUNDRAM, Arulkumar , ZHU, Zhize , GANDIKOTA, Srinivas , GELATOS, Avgerinos V. (Jerry) , ROSATO, John J. , EAGLESHAM, David J.
IPC分类号： B28B19/00 , C23C18/34
CPC分类号： C23C18/1893 , B82Y30/00 , C23C18/1651 , C23C18/32 , C23C18/34 , H01L21/02063 , H01L21/28518 , H01L21/288 , H01L21/76802 , H01L21/76814 , H01L21/76843 , H01L21/76847 , H01L21/76855 , H01L21/76856 , H01L21/76867 , H01L21/76874 , H01L21/76879 , H01L21/76889
摘要： Embodiments as described herein provide methods for depositing a material on a substrate during electroless deposition processes, as well as compositions of the electroless deposition solutions. In one embodiment, the substrate contains a contact aperture having an exposed silicon contact surface. In another embodiment, the substrate contains a contact aperture having an exposed silicide contact surface. The apertures are filled with a metal contact material by exposing the substrate to an electroless deposition process. The metal contact material may contain a cobalt material, a nickel material, or alloys thereof. Prior to filling the apertures, the substrate may be exposed to a variety of pretreatment processes, such as preclean processes and activations processes. A preclean process may remove organic residues, native oxides, and other contaminants during a wet clean process or a plasma etch process. Embodiments of the process also provide the deposition of additional layers, such as a capping layer.
摘要翻译：本文所述的实施方案提供了在无电沉积工艺期间在基材上沉积材料的方法，以及无电沉积溶液的组成。在一个实施例中，衬底包含具有暴露的硅接触表面的接触孔。在另一个实施例中，衬底包含具有暴露的硅化物接触表面的接触孔。通过将基板暴露于无电镀沉积工艺，孔通过金属接触材料填充。金属接触材料可以包含钴材料，镍材料或其合金。在填充孔之前，基底可以暴露于各种预处理过程，例如预清洗过程和激活过程。在湿式清洁过程或等离子体蚀刻过程中，预清洗方法可以去除有机残留物，天然氧化物和其它污染物。该方法的实施方案还提供附加层的沉积，例如覆盖层。

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