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1. 发明申请

WO2007057796A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED WITH SUCH A METHOD 审中-公开
标题翻译：制造半导体器件的方法和采用这种方法获得的半导体器件
公开(公告)号：WO2007057796A1
公开(公告)日：2007-05-24
申请号：PCT/IB2006/053956
申请日：2006-10-27
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MADAKASIRA, Vijayaraghavan , AGARWAL, Prabhat , DONKERS, Johannes, J., T., M. , VAN DAL, Mark
发明人： MADAKASIRA, Vijayaraghavan , AGARWAL, Prabhat , DONKERS, Johannes, J., T., M. , VAN DAL, Mark
IPC分类号： H01L21/768
CPC分类号： H01L21/76877 , H01L21/28525 , H01L21/76889 , H01L2221/1094
摘要： The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (12) which is provided with at least one semiconductor element (E) and comprising a monocrystalline silicon (1) region on top of which an epitaxial silicon region (2) is formed by providing a metal silicide region (3) on the monocrystalline silicon region (1) and a low-crystallinity silicon region (4) on top of the metal silicide region (3), after which the low-crystallinity silicon region (4) is transformed by heating into the epitaxial silicon region (2) having a high-crystallinity, during which process the metal silicide region (3) is moved from the bottom of the low-crystallinity silicon region (4) to the top of the epitaxial silicon region (2). According to the invention above the level of the metal silicide region (3) an insulating layer (5) is formed which is provided with an opening (6), the low-crystallinity silicon region (4) is deposited in the opening (6) and on top of the insulating layer (5), the part (4A, 4B) of the low-crystallinity silicon region (4) on top of the insulating layer (5) is removed by a planarization process after which the epitaxial silicon region (2) is formed. In this way an epitaxial silicon region (2), preferably a nano wire (2), is simply obtained that is provided with a metal silicide contact (region) in a self-aligned manner and that can form a part of semiconductor element (E) like a transistor.
摘要翻译：本发明涉及一种制造具有衬底（11）和半导体本体（12）的半导体器件（10）的方法，该半导体器件（12）设置有至少一个半导体元件（E）并且包括顶部的单晶硅（1）区域其中通过在单晶硅区域（1）上提供金属硅化物区域（3）和在金属硅化物区域（3）的顶部上的低结晶度硅区域（4）形成外延硅区域（2），之后其中低结晶度硅区域（4）通过加热转变成具有高结晶度的外延硅区域（2），在该过程中，金属硅化物区域（3）从低结晶度硅区域的底部移动（4）到外延硅区域（2）的顶部。根据上述本发明，金属硅化物区域（3）的水平形成有设置有开口（6）的绝缘层（5），低结晶度硅区域（4）沉积在开口（6）中，并且在绝缘层（5）的顶部，通过平坦化工艺除去绝缘层（5）顶部上的低结晶性硅区域（4）的部分（4A，4B），之后将外延硅区域 2）。以这种方式，简单地获得外延硅区域（2），优选纳米线（2），其以自对准方式设置有金属硅化物接触（区域），并且可以形成半导体元件（E ）像晶体管。

2. 发明申请

WO2004095564A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH A BIPOLAR TRANSISTOR 审中-公开
标题翻译：用双极晶体管制造半导体器件的方法
公开(公告)号：WO2004095564A1
公开(公告)日：2004-11-04
申请号：PCT/IB2004/050497
申请日：2004-04-23
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MAGNEE, Petrus, H., C. , HUETING, Raymond, J., E. , MELAI, Joost , IN 'T ZANDT, Michael, A., A. , DONKERS, Johannes, J., T., M.
发明人： MAGNEE, Petrus, H., C. , HUETING, Raymond, J., E. , MELAI, Joost , IN 'T ZANDT, Michael, A., A. , DONKERS, Johannes, J., T., M.
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L21/76895 , H01L29/7378
摘要： Method of manufacturing a semiconductor device with a bipolar transistor, in which method, on a surface (3) of a silicon body comprising a surface layer (2) of a first conductivity type lying on a heavily doped contact layer (6) of the same, first conductivity type, a first layer of semiconductor material (8) is formed in which layer the base (21) is to be formed. In this method, a mask (9) is formed on the first layer of semiconductor material at the location of the base to be formed, after which non-covered parts of the first layer of semiconductor material are successively etched away and replaced by a layer of doped amorphous or polycrystalline silicon. Next, the mask is removed, whereby a window (17) is formed at the location of the base in which a second layer of semiconductor material (19) of the first conductivity type is deposited for forming the emitter (20) of the transistor. Thus a transistor is formed, the base of which is contacted by a highly conductive base contact (15) formed in the layer of doped amorphous or polycrystalline silicon.
摘要翻译：制造具有双极性晶体管的半导体器件的方法，在该方法中，在硅体的表面（3）上，该硅体包括位于其上的重掺杂接触层（6）上的第一导电类型的表面层（2），第一导电型，形成第一半导体材料层（8），其中将形成基底（21）。在该方法中，在要形成的基底的位置处，在第一半导体材料层上形成掩模（9），之后将第一半导体材料层的未覆盖部分相继蚀刻掉，并由层的掺杂非晶或多晶硅。接下来，去除掩模，由此在基底的位置处形成窗口（17），在该位置沉积第一导电类型的第二半导体材料层（19）以形成晶体管的发射极（20）。因此，形成晶体管，其基极由形成在掺杂的非晶或多晶硅层中的高导电性基极接触（15）接触。

3. 发明申请

WO2006077502A1 BIPOLAR TRANSISTOR AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：双极晶体管及其制造方法
公开(公告)号：WO2006077502A1
公开(公告)日：2006-07-27
申请号：PCT/IB2006/050107
申请日：2006-01-12
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , DONKERS, Johannes, J., T., M. , VAN NOORT, Wibo, D. , MEUNIER-BEILLARD, Philippe , NUTTINCK, Sebastien , HIJZEN, Erwin , NEUILLY, François
发明人： DONKERS, Johannes, J., T., M. , VAN NOORT, Wibo, D. , MEUNIER-BEILLARD, Philippe , NUTTINCK, Sebastien , HIJZEN, Erwin , NEUILLY, François
IPC分类号： H01L21/31 , H01L29/732 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/66272 , H01L29/732 , H01L29/7378
摘要： The invention provides a bipolar transistor with a reduced collector series resistance integrated in a trench (4, 44) of a standard CMOS shallow trench isolation region. The bipolar transistor includes a collector region (6, 34) manufactured in one fabrication step, therefore having a shorter conductive path with a reduced collector series resistance, improving the high frequency performance of the bipolar transistor. The bipolar transistor further includes a base region (8, 22, 38) with a first part on a selected portion of the collector region (6, 34), which is on the bottom of the trench (4, 44), and an emitter region (10, 24, 39) on a selected portion of the first part of the base region (8, 22, 38). A base contact (11, 26, 51) electrically contacts the base region (8, 22, 38) on a second part of the base region (8, 22, 38), which is on an insulating region (2, 42). The collector region (6, 34) is electrically contacted on top of a protrusion (5, 45) with a collector contact (13, 25, 50).
摘要翻译：本发明提供了集成在标准CMOS浅沟槽隔离区的沟槽（4,44）中的集电极串联电阻降低的双极晶体管。双极晶体管包括在一个制造步骤中制造的集电极区域（6,34），因此具有较短的集电极串联电阻的导电路径，从而改善了双极晶体管的高频性能。双极晶体管还包括在沟槽（4,44）的底部上的集电极区域（6,34）的选定部分上的第一部分的基极区域（8,22,38）和发射极区域（10,24,39）在基区（8,22,38）的第一部分的选定部分上。在绝缘区域（2,42）上的基极区域（8,22,38）的第二部分上的基极接触部分（11,26,31）与基极区域（8,22,38）电接触。集电区域（6,34）与突起（5,45）的顶部与集电极接触（13,25,50）电接触。

4. 发明申请

WO2006011107A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED WITH SUCH A METHOD 审中-公开
标题翻译：制造半导体器件的方法和采用这种方法获得的半导体器件
公开(公告)号：WO2006011107A1
公开(公告)日：2006-02-02
申请号：PCT/IB2005/052382
申请日：2005-07-18
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MEUNIER-BEILLARD, Philippe , RAVIT, Claire , DONKERS, Johannes, J., T., M. , MAGNEE, Petrus, H., C, , HIJZEN, Erwin , VERHEIJEN, Marcelino, A. , PONOMAREV, Youri , LOO, Josine, J., G., P.
发明人： MEUNIER-BEILLARD, Philippe , RAVIT, Claire , DONKERS, Johannes, J., T., M. , MAGNEE, Petrus, H., C, , HIJZEN, Erwin , VERHEIJEN, Marcelino, A. , PONOMAREV, Youri , LOO, Josine, J., G., P.
IPC分类号： H01L29/786
CPC分类号： H01L29/78687 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L29/66742 , H01L29/7842 , H01L29/78603
摘要： The invention relates to a method of manufacturing a semiconductor device (10) in which a semiconductor body (11) comprising silicon is provided, at a surface thereof, with a first semiconductor layer (1) having a lattice of a mixed crystal of silicon and germanium, which lattice is substantially relaxed, and on top of the first semiconductor layer (1) a second semiconductor layer (2) is situated comprising strained silicon, in which layer (2) an active part of the semiconductor device (10) is formed, and wherein the first semiconductor layer (1) is formed above a patterned insulating layer (200) which is present in the semiconductor body (11) of silicon. According to the invention the method is characterized in that the insulating layer (200) is provided on top of the semiconductor body (11) and patterned such as to comprise a window (21) bordering a region (20) of the insulating layer, and in that the first semiconductor layer (1) is directly grown on the part of the semiconductor body (11) below the window (21) and the region (20) of the insulating layer is covered with the first semiconductor layer by lateral overgrowth. In this way either a substantially defect-free strain-relaxed layer (1) is obtained or a strain-relaxed layer (1) of which at least the part that, viewed in projection, is above the insulating region (20) is substantially defect-free.
摘要翻译：本发明涉及一种制造半导体器件（10）的方法，其中在其表面上设置包括硅的半导体本体（11），其中第一半导体层（1）具有硅的混晶晶格和锗，其格子基本上松弛，并且在第一半导体层（1）的顶部上，包括应变硅的第二半导体层（2），其中层（2）形成半导体器件（10）的有源部分，并且其中所述第一半导体层（1）形成在存在于所述硅的半导体本体（11）中的图案化绝缘层（200）的上方。根据本发明，所述方法的特征在于，绝缘层（200）设置在半导体本体（11）的顶部并且被图案化以包括与绝缘层的区域（20）接合的窗口（21），以及因为第一半导体层（1）直接在窗口（21）下面的半导体本体（11）的一部分上生长，并且绝缘层的区域（20）被侧向过度生长覆盖在第一半导体层上。以这种方式，获得基本上无缺陷的应变松弛层（1）或其中至少从投影中观察到的部分在绝缘区域（20）上方的至少部分基本上是缺陷的应变松弛层（1） -自由。

5. 发明申请

WO2006109208A2 METHOD OF FABRICATING A HETEROJUNCTION BIPOLAR TRANSISTOR 审中-公开
标题翻译：制备异相双极晶体管的方法
公开(公告)号：WO2006109208A2
公开(公告)日：2006-10-19
申请号：PCT/IB2006/051005
申请日：2006-04-03
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MEUNIER-BEILLARD, Philippe , DONKERS, Johannes, J., T., M. , HIJZEN, Erwin , MELAI, Joost
发明人： MEUNIER-BEILLARD, Philippe , DONKERS, Johannes, J., T., M. , HIJZEN, Erwin , MELAI, Joost
CPC分类号： H01L29/66242 , H01L29/16 , H01L29/7378
摘要： The invention provides a method for fabricating a heterojunction bipolar transistor with a base connecting region (23), which is formed self-aligned to a base region (7) without applying photolithographic techniques. Further, a collector connecting region (31) and an emitter region (29) are formed simultaneously and self-aligned to the base connecting region (23) without applying photolithographic techniques.
摘要翻译：本发明提供了一种用于制造具有基极连接区域（23）的异质结双极晶体管的方法，该基极连接区域（23）在不施加光刻技术的情况下与基极区域（7）自对准地形成。此外，在不使用光刻技术的情况下，集电极连接区域（31）和发射极区域（29）同时形成并且与基底连接区域（23）自对准。

6. 发明申请

WO2003100845A1 METHOD OF FABRICATION SIGE HETEROJUNCTION BIPOLAR TRANSISTOR 审中-公开
标题翻译：制造异常双极晶体管的方法
公开(公告)号：WO2003100845A1
公开(公告)日：2003-12-04
申请号：PCT/IB2003/002034
申请日：2003-05-27
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MAGNEE, Petrus, H., C. , DONKERS, Johannes, J., T., M.
发明人： MAGNEE, Petrus, H., C. , DONKERS, Johannes, J., T., M.
IPC分类号： H01L21/331
CPC分类号： H01L29/66242
摘要： The present invention provides for a method of fabricating a semiconductor device comprising a non-selectively grown SiGe(C) heterojunction bipolar transistor including the steps of forming an insulating layer (12, 40) on a substrate and providing a layer structure including a conductive layer (14, 42) on the insulating layer (12, 40), etching a transistor area opening (12, 44) through the conductive layer (14, 42), depositing a SiGe base layer (24, 46) on the inner wall of the transistor area opening (22, 44) and forming an insulator (32, 52) on an upper surface so as to fill the transistor area opening wherein prior to the filling step, a nitride layer (30, 50) is formed as an inner layer of the transistor area opening (22, 44).
摘要翻译：本发明提供一种制造半导体器件的方法，该半导体器件包括非选择性生长的SiGe（C）异质结双极晶体管，包括以下步骤：在衬底上形成绝缘层（12,40），并提供包括导电层（14,42），通过所述导电层（14,42）蚀刻晶体管区域开口（12,44），在所述绝缘层（12,40）的内壁上沉积SiGe基底层（24,46）所述晶体管区域开口（22,44）并且在上表面上形成绝缘体（32,52）以便填充晶体管区域开口，其中在填充步骤之前，将氮化物层（30,50）形成为内部晶体管区域开口（22,44）的层。

7. 发明申请

WO2007057803A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED WITH SUCH A METHOD 审中-公开
标题翻译：制造半导体器件的方法和采用这种方法获得的半导体器件
公开(公告)号：WO2007057803A1
公开(公告)日：2007-05-24
申请号：PCT/IB2006/053996
申请日：2006-10-29
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MELAI, Joost , HIJZEN, Erwin , MEUNIER-BEILLARD, Philippe , DONKERS, Johannes, J., T., M.
发明人： MELAI, Joost , HIJZEN, Erwin , MEUNIER-BEILLARD, Philippe , DONKERS, Johannes, J., T., M.
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L29/66287
摘要： The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (12) which is provided with at least one bipolar transistor having an emitter region (1), a base region (2) and a collector region (3), wherein in the semiconductor body (12) a first semiconductor region (13) is formed that forms one (3) of the collector and emitter regions (1,3) and on the surface of the semiconductor body (12) a stack of layers is formed comprising a first insulating layer (4), a polycrystalline semiconductor layer (5) and a second insulating layer (6) in which stack an opening (7) is formed, after which by non-selective epitaxial growth a further semiconductor layer (22) is deposited of which a monocrystalline horizontal part on the bottom of the opening (7) forms the base region (2) and of which a polycrystalline vertical part (2A) on a side face of the opening (7) is connected to the polycrystalline semiconductor layer (5), after which spacers (S) are formed parallel to the side face of the opening (7) and a second semiconductor region (31) is formed between said spacers (S) forming the other one (1) of the emitter and collector regions (1,3). According to the invention the above method is characterized in that before the further semiconductor layer (22) is deposited, the second insulating layer (6) is provided with an end portion (6A) that viewed in projection overhangs an end portion (5A) of the underlying semiconductor layer (5). In this way bipolar transistor devices can be obtained with good high frequency properties in a cost effective manner.
摘要翻译：本发明涉及一种制造半导体器件（10）的方法，所述半导体器件（10）具有衬底（11）和半导体本体（12），所述半导体器件（12）具有至少一个具有发射极区域（1），基极区域（2），和集电极区域（3），其中在所述半导体本体（12）中形成第一半导体区域（13），所述第一半导体区域形成所述集电极和发射极区域（1,3）中的一个（3）并且在所述半导体主体（12）形成一叠层，其包括形成有开口（7）的第一绝缘层（4），多晶半导体层（5）和第二绝缘层（6），之后通过非选择性外延生长沉积另外的半导体层（22），其中开口（7）的底部上的单晶水平部分形成基部区域（2），并且在该开口的侧面上具有多晶垂直部分（2A）（7）连接到多晶半导体层（5），之后是间隔（S）形成为平行于开口（7）的侧面，并且在形成发射极和集电极区域（1,3）的另一个（1）的所述间隔物（S）之间形成第二半导体区域（31））。根据本发明，上述方法的特征在于，在沉积另外的半导体层（22）之前，第二绝缘层（6）设置有端部（6A），该端部在突出部分中突出伸出端部（5A）底层半导体层（5）。以这种方式，可以以成本有效的方式获得具有良好高频特性的双极晶体管器件。

8. 发明申请

WO2007015194A2 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUCH A DEVICE 审中-公开
标题翻译：半导体器件和制造这种器件的方法
公开(公告)号：WO2007015194A2
公开(公告)日：2007-02-08
申请号：PCT/IB2006/052559
申请日：2006-07-26
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , DONKERS, Johannes, J., T., M. , VAN NOORT, Wibo, D. , NEUILLY, Francois
发明人： DONKERS, Johannes, J., T., M. , VAN NOORT, Wibo, D. , NEUILLY, Francois
CPC分类号： H01L29/7378 , H01L21/26506 , H01L21/26513 , H01L29/0649 , H01L29/1004 , H01L29/66242 , H01L29/66272 , H01L29/732
摘要： The invention relates to a semiconductor device (10) with a substrate (12) and a semiconductor body (11) of silicon comprising a bipolar transistor with an emitter region, a base region and a collector region (1,2,3) of a first conductivity type, a second conductivity type opposite to said first conductivity type and the first conductivity type, respectively, with a first semiconductor region (3) comprising the collector region or the emitter region being formed in the semiconductor body (11), on top of which a second semiconductor region (2) comprising the base region is present, on top of which a third semiconductor region (1) comprising the other of said collector region and said emitter region is present, said semiconductor body (11) being provided with a constriction at the location of the transition between the first and the second semiconductor region (3, 2) , which constriction has been formed by means of an electrically insulating region (26, 27) buried in the semiconductor body (11). According to the invention a part of the semiconductor body that is formed above the buried electrically insulating region (26,27) is monocrystalline. This enables a strong lateral miniaturization of the device and results in excellent high frequency properties of the transistor. Such a device (10) is possible thanks to its manufacture with a method of manufacturing according to the invention.
摘要翻译：本发明涉及具有衬底（12）和硅半导体主体（11）的半导体器件（10），该半导体器件包括具有发射极区域，基极区域和集电极区域的双极晶体管（第一导电类型，第二导电类型分别与所述第一导电类型和第一导电类型相反，第一半导体区域（3）包括集电极区域或发射极区域，所述第一半导体区域形成在半导体本体（11），在所述半导体本体（11）的顶部上存在包括所述基极区域的第二半导体区域（2），在所述半导体本体的顶部上存在包括所述集电极区域和所述发射极区域中的另一个的第三半导体区域（1），所述半导体本体（11）在第一半导体区域（3）和第二半导体区域（2）之间的过渡位置处设置有收缩部分，该收缩部分通过埋置在第一半导体区域（3）和第二半导体区域中的电绝缘区域 SE 微米线体（11）。根据本发明，形成在掩埋电绝缘区域（26,27）上方的半导体本体的一部分是单晶的。这使得器件的横向小型化强度大大提高，并且使晶体管具有优异的高频特性。由于采用根据本发明的制造方法制造，所以这种装置（10）是可能的。

9. 发明申请

WO2006109221A3 LATERAL BIPOLAR TRANSISTOR 审中-公开
公开(公告)号：WO2006109221A3
公开(公告)日：2006-10-19
申请号：PCT/IB2006/051045
申请日：2006-04-05
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MEUNIER-BEILLARD, Philippe , HUETING, Raymond, J., E. , DONKERS, Johannes, J., T., M. , HIJZEN, Erwin
发明人： MEUNIER-BEILLARD, Philippe , HUETING, Raymond, J., E. , DONKERS, Johannes, J., T., M. , HIJZEN, Erwin
IPC分类号： H01L21/331 , H01L29/735 , H01L27/06 , H01L21/8249
摘要： The invention provides a CMOS-based lateral bipolar transistor and a method of fabricating the same. A CMOS device forms the basis of the CMOS-based lateral bipolar transistor. The CMOS device is provided on a silicon, SOI or SSOI substrate and comprises a source and drain region, CMOS spacers (9, 10) and a removed gate electrode. An emitter region (41) and a collector region (45) are disposed in the source and drain regions, and a base region (43), comprising SiGe or p-type silicon, is provided adjacent to the emitter region (41) and the collector region (45). The base region (43) has a relatively large exposed area, because it is not covered by the, formerly removed, gate electrode. The base resistance may be reduced by providing a metal layer (29) and an electrical contact (33) on the exposed area of the base region (43).

10. 发明申请

WO2004057654A3 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：WO2004057654A3
公开(公告)日：2004-07-08
申请号：PCT/IB2003/006017
申请日：2003-12-16
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW , MAGNEE, Petrus, H., C. , DONKERS, Johannes, J., T., M. , SHI, Xiaoping
发明人： MAGNEE, Petrus, H., C. , DONKERS, Johannes, J., T., M. , SHI, Xiaoping
IPC分类号： H01L21/20
摘要： Method of manufacturing a semiconductor device, in which on a region of silicon oxide (5) situated next to a region of monocrystalline silicon (4) at the surface (3) of a semiconductor body (1), a non-monocrystalline auxiliary layer (8) is formed. The auxiliary layer is formed in two steps. In the first step, the silicon body is heated in an atmosphere comprising a gaseous arsenic compound; in the second step it is heated in an atmosphere comprising a gaseous silicon compound instead of said arsenic compound. Thus, the regions of silicon oxide are provided with an amorphous or polycrystalline silicon seed layer in a self-aligned manner.

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