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1. 发明申请

WO2013074516A1 IMPROVED READ OPERATION FOR NON-VOLATILE STORAGE SYSTEM WITH NAND STRINGS SHARING BIT LINE AND WORD LINES 审中-公开
标题翻译：改进非易失存储系统的读取操作，具有共享字线和字线的NAND条
公开(公告)号：WO2013074516A1
公开(公告)日：2013-05-23
申请号：PCT/US2012/064818
申请日：2012-11-13
申请人： SANDISK TECHNOLOGIES, INC. , MOKHLESI, Nima , DUNGA, Mohan, V. , MUI, Man
发明人： MOKHLESI, Nima , DUNGA, Mohan, V. , MUI, Man
IPC分类号： G11C11/56 , G11C16/04 , G11C16/26 , G11C16/34 , H01L27/115
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/3427 , H01L27/11524
摘要： A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line. One set of embodiments avoid unwanted boosting during read operations by keeping the channels of the memory cells connected to word lines on the drain side of the selected word line biased at a fixed potential.
摘要翻译：公开了一种非易失性存储系统，其包括连接到共享位线的同一块中的NAND串（或存储器单元的其它组）对。为了操作该系统，使用两条选择线，使得可以在块级选择共享位线的NAND串（或存储器单元的其它分组）。两个选择线连接到共享位线的每个NAND串（或存储器单元的其它组）的选择门。一组实施例通过将存储器单元的通道与所选择的字线的漏极侧的字线连接以偏置固定电位来避免读取操作期间的不希望的升压。

2. 发明申请

WO2012082223A2 NON-VOLATILE STORAGE SYSTEM WITH SHARED BIT LINES CONNECTED TO SINGLE SELECTION DEVICE 审中-公开
标题翻译：具有连接到单个选择设备的共享位线的非易失存储系统
公开(公告)号：WO2012082223A2
公开(公告)日：2012-06-21
申请号：PCT/US2011/056146
申请日：2011-10-13
申请人： SANDISK TECHNOLOGIES, INC. , MOKHLESI, Nima , DUNGA, Mohan, V. , HIGASHITANI, Masaaki
发明人： MOKHLESI, Nima , DUNGA, Mohan, V. , HIGASHITANI, Masaaki
CPC分类号： H01L21/28273 , G11C16/0483 , H01L27/11519 , H01L27/11521
摘要： A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line.
摘要翻译：公开了一种非易失性存储系统，其包括连接到共享位线的同一块中的NAND串（或存储器单元的其它组）对。为了操作该系统，使用两条选择线，使得可以在块级选择共享位线的NAND串（或存储器单元的其它分组）。两个选择线连接到共享位线的每个NAND串（或存储器单元的其它组）的选择门。

3. 发明申请

WO2008121535A1 NON-VOLATILE MEMORY AND METHOD FOR COMPENSATION FOR VOLTAGE DROPS ALONG A WORD LINE 审中-公开
标题翻译：非挥发性记忆和方法，用于补偿字线上的电压降
公开(公告)号：WO2008121535A1
公开(公告)日：2008-10-09
申请号：PCT/US2008/056975
申请日：2008-03-14
申请人： SANDISK CORPORATION , SEKAR, Deepak Chandra , MUI, Man Lung , MOKHLESI, Nima
发明人： SEKAR, Deepak Chandra , MUI, Man Lung , MOKHLESI, Nima
IPC分类号： G11C16/12 , G11C16/04 , G11C11/56
CPC分类号： G11C16/12 , G11C7/18 , G11C8/14 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/30
摘要： Variation in programming efficacy due to variation in time constants along a word line that spans across a memory plane is compensated by adjusting the bit line voltages across the plane to modify the programming rates. In this way, the variation in programming efficacy is substantially reduced during programming of a group of memory cells coupled to the word line. This will allow uniform optimization of programming across the group of memory cells and reduce the number of programming pulses required to program the group of memory cells, thereby improving performance. In one embodiment, during programming, the bit lines in a first half of the memory plane closer to a source of word line voltage is set to a first voltage by a first voltage shifter and the bit lines in a second half of the memory plane further from the source of word line voltage is set to a second voltage by a second voltage shifter.
摘要翻译：由跨越存储器平面的字线的时间常数变化引起的编程效能的变化通过调整整个平面上的位线电压来修正编程速率来补偿。以这种方式，在编程耦合到字线的一组存储器单元的编程期间，编程功效的变化显着降低。这将允许对存储器单元组进行编程的均匀优化，并且减少编程存储器单元组所需的编程脉冲数，从而提高性能。在一个实施例中，在编程期间，更靠近字线电压源的存储器平面的前半部分中的位线被第一电压移位器设置为第一电压，并且存储器平面的后半部分中的位线进一步从第二电压转换器将字线电压源设定为第二电压。

4. 发明申请

WO2013074528A1 NON-VOLATILE STORAGE WITH BROKEN WORD LINE SCREEN AND DATA RECOVERY 审中-公开
标题翻译：非易失存储器，带有清晰的字线屏幕和数据恢复
公开(公告)号：WO2013074528A1
公开(公告)日：2013-05-23
申请号：PCT/US2012/064838
申请日：2012-11-13
申请人： SANDISK TECHNOLOGIES, INC. , MOKHLESI, Nima , GU, Lanlan , GHAI, Ashish, Pal Singh , RAGHU, Deepak
发明人： MOKHLESI, Nima , GU, Lanlan , GHAI, Ashish, Pal Singh , RAGHU, Deepak
IPC分类号： G11C11/56 , G11C16/34 , G11C29/52 , G11C29/02 , G11C29/50 , G06F11/10
CPC分类号： G11C16/04 , G06F11/1072 , G11C11/5642 , G11C16/00 , G11C16/3404 , G11C16/349 , G11C29/025 , G11C29/04 , G11C29/50016 , G11C29/52 , G11C2029/0409 , G11C2029/0411
摘要： Data, normally read using a page-by page read process, can be recovered from memory cells connected to a broken word line by performing a sequential read process. To determine whether a word line is broken, both a page-by page read process and a sequential read process are performed. The results of both read processes are compared. If the number of mismatches between the two read processes is greater than a threshold, it is concluded that there is a broken word line.
摘要翻译：通过执行顺序读取处理，能够通过逐页读取处理正常读取的数据可以从连接到破碎的字线的存储单元中恢复。为了确定字线是否断开，执行逐页读取处理和顺序读取处理。比较两个读取过程的结果。如果两个读取过程之间的错配数量大于阈值，则得出结论是存在断字。

5. 发明申请

WO2011149823A1 PROGRAMMING NON-VOLATILE STORAGE WITH SYNCHRONIZED COUPLING 审中-公开
标题翻译：编程具有同步耦合的非易失性存储
公开(公告)号：WO2011149823A1
公开(公告)日：2011-12-01
申请号：PCT/US2011/037526
申请日：2011-05-23
申请人： SANDISK TECHNOLOGIES, INC. , MOKHLESI, Nima , CHIN, Henry , HIGASHITANI, Masaaki
发明人： MOKHLESI, Nima , CHIN, Henry , HIGASHITANI, Masaaki
IPC分类号： G11C11/56 , G11C16/10 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10
摘要： A process for programming non-volatile storage is able to achieve faster programming speeds and/or more accurate programming through synchronized coupling of neighboring word lines. The process for programming includes raising voltages for a set of word lines connected tol5 a group of connected non-volatile storage elements. The set of word lines includes a selected word line(WLn), unselected word lines (WLn+1/WLn- 1) that are adjacent to the selected word line and other unselected word lines (WLunse1). After raising voltages for the set of word lines, the process includes raising the selected word line to a program voltage (Vpgm) and raising the unselected word lines that are adjacent to the selected word line to one or more voltage levels (Vint1, Vint2, Vint3 ) concurrently with the raising the selected word line to the program voltage. The program voltage causes at least one of the non-volatile storage elements to experience programming.
摘要翻译：用于编程非易失性存储器的过程能够通过相邻字线的同步耦合来实现更快的编程速度和/或更精确的编程。编程过程包括提高连接到一组连接的非易失性存储元件的一组字线的电压。该字线组包括与所选择的字线和其他未被选择的字线（WLunse1）相邻的所选字线（WLn），未选字线（WLn + 1 / WLn-1）。在对所述一组字线提升电压之后，所述处理包括将所选择的字线升高到编程电压（Vpgm），并将与所选字线相邻的未选字线提升到一个或多个电压电平（Vint1，Vint2， Vint3）同时将选定的字线提升到编程电压。程序电压使至少一个非易失性存储元件经历编程。

6. 发明申请

WO2011119500A1 SIMULTANEOUS MULTI-STATE READ OR VERIFY IN NON-VOLATILE STORAGE 审中-公开
标题翻译：在非易失性存储中同时进行多状态读取或验证
公开(公告)号：WO2011119500A1
公开(公告)日：2011-09-29
申请号：PCT/US2011/029256
申请日：2011-03-21
申请人： SANDISK IL LTD. , SHARON, Eran , LI, Yan , MOKHLESI, Nima
发明人： SHARON, Eran , LI, Yan , MOKHLESI, Nima
IPC分类号： G11C11/56 , G11C16/04 , G11C16/34
CPC分类号： G11C16/3459 , G11C11/5642 , G11C16/0483 , G11C16/3454 , G11C2211/5624 , G11C2211/5631
摘要： Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross- coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time.
摘要翻译：公开了用于同时验证或读取非易失性存储器中的多个状态的方法和装置。公开了用于有效地减少或消除非易失性存储器中的交叉耦合效应的方法和装置。公开了用于有效执行多个电压读取以搜索存储器单元的阈值电压的方法和装置。可以在不同的NAND串上同时读取的存储单元测试不同的阈值电压电平。可以通过对不同阈值电压进行测试的存储器单元施加不同的栅极至源极电压来对不同阈值电压进行存储单元的测试。可以通过对存储器单元施加不同的漏极到源极电压来对不同的阈值电压测试存储器单元。交叉耦合影响的不同量的补偿可以应用于同时读取或编程的不同NAND串上的存储单元。

7. 发明申请

WO2009082637A1 REGULATION OF SOURCE POTENTIAL TO COMBAT CELL SOURCE IR DROP 审中-公开
标题翻译：源电位对调节细胞来源红细胞减少的调节
公开(公告)号：WO2009082637A1
公开(公告)日：2009-07-02
申请号：PCT/US2008/086694
申请日：2008-12-12
申请人： SANDISK CORPORATION , LEE, Dana , MOKHLESI, Nima , SEKAR, Deepak Chandra
发明人： LEE, Dana , MOKHLESI, Nima , SEKAR, Deepak Chandra
IPC分类号： G11C16/30
CPC分类号： G11C16/30
摘要： Techniques are presented for dealing with possible source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits of a non-volatile memory. The error is caused by a voltage drop across the resistance of the source path to the chip's ground when current flows. For this purpose, the memory device includes a source potential regulation circuit, including an active circuit element having a first input connected to a reference voltage and having a second input connected as a feedback loop that is connectable to the aggregate node from which the memory cells of a structural block have their current run to ground. A variation includes a non-linear resistive element connectable between the aggregate node and ground.
摘要翻译：提出用于处理可能的源极偏置的技术是由非易失性存储器的读/写电路的接地回路中的非零电阻引入的误差。误差是由电流流动时芯片接地源极路径的电阻上的电压降引起的。为此，存储器件包括源极电位调节电路，其包括有源电路元件，该有源电路元件具有连接到参考电压的第一输入端，并且具有连接到反馈回路的第二输入端，该反馈回路可连接到汇集节点，存储器单元的结构块现在已经跑到地面上了。变化包括可在聚集节点和地之间连接的非线性电阻元件。

8. 发明申请

WO2008121577A1 SOFT BIT DATA TRANSMISSION FOR ERROR CORRECTION CONTROL IN NON-VOLATILE MEMORY 审中-公开
标题翻译：用于非易失性存储器中的错误校正控制的软位数据传输
公开(公告)号：WO2008121577A1
公开(公告)日：2008-10-09
申请号：PCT/US2008/057722
申请日：2008-03-20
申请人： SANDISK CORPORATION , MOKHLESI, Nima , CHIN, Henry , ZHAO, Dengtao
发明人： MOKHLESI, Nima , CHIN, Henry , ZHAO, Dengtao
IPC分类号： G11C11/56 , G06F11/10
CPC分类号： G11C11/5642 , G06F11/1068 , G11C7/1006 , G11C16/0483 , G11C16/26 , G11C29/00 , G11C2211/5634
摘要： Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Soft data bits are read from the memory if the decoding fails to converge. Initial reliability metric values are provided after receiving the hard read results and at each phase of the soft bit operation(s). In one embodiment, a second soft bit is read from the memory using multiple subsets of soft bit compare levels. While reading at the second subset of compare levels, decoding can be performed based on the first subset data.
摘要翻译：使用迭代概率解码对存储在非易失性存储器中的数据进行解码。可以使用诸如低密度奇偶校验码的纠错码。在一种方法中，初始可靠性度量（诸如对数似然比）被用于解码一组非易失性存储元件的感测状态。解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。如果解码失败，则从存储器读取软数据位。在接收到硬读取结果之后以及在软位操作的每个阶段提供初始可靠性度量值。在一个实施例中，使用软比特比较级的多个子集从存储器读取第二软比特。在比较电平的第二子集读取时，可以基于第一子集数据执行解码。

9. 发明申请

WO2008083196A2 MARGINED NEIGHBOR READING FOR NON-VOLATILE MEMORY READ OPERATIONS INCLUDING COUPLING COMPENSATION 审中-公开
标题翻译：附带阅读非易失性存储器阅读操作，包括联合补偿
公开(公告)号：WO2008083196A2
公开(公告)日：2008-07-10
申请号：PCT/US2007/088899
申请日：2007-12-27
申请人： SANDISK CORPORATION , MOKHLESI, Nima
发明人： MOKHLESI, Nima
IPC分类号： G11C16/26 , G11C16/34 , G11C11/56
CPC分类号： G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C29/00 , G11C2211/5646
摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To account for this coupling, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell. When reading the adjacent cell to determine the appropriate compensation, margined read voltages can be used.
摘要翻译：存在于非易失性存储单元的浮动栅极（或其他电荷存储元件）上的表观电荷的变化可能发生，因为基于存储在相邻浮动栅极（或其它相邻电荷存储元件）中的电荷的电场的耦合）。在不同时间编程的相邻存储器单元组之间最明显地出现该问题。为了解决这种耦合，特定存储器单元的读取过程将向相邻存储器单元提供补偿，以便减少相邻存储单元对特定存储单元的耦合效应。当读取相邻单元以确定适当的补偿时，可以使用边缘读取电压。

10. 发明申请

WO2008083136A2 RESISTANCE SENSING AND COMPENSATION FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：非易失性存储器的电阻检测和补偿
公开(公告)号：WO2008083136A2
公开(公告)日：2008-07-10
申请号：PCT/US2007/088786
申请日：2007-12-24
申请人： SANDISK CORPORATION , MOKHLESI, Nima , CERNEA, Raul-adrian
发明人： MOKHLESI, Nima , CERNEA, Raul-adrian
CPC分类号： G11C11/5642 , G11C11/5628 , G11C16/0483 , G11C16/26
摘要： When reading data from a non-volatile storage element that is part of a group of connected non-volatile storage elements, resistance information is measured for the group. One or more read parameters are set based on the measured resistance information. The read process is then performed using the one or more parameters.
摘要翻译：当从作为一组连接的非易失性存储元件的一部分的非易失性存储元件读取数据时，测量该组的电阻信息。根据测量的电阻信息设置一个或多个读取参数。然后使用一个或多个参数执行读取过程。

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