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1. 发明申请

WO2014039459A1 NON-VOLATILE STORAGE WITH JOINT HARD BIT AND SOFT BIT READING 审中-公开
标题翻译：非挥发性储存与联合硬头和软位阅读
公开(公告)号：WO2014039459A1
公开(公告)日：2014-03-13
申请号：PCT/US2013/057894
申请日：2013-09-03
申请人： SANDISK TECHNOLOGIES, INC. , SHARON, Eran , ALROD, Idan , LI, Yan , KOH, Yee, Lih , KUO, Tien-chien
发明人： SHARON, Eran , ALROD, Idan , LI, Yan , KOH, Yee, Lih , KUO, Tien-chien
IPC分类号： G11C11/56 , G06F11/10
CPC分类号： G11C16/26 , G06F11/1012 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C2211/5624 , G11C2211/5631 , G11C2211/5632
摘要： A system is disclosed for reading hard bit information (650, 654) and soft bit information (670, 672, 674, 676) from non-volatile storage. Some of the hard bit information and/or soft bit information is read concurrently by using different bit line voltages, different integration times, different sense levels within the sense amplifiers, or other techniques. A method is disclosed for determining the hard bits and soft bits in real time based on sensed hard bit information and soft bit information.
摘要翻译：公开了一种用于从非易失性存储器读取硬比特信息（650,654）和软比特信息（670,672,674,676）的系统。一些硬比特信息和/或软比特信息通过使用不同的位线电压，不同的积分时间，读出放大器内的不同感测电平或其他技术同时读取。公开了一种基于感测的硬比特信息和软比特信息来实时确定硬比特和软比特的方法。

2. 发明申请

WO2013016390A3 NON-VOLATILE MEMORY AND METHOD WITH ACCELERATED POST-WRITE READ USING COMBINED VERIFICATION OF MULTIPLE PAGES 审中-公开
标题翻译：非易失性存储器和使用多个页面的组合验证的加速后写入读取方法
公开(公告)号：WO2013016390A3
公开(公告)日：2013-06-20
申请号：PCT/US2012048074
申请日：2012-07-25
申请人： SANDISK TECHNOLOGIES INC , SHARON ERAN
发明人： SHARON ERAN
IPC分类号： G11C11/56 , G06F11/10
CPC分类号： G11C11/5642 , G06F11/1048
摘要： A post-write read operation, using a combined verification of multiple pages of data, is presented. In a simultaneous verification of multiple pages in a block, the controller evaluates a combined function of the multiple pages, instead of evaluating each page separately. In one exemplary embodiment, the combined function is formed by XORing the pages together. Such a combined verification of multiple pages based on the read data can significantly reduce the controller involvement, lowering the required bus and ECC bandwidth for a post-write read and hence allow efficient post-write reads when the number of dies is large.
摘要翻译：提出了使用多页数据的组合验证的写入后读取操作。在同时验证块中的多个页面时，控制器评估多个页面的组合功能，而不是分别评估每个页面。在一个示例性实施例中，通过将页面合并在一起而形成组合功能。基于读取的数据对多页的这种组合验证可以显着地减少控制器的参与，降低用于写入后读取的所需总线和ECC带宽，并且因此当模具数量较大时允许有效的后写入读取。

3. 发明申请

WO2013016397A3 POST-WRITE READ IN NON-VOLATILE MEMORIES USING COMPARISON OF DATA AS WRITTEN IN BINARY AND MULTI-STATE FORMATS 审中-公开
标题翻译：在非易失性存储器中使用双向和多态格式中的数据进行比较读写
公开(公告)号：WO2013016397A3
公开(公告)日：2013-04-18
申请号：PCT/US2012048087
申请日：2012-07-25
申请人： SANDISK TECHNOLOGIES INC , SHARON ERAN , ALROD IDAN
发明人： SHARON ERAN , ALROD IDAN
IPC分类号： G11C16/34 , G06F11/10 , G11C11/56
CPC分类号： G11C16/3459 , G06F11/1072 , G11C11/5628 , G11C16/3481 , G11C2211/5641
摘要： Techniques for a post-write read are presented. In an exemplary embodiment, host data is initially written into the non-volatile memory in binary form, such as a non-volatile binary cache. It is then subsequently written from the binary section (410) into a multi-state nonvolatile section (420) of the memory. After being written in multi-state format, pages of data from a multi-state block can then be checked against there source pages in the binary section to verify the quality of the multi-state write. This process can be performed on the memory device itself, without transferring the pages out to the controller.
摘要翻译：介绍了写入后读取技术。在示例性实施例中，主数据最初以二进制形式写入非易失性存储器，例如非易失性二进制高速缓存。随后将其从二进制部分（410）写入存储器的多状态非易失性部分（420）。在以多状态格式写入后，可以在二进制部分的源页面中检查来自多状态块的数据页面，以验证多状态写入的质量。该过程可以在存储器设备本身上执行，而不将页面传送到控制器。

4. 发明申请

WO2013016393A1 DATA RECOVERY FOR DEFECTIVE WORD LINES DURING PROGRAMMING OF NON-VOLATILE MEMORY ARRAYS 审中-公开
标题翻译：在非易失性存储器阵列的编程过程中，针对有缺陷的字线的数据恢复
公开(公告)号：WO2013016393A1
公开(公告)日：2013-01-31
申请号：PCT/US2012/048080
申请日：2012-07-25
申请人： SANDISK TECHNOLOGIES INC. , SHARON, Eran , ALROD, Idan
发明人： SHARON, Eran , ALROD, Idan
IPC分类号： G06F11/10
CPC分类号： G11C29/04 , G06F11/1048 , G06F11/1072 , G11C29/82
摘要： The recovery of data during programming, such as in the case of a broken word-line, is considered. The arrangement described assumes that k pages may be corrupted when the system finishes programming a block. Then these corrupted pages can be recovered using an erasure code. In order to recover any k pages, the system will compute and temporarily store k parity pages in the controller. These k parity pages may be computed on-the-fly as the data pages are received from the host. Once programming of the block is finished, a post-write read may be done in order to validate that the data is stored reliably. If no problem is detected during EPWR, then the parity pages in the controller may be discarded. In case a problem is detected, and data in up to k pages is corrupt on some bad word-lines, then the missing data is recovered using the k parity pages that are stored in the controller and using the other non-corrupted pages that are read from the block of the memory array and decoded. Once the recovery is complete the block can be reprogrammed and the temporary parity pages in the controller may be discarded upon successfully reprogramming.
摘要翻译：考虑在编程期间恢复数据，例如在字线断开的情况下。所描述的布置假设当系统完成对块的编程时，k页可能被破坏。然后可以使用擦除代码恢复这些损坏的页面。为了恢复任何k页，系统将在控制器中计算和临时存储k个奇偶校验页面。当从主机接收到数据页时，这些k个奇偶校验页可以在运行中计算。一旦块的编程完成，可以进行写入后读取，以便验证数据是否被可靠地存储。如果在EPWR期间没有检测到问题，则可能会丢弃控制器中的奇偶校验页。如果检测到问题，并且在一些不良字线上，最多k页的数据已损坏，则使用存储在控制器中的k个奇偶校验页和使用其他未损坏的页面来恢复丢失的数据从存储器阵列中读取并解码。恢复完成后，可以重新编程块，并且在成功重新编程后，可能会丢弃控制器中的临时奇偶校验页。

5. 发明申请

WO2011161622A1 OPTIMIZED FLASH MEMORY WITHOUT DEDICATED PARITY AREA AND WITH REDUCED ARRAY SIZE 审中-公开
标题翻译：优化的闪存，没有专用的区域和减少的阵列大小
公开(公告)号：WO2011161622A1
公开(公告)日：2011-12-29
申请号：PCT/IB2011/052706
申请日：2011-06-21
申请人： SANDISK IL LTD. , SHARON, Eran , ALROD, Idan , LITSYN, Simon
发明人： SHARON, Eran , ALROD, Idan , LITSYN, Simon
IPC分类号： G11C11/56 , G06F11/10 , G11C16/10
CPC分类号： G06F12/0246 , G06F11/1072 , G06F11/1076 , G11C7/1006 , G11C11/5628 , G11C16/10 , G11C29/00 , G11C2211/5641 , H03M13/05
摘要： A method and system for optimizing flash memory without dedicated parity area and with reduced array size. The memory size of a multi level cell (MLC) flash is reduced and controller operation is simplified. Simplified operation includes the controller being able to program each host data page to an integer number of flash pages. A maximal available information bits per cell (IBPC) is maintained in a flash device while also maximizing the programming throughput of the flash. Features include the ability to dynamically select which number of cell states is used by flash memory cells.
摘要翻译：一种用于优化闪存而没有专用奇偶校验区和减小阵列大小的方法和系统。多级单元（MLC）闪存的存储器容量减小，控制器操作简化。简化操作包括控制器能够将每个主机数据页面编程为整数个闪存页面。在闪存设备中维护每个单元（IBPC）的最大可用信息位，同时还使闪存的编程吞吐量最大化。特性包括动态选择闪存单元使用哪些单元状态的能力。

6. 发明申请

WO2011031660A2 IDENTIFYING AT-RISK DATA IN NON-VOLATILE STORAGE 审中-公开
标题翻译：在非易失性存储中识别风险数据
公开(公告)号：WO2011031660A2
公开(公告)日：2011-03-17
申请号：PCT/US2010/047951
申请日：2010-09-07
申请人： SANDISK CORPORATION , PEI, Gen , GU, Lanlan , MOKHLESI, Nima , ALROD, Idan , SHARON, Eran , AFRIAT, Itshak
发明人： PEI, Gen , GU, Lanlan , MOKHLESI, Nima , ALROD, Idan , SHARON, Eran , AFRIAT, Itshak
IPC分类号： G11C16/34
CPC分类号： G11C16/3418 , G06F11/1072
摘要： The non-volatile storage system predicts which blocks (or other units of storage) will become bad based on performance data. User data in those blocks predicted to become bad can be re-programmed to other blocks, and the blocks predicted to become bad can be removed from further use.
摘要翻译：非易失性存储系统基于性能数据预测哪些块（或其他存储单元）将变坏。预测为坏的那些块中的用户数据可以被重新编程到其他块，并且预测为坏的块可以被进一步使用。

7. 发明申请

WO2011010286A4 COMPACT DECODING OF PUNCTURED CODES 审中-公开
公开(公告)号：WO2011010286A4
公开(公告)日：2011-01-27
申请号：PCT/IB2010/053317
申请日：2010-07-21
申请人： RAMOT AT TEL AVIV UNIVERSITY LTD. , SHARON, Eran , ALROD, Idan , LITSYN, Simon
发明人： SHARON, Eran , ALROD, Idan , LITSYN, Simon
IPC分类号： H03M13/00 , H03M13/25 , H04L1/00
摘要： k input bits are encoded according to a code with which is associated a m x n=m+k parity check matrix H . The resulting codeword is punctured, with n' bits. The punctured codeword is exported to a corrupting medium such as a communication channel or a memory. A representation of the punctured codeword is imported from the corrupting medium and is decoded using a matrix H' that is smaller than H . For example, H' is m'=m~(n-n ') x n' and is derived by merging selected rows of H . Alternatively, H has at most m rows and fewer than n columns but more than n' columns. Alternatively, H has fewer than m'=m-(n-n') rows and fewer than n' columns.

8. 发明申请

WO2009156935A4 USING DAMPING FACTORS TO OVERCOME LDPC TRAPPING SETS 审中-公开
公开(公告)号：WO2009156935A4
公开(公告)日：2009-12-30
申请号：PCT/IB2009/052662
申请日：2009-06-22
申请人： RAMOT AT TEL AVIV UNIVERSITY LTD. , SHARON, Eran , LITSYN, Simon , ALROD, Idan
发明人： SHARON, Eran , LITSYN, Simon , ALROD, Idan
IPC分类号： H03M13/11
摘要： To decode a representation, imported from a channel, of a codeword that encodes K information bits as N>K codeword bits, estimates of the codeword bits are updated by exchanging messages between JV bit nodes and N-K check nodes of a graph in a plurality of iterations. In each of one or more of the iterations, some or all values associated with the bit nodes, and/or some or all values associated with check nodes, and/or some or all messages are modified in a manner that depends explicitly on the ordinality of the iteration and is independent of any other iteration. Alternatively, the modifications are according to respective locally heteromorphic rules.

9. 发明申请

WO2009104063A1 METHOD AND DEVICE FOR ADAPTIVE DECODING USING GLOBAL PARITY BITS 审中-公开
标题翻译：使用全球特征位自适应解码的方法和装置
公开(公告)号：WO2009104063A1
公开(公告)日：2009-08-27
申请号：PCT/IB2008/055477
申请日：2008-12-21
申请人： RAMOT AT TEL AVIV UNIVERSITY LTD. , LITSYN, Simon , SHARON, Eran , ALROD, Idan , LASSER, Menahem
发明人： LITSYN, Simon , SHARON, Eran , ALROD, Idan , LASSER, Menahem
IPC分类号： H03M13/29 , G06F11/10 , H03M13/11
CPC分类号： H03M13/2927 , G06F11/1068 , H03M13/1111 , H03M13/152 , H03M13/1545 , H03M13/2903 , H03M13/2906 , H03M13/3707 , H03M13/6362
摘要： Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many- to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. A subset whose decoding is terminated is decoded again, at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits.
摘要翻译：要编码的数据位被分割成多个子组。每个子组被分别编码以产生相应的码字。所选择的子集从相应的码字中移除，留下缩短的码字，并且被多对一地转换成浓缩比特。最终码字是缩短的码字和浓缩比特的组合。最终码字的表示被分割成选定的子集和多个剩余子集。每个剩余子集被单独解码。解码终止的子集至少部分地根据所选择的子集被再次解码。如果编码和解码是系统的，则所选择的子集是奇偶校验位。

10. 发明申请

WO2007043042A3 METHOD OF ERROR CORRECTION IN MBC FLASH MEMORY 审中-公开
标题翻译： MBC闪存中错误校正方法
公开(公告)号：WO2007043042A3
公开(公告)日：2008-12-31
申请号：PCT/IL2006001159
申请日：2006-10-04
申请人： UNIV RAMOT , LITSYN SIMON , ALROD IDAN , SHARON ERAN , MURIN MARK , LASSER MENACHEM
发明人： LITSYN SIMON , ALROD IDAN , SHARON ERAN , MURIN MARK , LASSER MENACHEM
IPC分类号： G11C29/00
CPC分类号： G06F11/1072
摘要： A plurality of logical pages is stored in a MBC flash memory (42) along with corresponding ECC bits, with at least one of the MBC cells storing bits from more than one logical page, and with at least one of the ECC bits applying to two or more of the logical pages. When the pages are read from the memory (42), the data bits as read are corrected using the ECC bits as read. Alternatively, a joint, systematic or non-systematic ECC codeword is computed for two or more of the logical pages and is stored instead of those logical pages. When the joint codeword is read, the logical bits are recovered from the codeword as read. The scope of the invention also includes corresponding memory devices (54, 56, 5S), the controllers of such memory devices (54, 56, 58), and also computer-readable storage media bearing computer-readable code for implementing the methods.
摘要翻译：多个逻辑页面与相应的ECC位一起存储在MBC闪速存储器（42）中，其中至少一个MBC单元存储来自多于一个逻辑页面的位，并且至少一个ECC位应用于两个或更多的逻辑页面。当从存储器（42）读取页面时，读取的数据位使用被读取的ECC位进行校正。或者，针对两个或多个逻辑页面计算联合的，系统的或非系统的ECC码字，并且存储该代码字而不是那些逻辑页面。当读取联合码字时，从读取的码字中恢复逻辑比特。本发明的范围还包括对应的存储设备（54,56,5S），这些存储设备（54,56,58）的控制器，以及用于实现该方法的具有计算机可读代码的计算机可读存储介质。

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