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1. 发明申请

WO2017074555A1 3D NAND DEVICE WITH FIVE-FOLDED MEMORY STACK STRUCTURE CONFIGURATION 审中-公开
标题翻译：具有五折存储器堆叠结构配置的3D NAND器件
公开(公告)号：WO2017074555A1
公开(公告)日：2017-05-04
申请号：PCT/US2016/049763
申请日：2016-08-31
申请人： SANDISK TECHNOLOGIES LLC
发明人： OGAWA, Hiroyuki , TANAKA, Hiroyuki
IPC分类号： H01L29/66 , H01L29/788 , H01L29/792 , H01L27/115
CPC分类号： H01L27/11556 , H01L23/5226 , H01L23/5283 , H01L27/11519 , H01L27/11565 , H01L27/11582
摘要： A three-dimensional semiconductor device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack and arranged in at least five rows that extend along a first horizontal direction, contact via structures arranged in a same number of rows as the memory stack structures and overlying the memory stack structures, each of the contact via structures being electrically connected to a semiconductor channel of a respective memory stack structure, bit lines contacting a respective contact via structure and extending along a second horizontal direction that is different from the first horizontal direction, and a pair of wall-shaped via structures extending through the alternating stack and laterally extending along the first horizontal direction.
摘要翻译：三维半导体器件包括位于衬底上方的绝缘层和导电层的交替堆叠，存储器堆叠结构延伸穿过交替堆叠并且布置成至少五行，其沿第一经由与所述存储器堆叠结构排列成相同行数并且覆盖所述存储器堆叠结构的结构的接触通孔结构，所述接触通孔结构中的每一者电连接到相应存储器堆叠结构的半导体沟道，接触相应存储器堆叠结构的半导体沟道经由结构接触并且沿着不同于第一水平方向的第二水平方向延伸;以及一对壁状通孔结构，延伸穿过交替叠层并沿着第一水平方向横向延伸。

2. 发明申请

WO2016153597A1 PILLAR ARRANGEMENT IN NAND MEMORY 审中-公开
标题翻译： NAND存储器中的支架布置
公开(公告)号：WO2016153597A1
公开(公告)日：2016-09-29
申请号：PCT/US2016/015212
申请日：2016-01-27
申请人： INTEL CORPORATION
发明人： WOLSTENHOLME, Graham, Richard
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11551 , H01L27/0207 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/11582
摘要： Embodiments of the present disclosure are directed towards techniques and configurations for providing a 3D memory array apparatus. In one embodiment, the apparatus may comprise a substantially hexagonal arrangement having seven pillars disposed in a die in a repeating pattern. The arrangement may include first and second pillars disposed at a pillar pitch from each other in a first row; third, fourth, and fifth pillars disposed at the pillar pitch from each other in a second row; and sixth and seventh pillar disposed at the pillar pitch from each other in a third row and shifted relative to the first and second pillars respectively by a quarter of the pillar pitch in a direction that is substantially orthogonal to bitlines disposed in the die. Each pillar in the arrangement may be electrically coupled with a different bitline. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例涉及用于提供3D存储器阵列装置的技术和配置。在一个实施例中，该装置可以包括基本上六边形的布置，其具有以重复图案设置在模具中的七个支柱。该布置可以包括在第一排中彼此以柱间距设置的第一和第二柱; 第三柱，第四柱和第五柱，在第二排中彼此以柱间距排列; 第六柱和第七柱以第三排彼此相互间隔设置，并且相对于第一和第二柱相对于基本上与设置在模具中的位线正交的方向分别移动四分之一的柱间距。该装置中的每个支柱可以与不同的位线电耦合。可以描述和/或要求保护其他实施例。

3. 发明申请

WO2016135849A1 半導体記憶装置及びその製造方法审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：WO2016135849A1
公开(公告)日：2016-09-01
申请号：PCT/JP2015/055206
申请日：2015-02-24
申请人：株式会社東芝
发明人：関根　克行 , 加藤　竜也 , 荒井　史隆 , 岩本　敏幸 , 渡辺　優太 , 坂本　渉 , 糸川　寛志 , 金子　明生
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11556 , H01L21/02164 , H01L21/0217 , H01L21/02181 , H01L21/02271 , H01L21/02532 , H01L21/02592 , H01L21/0262 , H01L21/02636 , H01L21/28273 , H01L21/28562 , H01L21/28568 , H01L21/3065 , H01L21/31111 , H01L21/31116 , H01L21/76801 , H01L27/11519 , H01L29/1037 , H01L29/42324 , H01L29/456 , H01L29/4958 , H01L29/4966 , H01L29/4975 , H01L29/513 , H01L29/515 , H01L29/517 , H01L29/66666 , H01L29/7827 , H01L29/7883 , H01L29/7889
摘要：実施形態に係る半導体記憶装置は、第１方向に延びる半導体ピラーと、前記第１方向に対して交差した第２方向に延びる第１電極と、前記半導体ピラーと前記第１電極との間に設けられた第２電極と、前記半導体ピラーと前記第２電極との間に設けられた第１絶縁膜と、前記第１電極と前記第２電極との間、及び、前記第１電極の前記第１方向両側に設けられた第２絶縁膜と、前記第２電極と前記第２絶縁膜との間に設けられ、前記第１絶縁膜に接していない導電膜と、を備える。
摘要翻译：根据本发明的实施例，该半导体存储装置设置有：沿第一方向延伸的半导体柱; 第一电极，沿与第一方向相交的第二方向延伸; 设置在所述半导体柱和所述第一电极之间的第二电极; 设置在所述半导体柱和所述第二电极之间的第一绝缘膜; 第二绝缘膜，设置在第一电极和第二电极之间，并且在第一电极侧的第一方向上; 以及设置在第二电极和第二绝缘膜之间并且不与第一绝缘膜接触的导电膜。

4. 发明申请

WO2016053453A1 3D SEMICIRCULAR VERTICAL NAND STRING WITH SELF ALIGNED FLOATING GATE OR CHARGE TRAP CELL MEMORY CELLS AND METHODS OF FABRICATING AND OPERATING THE SAME 审中-公开
标题翻译：具有自对准浮动门或充电陷阱细胞存储器电池的3D半圆形垂直NAND晶体及其制造和操作方法
公开(公告)号：WO2016053453A1
公开(公告)日：2016-04-07
申请号：PCT/US2015/042220
申请日：2015-07-27
申请人： SANDISK TECHNOLOGIES INC.
发明人： KAI, James K. , ZHANG, Yanli , CHIEN, Henry , ALSMEIER, Johann , SEROV, Andrey
IPC分类号： H01L27/115
CPC分类号： H01L27/11556 , G11C16/0408 , G11C16/0483 , G11C16/14 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L29/66666 , H01L29/66825 , H01L29/7827
摘要： A memory device includes a plurality of memory cells arranged in a string substantially perpendicular to the major surface of the substrate (10) in a plurality of device levels, at least one first select gate electrode located between the major surface of the substrate and the plurality of memory cells, at least one second select gate electrode located above the plurality of memory cells, a semiconductor channel (601) having a portion that extends vertically along a direction perpendicular to the major surface, a first memory film (54) contacting a first side of the semiconductor channel, and a second memory film (54) contacting a second side of the semiconductor channel. The second memory film is electrically isolated from the first memory film, and is located at a same level as the first memory film.
摘要翻译：存储器件包括多个存储单元，多个存储单元以多个器件级别布置成基本上垂直于衬底（10）的主表面的串，至少一个第一选择栅极位于衬底的主表面和多个器件级之间存储单元的至少一个第二选择栅极，位于所述多个存储单元上方的至少一个第二选择栅电极，具有沿垂直于所述主表面的方向垂直延伸的部分的半导体沟道（601），与第一存储单元接触的第一存储膜半导体通道的第二侧和与半导体通道的第二侧接触的第二存储膜（54）。第二存储膜与第一存储膜电隔离，并且位于与第一存储膜相同的水平。

5. 发明申请

WO2016022319A2 PROTECTIVE MATERIAL TO PREVENT SHORT CIRCUITS IN THREE-DIMENSIONAL MEMORY DEVICE 审中-公开
标题翻译：防止三维存储设备中的短路的保护材料
公开(公告)号：WO2016022319A2
公开(公告)日：2016-02-11
申请号：PCT/US2015/042302
申请日：2015-07-27
申请人： SANDISK TECHNOLOGIES INC.
发明人： YUAN, Jiahui , PACHAMUTHU, Jayavel , DONG, Yingda , ZHAO, Wei
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , G01R31/025 , G11C16/0483 , G11C29/025 , H01L21/32136 , H01L21/76224 , H01L27/0255 , H01L27/0288 , H01L27/0629 , H01L27/11519 , H01L27/11524 , H01L27/11548 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L28/20 , H01L28/40 , H01L29/16 , H01L29/42328 , H01L29/42344 , H01L29/6609 , H01L29/861
摘要： In a three-dimensional stacked non-volatile memory device, a short circuit is prevented in a select gate layer by providing a protective material such as a diode, capacitor, linear resistor or varistor between select gate lines and a remaining portion of the select gate layer. Charges which are accumulated in the select gate lines due to plasma etching are therefore prevented from discharging through the remaining portion in a short circuit path when the select gate lines are driven. The protective material can comprise a p-n diode, an n-i-n or p-i-p resistor, a thin oxide layer between doped polysilicon layers in a capacitor, or a variable-resistance material such as ZnO2 between oxide layers in a varistor.
摘要翻译：在三维堆叠式非易失性存储器件中，通过在选择栅极线之间提供诸如二极管，电容器，线性电阻器或变阻器之类的保护材料来防止选择栅极层中的短路和选择栅极层的剩余部分。因此，当选择栅极线被驱动时，由于等离子体蚀刻而累积在选择栅极线中的电荷被阻止通过短路路径中的剩余部分放电。保护材料可以包括p-n二极管，n-i-n或p-i-p电阻器，电容器中掺杂多晶硅层之间的薄氧化物层，或变阻器中氧化物层之间的可变电阻材料，例如ZnO2。

6. 发明申请

WO2014055460A3 SUPPORT LINES TO PREVENT LINE COLLAPSE IN ARRAYS 审中-公开
标题翻译：支持线，以防止阵列线阵
公开(公告)号：WO2014055460A3
公开(公告)日：2015-01-15
申请号：PCT/US2013062774
申请日：2013-09-30
申请人： SANDISK 3D LLC , LEE DONOVAN
发明人： LEE DONOVAN
IPC分类号： G11C29/44 , G11C29/04 , H01L27/06 , H01L27/115 , H01L29/78
CPC分类号： H01L29/7781 , G11C16/00 , G11C29/04 , G11C29/44 , H01L21/76224 , H01L27/0688 , H01L27/11519 , H01L27/11529 , H01L29/66825 , H01L29/7881
摘要： Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be provided to prevent the collapse of closely spaced device structures during fabrication. In one example, during fabrication of a NAND flash memory, one or more mechanical support structures may be set in place prior to performing a high aspect ratio word line etch for forming the NAND strings. The one or more mechanical support structures may comprise one or more fin supports that are arranged in a bit line direction. In another example, the one or more mechanical support structures may be developed during the word line etch for forming the NAND strings.
摘要翻译：描述了在制造NAND闪速存储器和利用具有高纵横比的紧密间隔的器件结构的其它微电子器件时防止线塌陷的方法。在一些实施例中，可以提供一个或多个机械支撑结构以防止在制造期间紧密间隔的装置结构的塌陷。在一个示例中，在制造NAND闪速存储器期间，可以在执行用于形成NAND串的高纵横比字线蚀刻之前将一个或多个机械支撑结构设置在适当位置。一个或多个机械支撑结构可以包括沿位线方向布置的一个或多个翅片支撑件。在另一示例中，可以在用于形成NAND串的字线蚀刻期间显影一个或多个机械支撑结构。

7. 发明申请

WO2014061425A1 不揮発性半導体記憶装置审中-公开
标题翻译：非挥发性半导体存储器件
公开(公告)号：WO2014061425A1
公开(公告)日：2014-04-24
申请号：PCT/JP2013/076284
申请日：2013-09-27
申请人：株式会社フローディア
发明人：谷口　泰弘 , 葛西　秀男 , 品川　裕 , 奥山　幸祐
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/336 , H01L21/8244 , H01L27/11 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C14/0063 , G11C7/18 , G11C8/16 , G11C16/04 , G11C16/0441 , G11C16/08 , G11C16/12 , G11C16/14 , G11C16/24 , G11C16/26 , H01L27/11519 , H01L27/11558 , H01L29/7881
摘要：　ビット線本数を増やすことなく、リードトランジスタの誤作動を確実に防止し得る不揮発性半導体記憶装置を提案する。不揮発性半導体記憶装置(1)では、スイッチトランジスタ(SWa,SWb)の切り替えによって、第1セル(2a)のプログラムトランジスタ(5a)に接続されてデータ書き込み用となる第2ビット線(BLN1)が、他方の第2セル(2b)にて読み出し用のビット線を兼ねつつ、データの書き込み時および消去時に電荷移動経路となるプログラムトランジスタ(5a,5b)およびイレーストランジスタ(3a,3b)を設けたことにより、ビット線本数を増やすことなく、データ書き込みや消去に用いられることにより生じてしまうリードトランジスタ(4a,4b)の誤作動を確実に防止し得る。
摘要翻译：提供了一种非易失性半导体存储装置，其可以可靠地防止读取晶体管的故障，而不增加位线数量。在非易失性半导体存储装置（1）中，使与第一单元（2a）的程序晶体管（5a）连接以便用于数据写入的第二位线（BLN1）作为位用于通过切换开关晶体管（SWa，SWb）以及在写入数据时用作电荷传输路径的编程晶体管（5a，5b）和擦除晶体管（3a，3b）在另一个第二单元（2b）中读取的线提供删除数据的时间。该配置使得可以可靠地防止在读取晶体管用于写入或删除数据时发生的读取晶体管（4a，4b）的故障，而不增加位线数量。

8. 发明申请

WO2014008419A1 STAIR STEP FORMATION USING AT LEAST TWO MASKS 审中-公开
标题翻译：使用至少两个掩模的平台步骤形成
公开(公告)号：WO2014008419A1
公开(公告)日：2014-01-09
申请号：PCT/US2013/049360
申请日：2013-07-03
申请人： MICRON TECHNOLOGY, INC.
发明人： HA, Chang, Wan , WOLSTENHOLME, Graham R. , THIMMEGOWDA, Deepak
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/32139 , H01L21/76822 , H01L21/76865 , H01L23/535 , H01L27/1052 , H01L27/11519 , H01L27/11548 , H01L27/11556 , H01L27/11565 , H01L27/11575 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.
摘要翻译：提供了使用至少两个掩模（例如存储器件）中的阶梯形成的装置和方法。一个示例性方法可以包括在导电材料上形成第一掩模以限定第一暴露区域，以及在第一暴露区域的一部分上形成第二掩模以限定第二暴露区域，第二暴露区域小于第一暴露区域区。从第二暴露区域去除导电材料。第二掩模的初始第一尺寸小于第一曝光区域的第一尺寸，并且第二掩模的初始第二尺寸是第一曝光区域的至少第二尺寸加上等于初始第一曝光区域之间的差距的距离在形成阶梯结构之后，第二掩模的尺寸和第二掩模的最终第一尺寸。

9. 发明申请

WO2013078068A1 PASSIVE DEVICES FOR 3D NON-VOLATILE MEMORY 审中-公开
标题翻译：用于3D非易失性存储器的被动设备
公开(公告)号：WO2013078068A1
公开(公告)日：2013-05-30
申请号：PCT/US2012/065374
申请日：2012-11-15
申请人： SANDISK TECHNOLOGIES, INC. , HIGASHITANI, Masaaki , RABKIN, Peter
发明人： HIGASHITANI, Masaaki , RABKIN, Peter
IPC分类号： H01L27/115 , H01L27/06 , H01L23/522 , H01L49/02
CPC分类号： H01L27/11582 , H01L27/11519 , H01L27/11531 , H01L27/11556 , H01L27/11565 , H01L27/11573 , H01L27/11575 , H01L28/87
摘要： Passive devices such as resistors and capacitors are provided for a 3D non-volatile memory device. In a peripheral area of a substrate, a passive device includes alternating layers of a dielectric (L0, L2,...,L12) such as oxide and a conductive material (L1, L3,...,L13) such as heavily doped polysilicon or metal silicide in a stack. The substrate includes one or more lower metal layers (M1) connected to circuitry. One or more upper metal layers (DO) are provided above the stack. Contact structures (2802...2814) extend from the layers of conductive material to portions of the one or more upper metal layers so that the layers of conductive material are connected to one another in parallel, for a capacitor, or serially, for a resistor, by the contact structures and the at least one upper metal layer. Additional contact structures (2906, 2908) can connect the circuitry to the one or more upper metal layers.
摘要翻译：为三维非易失性存储器件提供诸如电阻器和电容器的无源器件。在基板的周边区域中，无源器件包括诸如氧化物和导电材料（L1，L3，...，L13）的电介质（L0，L2，...，L12）的交替层，例如重掺杂堆叠中的多晶硅或金属硅化物。衬底包括连接到电路的一个或多个下金属层（M1）。在堆叠上方提供一个或多个上金属层（DO）。接触结构（2802 ... 2814）从导电材料层延伸到一个或多个上金属层的部分，使得导电材料层彼此并联连接，用于电容器或串联连接，用于电阻器，通过接触结构和至少一个上金属层。附加接触结构（2906,2908）可以将电路连接到一个或多个上金属层。

10. 发明申请

WO2012082223A3 NON-VOLATILE STORAGE SYSTEM WITH SHARED BIT LINES CONNECTED TO SINGLE SELECTION DEVICE 审中-公开
标题翻译：具有连接到单个选择设备的共享位线的非易失存储系统
公开(公告)号：WO2012082223A3
公开(公告)日：2013-04-04
申请号：PCT/US2011056146
申请日：2011-10-13
申请人： SANDISK TECHNOLOGIES INC , MOKHLESI NIMA , DUNGA MOHAN V , HIGASHITANI MASAAKI
发明人： MOKHLESI NIMA , DUNGA MOHAN V , HIGASHITANI MASAAKI
IPC分类号： H01L21/28 , H01L27/115
CPC分类号： H01L21/28273 , G11C16/0483 , H01L27/11519 , H01L27/11521
摘要： A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line.
摘要翻译：公开了一种非易失性存储系统，其包括连接到共享位线的同一块中的NAND串（或存储器单元的其它组）对。为了操作该系统，使用两条选择线，使得可以在块级选择共享位线的NAND串（或存储器单元的其它分组）。两个选择线连接到共享位线的每个NAND串（或存储器单元的其它组）的选择门。

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