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1. 发明申请

WO2018226280A1 SEPARATE DRAIN-SIDE DUMMY WORD LINES WITHIN A BLOCK TO REDUCE PROGRAM DISTURB 审中-公开
公开(公告)号：WO2018226280A1
公开(公告)日：2018-12-13
申请号：PCT/US2018/021065
申请日：2018-03-06
申请人： SANDISK TECHNOLOGIES LLC
发明人： ZHANG, Zhengyi , CHIN, Henry , DONG, Yingda
IPC分类号： G11C8/08 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/34 , H01L27/115 , G11C16/04
CPC分类号： G11C16/3459 , G11C8/08 , G11C8/12 , G11C8/14 , G11C8/16 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/24 , G11C16/3418 , G11C16/3427 , H01L27/11582
摘要： Disturbs are reduced during programming and read operations for drain-side memory cells in a string by controlling dummy word line portions separately in selected and unselected sub-blocks. One or more of the dummy word line layers are separated so that they can be driven with different voltages. This allows the channel gradient to be optimized to reduce the likelihood of disturbs. In another aspect, a stack of alternating conductive and dielectric layers is formed in two parts, with lower pillars which comprise select gate transistors, source-side dummy memory cells and data memory cells, below upper pillars which comprise drain-side dummy memory cells and select gate transistors. The upper pillars are relatively narrow to provide a more compact structure. Moreover, the centerline of some upper pillars can be offset from the centerline of corresponding lower pillars to provide room for an isolation region.

2. 发明申请

WO2017209812A1 NON-VOLATILE MEMORY WITH CUSTOMIZED CONTROL OF INJECTION TYPE OF DISTURB DURING READ OPERATIONS 审中-公开
标题翻译：非易失性存储器，可在读取操作期间自定义控制注入类型的干扰
公开(公告)号：WO2017209812A1
公开(公告)日：2017-12-07
申请号：PCT/US2017/018758
申请日：2017-02-21
申请人： SANDISK TECHNOLOGIES LLC
发明人： CHEN, Hong-Yan , DONG, Yingda
IPC分类号： G11C11/56 , G11C16/08 , G11C16/28 , G11C16/34
CPC分类号： G11C16/26 , G11C8/08 , G11C11/5642 , G11C16/04 , G11C16/0466 , G11C16/08 , G11C16/28 , G11C16/3418 , G11C16/3427
摘要： A non-volatile memory system includes one or more control circuits configured to read memory cells. The reading of the programmed memory cells includes applying one or more voltages to perform boosting of a channel region associated with unselected memory cells, allowing the boosting of the channel region for a portion of time while applying the one or more voltages, preventing/interrupting the boosting of the channel region while applying the one or more voltages for a duration of time based on position of a memory cell selected for verification, applying a compare signal to the memory cell selected for reading, and performing a sensing operation for the memory cell selected for reading in response to the compare signal.
摘要翻译：非易失性存储器系统包括被配置为读取存储器单元的一个或多个控制电路。编程的存储器单元的读取包括施加一个或多个电压以执行与未选中的存储器单元相关联的沟道区域的升压，允许在施加一个或多个电压的同时升高沟道区域的一部分时间，防止/中断在选择用于验证的存储单元的位置的基础上，在施加一个或多个电压一段时间的同时施加一个或多个电压，向选择用于读取的存储单元施加比较信号，并且对所选择的存储单元执行感测操作用于响应比较信号进行读取。

3. 发明申请

WO2017165173A1 SOLID STATE STORAGE SYSTEM WITH LATENCY MANAGEMENT MECHANISM AND METHOD OF OPERATION THEREOF 审中-公开
标题翻译：具有延迟管理机构的固态存储系统及其操作方法
公开(公告)号：WO2017165173A1
公开(公告)日：2017-09-28
申请号：PCT/US2017/022608
申请日：2017-03-15
申请人： SMART MODULAR TECHNOLOGIES, INC.
发明人： LIN, Fong-Long , LIN, Shu-Cheng
IPC分类号： G06F11/14 , G06F11/30
CPC分类号： G06F11/1044 , G11C16/0483 , G11C16/3427
摘要： A solid state storage system (100), and method (800) of operation thereof, including: a system interface (102) configured to receive host commands (105); a controller (108), coupled to the system interface (102), configured to identify frequently read data blocks (126) from the host commands (105); a non-volatile memory (124), coupled to the controller (108), configured for access of the frequently read data blocks (126); an error correction code unit (130), coupled to the controller (108), configured to provide health monitor parameters (118) for the frequently read data blocks (126) verified by the controller (108); and a redundant frequently read data (RFRD) area (902), coupled to the error correction code unit (130), configured to transfer a recovered data (624) from the frequently read data blocks (126).
摘要翻译：一种固态存储系统（100）及其操作方法（800），包括：被配置为接收主机命令（105）的系统接口（102）; 耦合到所述系统接口（102）的控制器（108），其被配置为从所述主机命令（105）中识别频繁读取的数据块（126）; 耦合到所述控制器（108）的非易失性存储器（124），所述非易失性存储器被配置用于访问所述频繁读取的数据块（126）; 耦合到所述控制器（108）的错误校正码单元（130），被配置为为由所述控制器（108）验证的所述频繁读取的数据块（126）提供健康监视参数（118）; 和耦合到纠错码单元（130）的冗余频繁读取数据（RFRD）区域（902），其被配置为从频繁读取的数据块（126）传送恢复的数据（624）。

4. 发明申请

WO2017117007A1 NAND FLASH STORAGE ERROR MITIGATION SYSTEMS AND METHODS 审中-公开
标题翻译： NAND闪存存储错误缓解系统和方法
公开(公告)号：WO2017117007A1
公开(公告)日：2017-07-06
申请号：PCT/US2016/068370
申请日：2016-12-22
申请人： ALIBABA GROUP HOLDING LIMITED
发明人： LI, Shu
IPC分类号： G06F12/00
CPC分类号： G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/00 , G06F12/0246 , G06F2212/1016 , G06F2212/1036 , G06F2212/403 , G06F2212/7202 , G11C16/0483 , G11C16/3427 , G11C16/349 , G11C29/52
摘要： The present invention facilitates efficient and effective information storage device operations. In one embodiment, a storage device comprises: a plurality of storage cells configured to store information; a plurality of word lines coupled to the plurality of storage cells; and a plurality of bit lines coupled to the plurality of storage cells, wherein the plurality of bit lines are configured to enable writing of the plurality of storage cells and the plurality of word lines are configured to enable reading of the storage cells. The information is configured in a plurality of information first type portions (e.g., codewords) which respectively include a plurality of second type portions (e.g., data chunks), and the information is stored by the plurality of storage cells in a distribution that ensures two second type portions from a respective first type portion are not stored in storage cells adjacent to one another.
摘要翻译：本发明有利于高效和有效的信息存储设备操作。在一个实施例中，一种存储设备包括：多个存储单元，其被配置为存储信息; 多个字线，耦合到所述多个存储单元; 以及耦合到所述多个存储单元的多个位线，其中所述多个位线被配置为使得能够写入所述多个存储单元，并且所述多个字线被配置为能够读取所述存储单元。信息被配置在分别包括多个第二类型部分（例如，数据块）的多个信息第一类型部分（例如，码字）中，并且信息由多个存储单元存储在确保两个来自相应第一类型部分的第二类型部分不存储在彼此相邻的存储单元中。

5. 发明申请

WO2017058347A1 MULTI-GATE NOR FLASH THIN-FILM TRANSISTOR STRINGS ARRANGED IN STACKED HORIZONTAL ACTIVE STRIPS WITH VERTICAL CONTROL GATES 审中-公开
标题翻译：多栅极或闪烁的薄膜晶体管阵列安装在垂直控制门的堆叠水平有源条中
公开(公告)号：WO2017058347A1
公开(公告)日：2017-04-06
申请号：PCT/US2016/044336
申请日：2016-07-27
申请人： HARARI, Eli
发明人： HARARI, Eli
IPC分类号： G11C16/04 , G11C11/34 , G11C16/06 , H01L29/792
CPC分类号： G11C16/3431 , G11C11/5628 , G11C11/5635 , G11C16/0416 , G11C16/0466 , G11C16/0483 , G11C16/0491 , G11C16/10 , G11C16/26 , G11C16/28 , G11C16/3427 , H01L21/28282 , H01L27/0688 , H01L27/11565 , H01L27/11573 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： Multi-gate NOR flash thin-film transistor (TFT) string arrays ("multi-gate NOR string arrays") are organized as stacks of horizontal active strips running parallel to the surface of a silicon substrate, with the TFTs in each stack being controlled by vertical local word-lines provided along one or both sidewalls of the stack of active strips. Each active strip includes at least a channel layer formed between two shared source or drain layers. Data storage in the TFTs of an active strip is provided by charge-storage elements provided between the active strip and the control gates provided by the adjacent local word-lines. Each active strip may provide TFTs that belong to one or two NOR strings, depending on whether one or both sides of the active strip are used.
摘要翻译：多栅极NOR闪存薄膜晶体管（TFT）串阵列（“多栅极NOR串阵列”）被组织为平行于硅衬底的表面延伸的水平有源条的堆叠，每个堆叠中的TFT被控制通过沿着活动条的堆叠的一个或两个侧壁设置的垂直的局部字线。每个有源条带至少包括在两个共用源极或漏极层之间形成的沟道层。有源条带的TFT中的数据存储由提供在有源条和由相邻本地字线提供的控制栅之间的电荷存储元件提供。取决于使用活动条的一侧还是两侧，每个活动条可以提供属于一个或两个NOR字符串的TFT。

6. 发明申请

WO2016154144A1 SONOS BYTE-ERASABLE EEPROM 审中-公开
标题翻译： SONOS字节可擦除EEPROM
公开(公告)号：WO2016154144A1
公开(公告)日：2016-09-29
申请号：PCT/US2016/023476
申请日：2016-03-21
申请人： NEO SEMICONDUCTOR, INC.
发明人： HSU, Fu-Chang
IPC分类号： G11C5/06 , G11C16/04
CPC分类号： G11C16/10 , G11C16/0466 , G11C16/3427
摘要： A SONOS byte-erasable EEPROM is disclosed. In one aspect, an apparatus includes a plurality of SONOS memory cells forming an EEPROM memory array. The apparatus also includes a controller that generates bias voltages to program and erase the memory cells. The controller performs a refresh operation when programming selected memory cells to reduce write-disturb on unselected memory cells to prevent data loss.
摘要翻译：公开了一种SONOS字节可擦除EEPROM。一方面，一种装置包括形成EEPROM存储器阵列的多个SONOS存储单元。该装置还包括产生偏置电压以对存储器单元进行编程和擦除的控制器。当编程所选存储单元时，控制器执行刷新操作，以减少未选择的存储单元的写入干扰，以防止数据丢失。

7. 发明申请

WO2016089474A1 PARTIAL BLOCK ERASE FOR DATA REFRESHING 审中-公开
标题翻译：数据刷新的部分块删除
公开(公告)号：WO2016089474A1
公开(公告)日：2016-06-09
申请号：PCT/US2015/054459
申请日：2015-10-07
申请人： SANDISK TECHNOLOGIES INC.
发明人： LIANG, Guirong , ZHOU, Zhenming , HIGASHITANI, Masaaki
IPC分类号： G11C11/56 , G11C16/34 , G11C16/04
CPC分类号： G06F11/1068 , G06F11/1048 , G11C5/063 , G11C11/5628 , G11C16/0483 , G11C16/14 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C16/349 , G11C2211/5644 , H01L27/11524
摘要： Systems and methods for performing partial block erase operations on a subset of word lines within a memory array prior to performing data refreshing or open-block programming are described. In some cases, data stored in memory cells connected to a word line with a fail bit count above an error threshold (e.g., more than two bit errors per page or more than three bit errors per word line) may be refreshed by performing a read operation on the memory cells, generating corrected data for the memory cells, performing a partial block erase operation on one or more word lines including the word line, and then writing the corrected data into the memory cells. The one or more word lines may include the word line with the fail bit count above the error threshold and an adjacent word line that is adjacent to the word line.
摘要翻译：描述了在执行数据刷新或开放块编程之前在存储器阵列内的字线子集上执行部分块擦除操作的系统和方法。在一些情况下，可以通过执行读取来刷新存储在具有错误位计数高于误差阈值的字线的存储器单元中的数据（例如，每页多于两个位错误或每个字线多于三位错误）对存储器单元进行操作，产生用于存储单元的校正数据，对包括字线的一条或多条字线执行部分块擦除操作，然后将校正数据写入存储单元。一个或多个字线可以包括具有高于误差阈值的故障位计数的字线和与字线相邻的相邻字线。

8. 发明申请

WO2016057202A1 PROGRAMMING OF DRAIN SIDE WORD LINE TO REDUCE PROGRAM DISTURB AND CHARGE LOSS 审中-公开
标题翻译：排水侧边线编程减少程序干扰和充电损失
公开(公告)号：WO2016057202A1
公开(公告)日：2016-04-14
申请号：PCT/US2015/051275
申请日：2015-09-21
申请人： SANDISK TECHNOLOGIES INC.
发明人： YUAN, Jiahui , DONG, Yingda , LU, Ching-Huang , ZHAO, Wei
IPC分类号： G11C11/56 , G11C16/04 , G11C16/34
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/3427 , G11C16/3459 , G11C2211/5621 , G11C2211/5648
摘要： Techniques are provided for programming the memory cells of a drain-side edge word line of a set of word lines before programming memory cells of any other word line of the set. Pass voltages applied to the other word lines act as stress pulses which redistribute holes in the charge-trapping material of the memory cells of the other word lines to reduce short-term charge loss and downshifting of the threshold voltage. Additionally, one or more initial program voltages used for the drain-side edge word line are relatively low and also act as stress pulses. The memory cells of the drain-side edge word line are programmed to a narrower Vth window than the memory cells of the other word lines. This compensates for a higher level of program disturb of erased state memory cells of the drain-side edge word line due to reduced channel boosting.
摘要翻译：提供了在编程集合的任何其他字线的存储器单元之前对一组字线集合的漏极边缘字线的存储器单元进行编程的技术。施加到其它字线的通过电压作为应力脉冲，其重新分配其它字线的存储单元的电荷捕获材料中的空穴，以减少阈值电压的短期电荷损耗和降档。此外，用于漏极侧边缘字线的一个或多个初始编程电压相对较低并且还用作应力脉冲。漏极侧边缘字线的存储单元被编程到比其它字线的存储单元窄的Vth窗口。这由于减少的信道增强而补偿了漏极侧边缘字线的擦除状态存储单元的编程干扰的较高水平。

9. 发明申请

WO2016039975A1 CONTROLLING PASS VOLTAGES TO MINIMIZE PROGRAM DISTURB IN CHARGE-TRAPPING MEMORY 审中-公开
标题翻译：控制电源电压以最小化充电跟踪存储器中的程序干扰
公开(公告)号：WO2016039975A1
公开(公告)日：2016-03-17
申请号：PCT/US2015/046679
申请日：2015-08-25
申请人： SANDISK TECHNOLOGIES INC.
发明人： DONG, Yingda , CHEN, Hong-Yan
IPC分类号： G11C16/34 , G11C11/56 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0466 , G11C16/0483 , G11C16/3427 , G11C16/3459
摘要： Techniques are provided for preventing program disturb of unselected memory cells during programming of a selected memory cell in a NAND string which includes a continuous charge-trapping layer, either in a two-dimensional or three-dimensional configuration. In such a NAND string, regions between the memory cells can be inadvertently programmed as parasitic cells due to the program voltage and pass voltages on the word lines. For programmed cells, an upshift in threshold voltage due to a parasitic cell can be avoided by providing a higher pass voltage on an adjacent later-programmed word line than on an adjacent previously-programmed word line. For erased cells, an upshift in threshold voltage due to the parasitic cells can be reduced by progressively lowering the pass voltage on the adjacent later-programmed word line. The lowering can occur when memory cells of a lowest target data state complete programming.
摘要翻译：提供技术用于防止在包括二维或三维配置的连续电荷俘获层的NAND串中的所选存储单元的编程期间防止未选择存储单元的程序干扰。在这种NAND串中，由于程序电压和字线上的通过电压，存储单元之间的区域可能被无意地编程为寄生单元。对于编程单元，通过在相邻的后面编程的字线上提供比在相邻的预先编程的字线上更高的通过电压，可以避免由寄生电池引起的阈值电压升档。对于已擦除的单元，可以通过逐渐降低相邻的后编程字线上的通过电压来降低由寄生电池引起的阈值电压升档。当最低目标数据状态的存储单元完成编程时，可能会发生降低。

10. 发明申请

WO2016025167A1 MULTI-PULSE PROGRAMMING CYCLE OF NON-VOLATILE MEMORY FOR ENHANCED DE-TRAPPING 审中-公开
标题翻译：用于增强脱钩的非易失性存储器的多脉冲编程周期
公开(公告)号：WO2016025167A1
公开(公告)日：2016-02-18
申请号：PCT/US2015/042504
申请日：2015-07-28
申请人： SANDISK TECHNOLOGIES INC.
发明人： KOH, Yee Lih , KUO, Tien-Chien , MUI, Man Lung , LEE, Juan Carlos
IPC分类号： G11C11/56 , G11C16/34
CPC分类号： G11C11/5628 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C16/3427 , G11C16/3459 , G11C2211/5621 , G11C2211/5648
摘要： When writing a multi-state non-volatile memory, a de-trapping operation is included in the programming cycle. To reduce the performance penalty of including a de-trapping operation, the programming cycle of a single series of increasing pulses alternating with verify operations is replaced with a cycle including a pulse from each of two or more staircases, where each staircase is for a corresponding subset of the data states. After the multiple pulses, but before the following verify, a de-trapping operation is inserted in the programming cycle.
摘要翻译：在写入多状态非易失性存储器时，编程周期中包含解除捕获操作。为了降低包括解除捕获操作的性能损失，与验证操作交替的单个增加脉冲序列的编程周期被包括来自两个或多个楼梯中的每一个的脉冲的周期替换，其中每个阶梯用于相应的数据状态的子集。在多个脉冲之后，但在进行以下验证之前，在编程周期中插入解除捕获操作。

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