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1. 发明申请

WO2009082637A1 REGULATION OF SOURCE POTENTIAL TO COMBAT CELL SOURCE IR DROP 审中-公开
标题翻译：源电位对调节细胞来源红细胞减少的调节
公开(公告)号：WO2009082637A1
公开(公告)日：2009-07-02
申请号：PCT/US2008/086694
申请日：2008-12-12
申请人： SANDISK CORPORATION , LEE, Dana , MOKHLESI, Nima , SEKAR, Deepak Chandra
发明人： LEE, Dana , MOKHLESI, Nima , SEKAR, Deepak Chandra
IPC分类号： G11C16/30
CPC分类号： G11C16/30
摘要： Techniques are presented for dealing with possible source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits of a non-volatile memory. The error is caused by a voltage drop across the resistance of the source path to the chip's ground when current flows. For this purpose, the memory device includes a source potential regulation circuit, including an active circuit element having a first input connected to a reference voltage and having a second input connected as a feedback loop that is connectable to the aggregate node from which the memory cells of a structural block have their current run to ground. A variation includes a non-linear resistive element connectable between the aggregate node and ground.
摘要翻译：提出用于处理可能的源极偏置的技术是由非易失性存储器的读/写电路的接地回路中的非零电阻引入的误差。误差是由电流流动时芯片接地源极路径的电阻上的电压降引起的。为此，存储器件包括源极电位调节电路，其包括有源电路元件，该有源电路元件具有连接到参考电压的第一输入端，并且具有连接到反馈回路的第二输入端，该反馈回路可连接到汇集节点，存储器单元的结构块现在已经跑到地面上了。变化包括可在聚集节点和地之间连接的非线性电阻元件。

2. 发明申请

WO2008121577A1 SOFT BIT DATA TRANSMISSION FOR ERROR CORRECTION CONTROL IN NON-VOLATILE MEMORY 审中-公开
标题翻译：用于非易失性存储器中的错误校正控制的软位数据传输
公开(公告)号：WO2008121577A1
公开(公告)日：2008-10-09
申请号：PCT/US2008/057722
申请日：2008-03-20
申请人： SANDISK CORPORATION , MOKHLESI, Nima , CHIN, Henry , ZHAO, Dengtao
发明人： MOKHLESI, Nima , CHIN, Henry , ZHAO, Dengtao
IPC分类号： G11C11/56 , G06F11/10
CPC分类号： G11C11/5642 , G06F11/1068 , G11C7/1006 , G11C16/0483 , G11C16/26 , G11C29/00 , G11C2211/5634
摘要： Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Soft data bits are read from the memory if the decoding fails to converge. Initial reliability metric values are provided after receiving the hard read results and at each phase of the soft bit operation(s). In one embodiment, a second soft bit is read from the memory using multiple subsets of soft bit compare levels. While reading at the second subset of compare levels, decoding can be performed based on the first subset data.
摘要翻译：使用迭代概率解码对存储在非易失性存储器中的数据进行解码。可以使用诸如低密度奇偶校验码的纠错码。在一种方法中，初始可靠性度量（诸如对数似然比）被用于解码一组非易失性存储元件的感测状态。解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。如果解码失败，则从存储器读取软数据位。在接收到硬读取结果之后以及在软位操作的每个阶段提供初始可靠性度量值。在一个实施例中，使用软比特比较级的多个子集从存储器读取第二软比特。在比较电平的第二子集读取时，可以基于第一子集数据执行解码。

3. 发明申请

WO2008083196A2 MARGINED NEIGHBOR READING FOR NON-VOLATILE MEMORY READ OPERATIONS INCLUDING COUPLING COMPENSATION 审中-公开
标题翻译：附带阅读非易失性存储器阅读操作，包括联合补偿
公开(公告)号：WO2008083196A2
公开(公告)日：2008-07-10
申请号：PCT/US2007/088899
申请日：2007-12-27
申请人： SANDISK CORPORATION , MOKHLESI, Nima
发明人： MOKHLESI, Nima
IPC分类号： G11C16/26 , G11C16/34 , G11C11/56
CPC分类号： G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C29/00 , G11C2211/5646
摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To account for this coupling, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell. When reading the adjacent cell to determine the appropriate compensation, margined read voltages can be used.
摘要翻译：存在于非易失性存储单元的浮动栅极（或其他电荷存储元件）上的表观电荷的变化可能发生，因为基于存储在相邻浮动栅极（或其它相邻电荷存储元件）中的电荷的电场的耦合）。在不同时间编程的相邻存储器单元组之间最明显地出现该问题。为了解决这种耦合，特定存储器单元的读取过程将向相邻存储器单元提供补偿，以便减少相邻存储单元对特定存储单元的耦合效应。当读取相邻单元以确定适当的补偿时，可以使用边缘读取电压。

4. 发明申请

WO2008083136A2 RESISTANCE SENSING AND COMPENSATION FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：非易失性存储器的电阻检测和补偿
公开(公告)号：WO2008083136A2
公开(公告)日：2008-07-10
申请号：PCT/US2007/088786
申请日：2007-12-24
申请人： SANDISK CORPORATION , MOKHLESI, Nima , CERNEA, Raul-adrian
发明人： MOKHLESI, Nima , CERNEA, Raul-adrian
CPC分类号： G11C11/5642 , G11C11/5628 , G11C16/0483 , G11C16/26
摘要： When reading data from a non-volatile storage element that is part of a group of connected non-volatile storage elements, resistance information is measured for the group. One or more read parameters are set based on the measured resistance information. The read process is then performed using the one or more parameters.
摘要翻译：当从作为一组连接的非易失性存储元件的一部分的非易失性存储元件读取数据时，测量该组的电阻信息。根据测量的电阻信息设置一个或多个读取参数。然后使用一个或多个参数执行读取过程。

5. 发明申请

WO2005081318A1 SHIELD PLATE FOR LIMITING CROSS COUPLING BETWEEN FLOATING GATES 审中-公开
标题翻译：用于限制浮动闸门之间的交叉耦合的屏蔽板
公开(公告)号：WO2005081318A1
公开(公告)日：2005-09-01
申请号：PCT/US2005/004157
申请日：2005-02-09
申请人： SANDISK CORPORATION , MOKHLESI, Nima , LUTZE, Jeffrey, W.
发明人： MOKHLESI, Nima , LUTZE, Jeffrey, W.
IPC分类号： H01L27/115
CPC分类号： G11C11/5642 , G11C11/5628 , G11C2211/5621 , H01L27/115 , H01L27/11521 , H01L29/7887
摘要： A memory system is disclosed that includes a set of non-volatile storage elements. Each of said non-volatile storage elements includes source/drain regions at opposite sides of a channel in a substrate and a floating gate stack above the channel. The memory system also includes a set of shield plates positioned between adjacent floating gate stacks and electrically connected to the source/drain regions for reducing coupling between adjacent floating gates. The shield plates are selectively grown on the active areas of the memory without being grown on the inactive areas. In one embodiment, the shield plates are epitaxially grown silicon positioned above the source/drain regions.
摘要翻译：公开了一种包括一组非易失性存储元件的存储器系统。所述非易失性存储元件中的每一个包括在衬底中的沟道的相对侧处的源极/漏极区域和在沟道上方的浮动栅极堆叠。存储器系统还包括位于相邻浮置栅极堆叠之间并且电连接到源极/漏极区域的一组屏蔽板，用于减少相邻浮动栅极之间的耦合。屏蔽板选择性地生长在存储器的有效区域上，而不会在非活动区域上生长。在一个实施例中，屏蔽板是位于源极/漏极区上方的外延生长的硅。

6. 发明申请

WO2008134253A1 REDUCING POWER CONSUMPTION DURING READ OPERATIONS IN NON-VOLATILE STORAGE 审中-公开
标题翻译：在非易失存储器中阅读操作期间降低功耗
公开(公告)号：WO2008134253A1
公开(公告)日：2008-11-06
申请号：PCT/US2008/060630
申请日：2008-04-17
申请人： SANDISK CORPORATION , SEKAR, Deepak, Chandra , MOKHLESI, Nima , SO, Hock, C.
发明人： SEKAR, Deepak, Chandra , MOKHLESI, Nima , SO, Hock, C.
IPC分类号： G11C11/56 , G11C16/04 , G11C16/26
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C16/3418 , G11C16/3459 , G11C2211/5621 , G11C2211/5634 , G11C2211/5648 , G11C2211/565
摘要： Power consumption in a non-volatile storage device is reduced by providing reduced read pass voltages on unselected word lines during a read operation. A programming status of one or more unselected word lines which are after a selected word line on which storage elements are being read is checked to determine whether the unselected word lines contain programmed storage elements. When an unprogrammed word line is identified, reduced read pass voltages are provided on that word line and other word lines which are after that word line in a programming order. The programming status can be determined by a flag stored in the word line, for instance, or by reading the word line at the lowest read state. The unselected word lines which are checked can be predetermined in a set of word lines, or determined adaptively based on a position of the selected word line.
摘要翻译：在读取操作期间通过在未选择的字线上提供减小的读取通过电压来减少非易失性存储设备中的功耗。检查在其上正在读取存储元件的所选字线之后的一个或多个未选字线的编程状态，以确定未选择的字线是否包含编程的存储元件。当识别出未编程的字线时，在该字线和在该字线之后的编程顺序中的其它字线提供减小的读通道电压。编程状态可以通过例如存储在字线中的标志来确定，或者通过在最低读取状态下读取字线来确定。被检查的未选择的字线可以在一组字线中预先确定，或者基于所选字线的位置自适应地确定。

7. 发明申请

WO2008115874A1 ADJUSTING RESISTANCE OF NON-VOLATILE MEMORY USING DUMMY MEMORY CELLS 审中-公开
标题翻译：使用DUMMY MEMORY CELLS调节非易失性记忆电阻
公开(公告)号：WO2008115874A1
公开(公告)日：2008-09-25
申请号：PCT/US2008/057245
申请日：2008-03-17
申请人： SANDISK CORPORATION , CHEN, Henry , MOKHLESI, Nima , ZHAO, Dengtao
发明人： CHEN, Henry , MOKHLESI, Nima , ZHAO, Dengtao
IPC分类号： G11C16/10 , G11C11/56 , G11C16/04
CPC分类号： G11C11/5628 , G11C7/14 , G11C16/0483 , G11C16/349
摘要： In some non-volatile storage systems, a block of data memory cells is manufactured with a dummy word line at the bottom of the block, at the top of the block, and/or at other locations. By selectively programming memory cells on the dummy word line(s), the resistances associated with the data memory cells can be changed to account for different programmed data patterns.
摘要翻译：在一些非易失性存储系统中，在块的底部，块的顶部和/或其他位置处制造具有伪字线的数据存储单元块。通过选择性地编程虚拟字线上的存储器单元，可以改变与数据存储单元相关联的电阻以考虑不同的编程数据模式。

8. 发明申请

WO2008048812A1 FABRICATING NON-VOLATILE MEMORY WITH DUAL VOLTAGE SELECT GATE STRUCTURE 审中-公开
标题翻译：用双电压门控结构制造非易失性存储器
公开(公告)号：WO2008048812A1
公开(公告)日：2008-04-24
申请号：PCT/US2007/080745
申请日：2007-10-08
申请人： SANDISK CORPORATION , MOKHLESI, Nima , HIGASHITANI, Masaaki
发明人： MOKHLESI, Nima , HIGASHITANI, Masaaki
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/423 , G11C16/04
CPC分类号： H01L21/28273 , G11C11/5628 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A select gate structure for a non-volatile storage system include a select gate and a coupling electrode which are independently drivable. The coupling electrode is adjacent to a word line in a NAND string and has a voltage applied which reduces gate induced drain lowering (GIDL) program disturb of an adjacent unselected non-volatile storage element. In particular, an elevated voltage can be applied to the coupling electrode when the adjacent word line is used for programming. A reduced voltage is applied when a non-adjacent word line is used for programming. The voltage can also be set based on other programming criterion. The select gate is provided by a first conductive region while the coupling electrode is provided by a second conductive region formed over, and isolated from, the first conductive region.
摘要翻译：用于非易失性存储系统的选择栅极结构包括独立驱动的选择栅极和耦合电极。耦合电极与NAND串中的字线相邻，并且具有施加的电压，其减小相邻未选择的非易失性存储元件的栅极引起的漏极降低（GIDL）编程干扰。特别地，当相邻字线用于编程时，可以将高电压施加到耦合电极。当使用非相邻字线进行编程时，施加降低的电压。电压也可以根据其他编程标准设定。选择栅极由第一导电区域提供，而耦合电极由形成在第一导电区域上并与之隔离的第二导电区域提供。

9. 发明申请

WO2007149676A2 METHOD FOR OPERATING NON-VOLATILE MEMORY USING TEMPERATURE COMPENSATION OF VOLTAGES OF UNSELECTED WORD LINES AND SELECT GATES 审中-公开
标题翻译：使用不受限制的字线和选择门的电压的温度补偿来操作非易失性存储器的方法
公开(公告)号：WO2007149676A2
公开(公告)日：2007-12-27
申请号：PCT/US2007/069709
申请日：2007-05-25
申请人： SANDISK CORPORATION , MOKHLESI, Nima , ZHAO, Dengtao
发明人： MOKHLESI, Nima , ZHAO, Dengtao
CPC分类号： G11C16/0483 , G11C7/04 , G11C11/5642 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C16/3459 , G11C2211/5621
摘要： Reading and verify operations are performed on non-volatile storage elements using temperature-compensated read voltages for unselected word lines, and/or for select gates such as drain or source side select gates of a NAND string. In one approach, while a read or verify voltage is applied to a selected word line, temperature-compensated read voltages are applied to unselected word lines and select gates. Word lines which directly neighbor the selected word line can receive a voltage which is not temperature compensated, or which is temperature-compensated to a reduced degree. The read or verify voltage applied to the selected word line can also be temperature-compensated. The temperature compensation may also account for word line position.
摘要翻译：使用非选择字线的温度补偿读取电压和/或用于NAND串的漏极或源极选择栅极的选择栅极对非易失性存储元件执行读取和验证操作。在一种方法中，当读取或验证电压被施加到所选择的字线时，温度补偿的读取电压被施加到未选择的字线并选择门。直接与所选字线相邻的字线可以接收不被温度补偿的电压，或者被降低程度的温度补偿。施加到所选字线的读取或验证电压也可以进行温度补偿。温度补偿也可以说明字线位置。

10. 发明申请

WO2005073977A3 VARIABLE CURRENT SINKING FOR COARSE/FINE PROGRAMMING OF NON-VOLATILE MEMORY 审中-公开
公开(公告)号：WO2005073977A3
公开(公告)日：2005-08-11
申请号：PCT/US2005/002208
申请日：2005-01-25
申请人： SANDISK CORPORATION , GUTERMAN, Daniel, C. , MOKHLESI, Nima , FONG, Yupin
发明人： GUTERMAN, Daniel, C. , MOKHLESI, Nima , FONG, Yupin
IPC分类号： G11C11/56
摘要： A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.

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